JP2009111306A - Electronic device with josephson junction, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming an electronic device with a Josephson junction, which is not dependent on process conditions and connection conditions, namely pattern, of a niobium electrode and to provide an electric device with a highly reliable Josephson junction formed by this method. <P>SOLUTION: Hydrogen in niobium film and under niobium interconnection is emitted to obtain a sufficiently low concentration or hydrogen movement from Josephson junction electrode niobium is restricted. Thus, a fixed hydrogen concentration is ensured and thereby bonding property in accordance with a design value is achieved. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic device having a Josephson junction and a manufacturing method thereof, and more particularly, to an electronic device having a large effect when applied to a superconducting integrated circuit device and a manufacturing method thereof.

  In a highly integrated electronic device, it is necessary to keep the characteristic variation of elements constituting the device small and within a certain range. A superconducting Josephson element is required to have a manufacturing process in which the critical current value of a Josephson junction designed to have the same size does not vary beyond an allowable range. Up to now, it has been considered that etching is one of the biggest factors that determine this variation, and plasma etching techniques that can transfer patterns with accurate shapes and dimensions are also being studied. This is a case where the critical current values of a large number of junctions vary as a whole, and it has been reported that a variation (standard deviation) of 1.4% can be achieved with a junction of 0.93 square microns (see Non-Patent Document 1).

  In addition, Tolpygo et al. Reported a phenomenon in which only a small number of large junctions deviate from the average value, not the variation of the entire critical current value of many junctions (see Non-Patent Document 2). Even if a small number of junctions greatly exceed the allowable range, it becomes difficult to realize a large-scale circuit in which a large number of junctions are integrated, so this is considered to be a more serious problem at this time. They say that the cause of the variation is a change during the manufacturing process, that is, the possibility of deterioration in a process using plasma, such as a film forming apparatus or an etching apparatus.

US Pat. No. 7,081,417 Japanese Patent Application No. 2003-183879 Japanese Patent Application No. 2004-183879 H. Akaike, Y. Kitagawa, T. Satoh, K. Hinode, S. Nagasawa, and M. Hidaka, “Nb / AlOx / Nb junctions fabricated using ECR plasma etching”, Physica C 412-414 (2004), p. 1442-1446. S.K. Tolpygo, D. Amparo, A. Kirichenko, and D. Yohannes, “Plasma Process-Induced Damage to Josephson Junctions in Superconducting Integrated Circuits”, Extended Abstract of 11th International Superconductive Electronics Conference (2007), Publication Number O-101 E. Schroader, Z. Naturforsch. 12a, 247 (1957), p.247 G.C.Rauch, R.M.Rose, J. Wulff: Less-Common Metals 8, (1965), p.99 NM Jisrawi, MW Ruckman, TR Thurstion, G. Reisfeld, M. Weinert, and M. Strongin, “Reversible depression in the Tc of thin Nb films due to enhanced hydrogen absorption,” Phys. Rev. B58, (1998), p. .6585 G. Alefeld and J. Volkl, “Hydrogen in Metals I, II,” Springer-Verlag, (1978), pp.321-348 Y. Fukai, “The Metal-Hydrogen System”, Springer-Verlag, (1992), pp.207-299 "Metal Data Book", edited by the Japan Institute of Metals, Maruzen, (1993), pp.20-25

The present inventors have also observed and examined fluctuations and variations in the Josephson junction critical current value that are considered to be equivalent to those disclosed in Non-Patent Document 2 described above. The summary of the study results will be described below.
The distribution of critical current values at 1000 junctions measured with the same test pattern as described in this document is shown as a histogram in FIG. The 1000 junctions are designed to have the same dimensions and therefore the same critical current value. The Josephson element used here has a junction of 3.0 μm □ and a critical current value J _C of 2.5 kA / cm ² . Most of the 1000 junctions (99% or more) have a critical current value of ± several percent around the average value, but there are always a small number of those that deviate greatly (about 20%).

Another example will be described with reference to FIG. This is an example of the distribution of 1000 critical current values, each of two types of junctions (identified by STD and CC symbols) with the same junction but a slightly different wiring. What is written as STD is that of FIG. The Josephson element used here has a junction of 3.0 μm □ and a critical current value J _C of 2.5 kA / cm ² . Conventionally, junctions that are not distinguished by design and are considered to have the same critical current value show significantly different critical current values beyond the range of their variations.

  These two examples show that there are very few junctions with large critical current values, and that there are differences in the critical current values depending on the way of wiring connection even if the junctions are the same. The distribution of critical current values of actual circuit elements is presumed to be distributed in a very wide range as schematically shown in FIG. 14 (because there are more types of connection methods). If the characteristic values of circuit elements vary over a wide range exceeding 10% even with a very small number, it becomes very difficult to produce a large-scale integrated circuit in which several thousand to several tens of thousands of circuit elements are integrated. Therefore, in order to realize a large-scale integrated circuit, it is indispensable to suppress such a variation in circuit elements to a narrow range. The object of the present invention is to suppress such variations by making some improvements in the process or device structure.

  In the above-mentioned Non-Patent Document 2, it is estimated that the critical current fluctuation is caused by the plasma process. However, according to the study by the present inventors, it has been found that the root cause of the fluctuation is that hydrogen is mixed in niobium, which is an electrode material of the device, and a concentration difference depending on the location can be formed in the device. Since the superconducting properties of the niobium electrode change according to the hydrogen concentration, it was found that the change in the hydrogen concentration directly causes the fluctuation of the superconducting critical current value. It has been found that the concentration of mixed hydrogen differs depending on the niobium film deposition apparatus, and also depends on the film deposition conditions and usage conditions. Also, hydrogen may enter the niobium electrode and hydrogen may exit from the niobium electrode in processes other than film formation, and it depends on the process conditions and the connection condition of the niobium electrode (pattern dependence). It has been found that there is an intricate mechanism that makes this phenomenon look complicated.

  An object of the present invention is to provide a Josephson junction having a critical current value as designed, which is not dependent on process conditions and connection conditions of niobium electrodes, that is, patterns, while suppressing variations in hydrogen concentration in the niobium electrode. An object of the present invention is to provide a method for forming an electronic device and an electronic device including a highly reliable Josephson junction formed by the method.

  When the hydrogen concentration in the niobium film made by the Josephson junction manufacturing process used by the present inventor was evaluated by the heated emission gas analysis method, it was measured that hydrogen emission of 0.4 to 5% (atomic%) was found. did. Since this manufacturing process is representative, it is considered that the same level (0.1 to several percent) of hydrogen is mixed in niobium even in the manufacturing process of a general Josephson junction that is currently widely practiced. It is done.

The niobium film forming process and the etching process are the main processes. When the niobium surface without the oxide layer is exposed, hydrogen gas or ions in the atmosphere enter the niobium film. When the hydrogen concentration in the atmosphere is sufficiently low, it is released from the niobium to the outside. Even if hydrogen gas (or a gas that decomposes and produces hydrogen or hydrogen ions such as CHF ₃ ) is not added intentionally in the film formation process or dry etching process, moisture in the atmosphere remains and the plasma Since it decomposes into hydrogen, the hydrogen partial pressure may not be negligible.

  It is well known that the superconducting properties of so-called niobium hydride containing a large amount of hydrogen of several tens of percent or more are significantly deteriorated (see Non-Patent Document 3).

However, it has been said that the superconducting property is not changed in an alloy called α phase, which is a solid solution of hydrogen at a maximum temperature of 5% (see Non-Patent Document 4).
Recently, however, it has been reported that thin-film niobium changes in superconducting properties even when hydrogen is mixed in such a few percent (see Non-Patent Document 5).

According to this report, the higher the hydrogen concentration, the more the superconducting properties of the niobium electrode deteriorate. Therefore, it is highly possible that the change in the hydrogen concentration directly causes a change in the superconducting critical current value.
According to the study by the authors up to the present time, it is estimated that about 1% (number of atoms) of hydrogen mixing causes a fluctuation of the superconducting critical current value of several tens of percent.
Therefore, for example, in order to suppress the critical current value in the circuit to a variation of about 10% from the design value, the hydrogen concentration in the niobium electrodes in the vicinity of all Josephson junctions should be made constant with an accuracy of about 0.1%. If you can do it. One method is to release as much hydrogen as possible from the niobium of the electrode / wiring of the finally completed device so that the concentration is 0.1% or less.

The following points must be taken into account when making the hydrogen concentration in niobium constant.
(A) Hydrogen moves in niobium even at room temperature. According to the so-called diffusion phenomenon, the diffusion distance (movement distance) is proportional to the 1/2 power of time. The standard diffusion distance at room temperature is about 1 cm / day. The process usually takes one step, such as niobium patterning, in minutes to hours. During this time, the concentration becomes almost uniform by diffusion in the range of several tens to several hundreds of microns, but non-uniformity remains in the order of the whole chip mm. In the niobium region, which is patterned in the shape of an island and not directly connected to niobium in other layers (details will be described later, hydrogen does not diffuse when connected via aluminum and molybdenum), hydrogen movement stops, and hydrogen inherent to that region It will be determined by the concentration. Hydrogen is likely to move even with palladium, platinum, titanium, and the like, which are sometimes used in niobium Josephson junction elements.
(B) Since hydrogen hardly moves in aluminum, it does not move beyond the barrier film of the Josephson junction. Hydrogen hardly moves even in molybdenum, tungsten, nitrides thereof, or niobium nitride that may be used in Josephson junction elements (see Non-Patent Documents 6 to 8).

  Based on this, Niobium's actual Josephson junction element is divided into a number of niobium regions separated by aluminum and molybdenum, which are difficult for hydrogen to move (even if they are electrically connected). I understand that. Depending on the process, there will be a difference in the hydrogen concentration of these niobium regions.

In order to make the hydrogen concentration in the divided niobium region uniform from the viewpoint of hydrogen transfer, the following method was considered.
(1) The niobium is subjected to a hydrogen releasing treatment, and the hydrogen concentration is lowered to such an extent that the fluctuation of the critical current value can be ignored.
(1-1) Hydrogen is released out of niobium if the surface of the niobium oxide layer is exposed in a reduced pressure (vacuum) having a sufficiently low hydrogen partial pressure.
(1-2) If a layer of palladium or platinum is provided on the niobium surface, hydrogen is released even in the atmosphere with a low hydrogen partial pressure. In the middle of the process, a palladium or platinum layer is formed, hydrogen is released, and then the palladium or platinum is removed and then the upper layer is formed.
(1-3) A hydrogen-extracting electrode that finally penetrates to the element surface is provided for each niobium island divided from the viewpoint of hydrogen migration. A palladium or platinum layer is formed on the surface of the electrode.
(2) In some cases, a uniform hydrogen concentration can be realized by forming a region in which hydrogen hardly passes in the vicinity of the junction and stopping the inflow and outflow of hydrogen from and to the adjacent region in the process.

It is difficult to measure the hydrogen concentration of each junction electrode in an actually fabricated device. Since the volume of the niobium electrode is very small, it is practically impossible to measure the hydrogen concentration directly. Therefore, a Kelvin type four-terminal test pattern having the same structure as that of the actual bonding and capable of measuring the bonding resistance at room temperature was fabricated on the same wafer, and the hydrogen concentration variation was estimated from the resistance value of the test pattern. The estimation procedure at that time will be described below.
(2-1) It was confirmed that the variation amount of the room temperature resistance value of the test pattern was almost equal to the variation amount of the junction critical current value at the element operating temperature (typically, the liquid helium temperature of 4.2 K).
(2-2) Test pattern (junction) It was confirmed that the room temperature resistance fluctuation amount was about five times the niobium wiring resistance fluctuation amount including the same concentration (FIG. 15).
(2-3) It was confirmed that the niobium wiring resistance fluctuation amount was about 7 times the hydrogen concentration (atomic%) in niobium (FIG. 16).
(2-4) From the above relationship, in order to keep the critical current density of the actual device junction within the range of ± 5%, the hydrogen concentration of the electrode is about ± 0.15%, preferably within the range of ± 0.1%. It can be seen that control is required.
(2-5) Whether or not the hydrogen concentration is controlled within this range can be determined by whether or not the critical current value of the element is within a range of ± 5%.

  According to the present invention, it is possible to suppress the deviation from the design value of the critical current value of the Josephson junction depending on the connection state of the niobium electrode, that is, the pattern, and it is possible to realize a large-scale and high-performance Josephson junction LSI. become.

<Example 1>
FIG. 1 is a cross-sectional view showing an example of a superconducting Josephson junction element effective by applying the present invention. 1 is a silicon substrate, 2 is an insulating film made of a silicon thermal oxide film, 3 is an insulating film of each layer made of SiO ₂ formed by sputtering, and Nb (indicated by Nb _11, Nb _31, Nb _51, etc. in FIG. 1). The niobium layer of the superconducting wiring, Al ₂ O ₃ is an aluminum oxide layer, and Mo is a molybdenum layer. In the figure, the insulating film SiO ₂ layer 3 is complicated in the figure, so that the reference numeral is attached to the lowermost layer. For the other layers, the insulating film SiO ₂ layer is displayed by applying the same right-down hatching. Similarly, in the following drawings, the silicon substrate has a downward-thick and thick hatching, the insulating film formed by the silicon thermal oxide film has a thin left-down hatching, the insulating film SiO ₂ layer has a right-bottom thin hatching, and the niobium layer has a left-downward hatching. The thick hatching, the aluminum oxide layer is indicated by a thick line, and the Mo layer is indicated by a thick left downward hatching.

The element shown in FIG. 1 is formed in the following manner, for example. Wiring patterns of niobium layers Nb ₁₁ and Nb ₁₂ are formed on the silicon thermal oxide film 2 formed on the silicon substrate 1. An insulating film SiO ₂ layer 3 is formed thereon and then planarized. Next, a wiring pattern of the niobium layer Nb ₂ is formed, an insulating film SiO ₂ layer 3 is formed thereon and then planarized, and the wiring pattern of the niobium layer Nb _{2 and} the wiring patterns of the niobium layers Nb ₃₁ and Nb ₃₁ are connected. An opening for this purpose is formed in the corresponding position of the insulating film SiO ₂ layer 3. Then, after forming a three-layered niobium Nb film-aluminum oxide Al ₂ O ₃ film-niobium Nb film on the entire surface, Josephson junction electrodes, Nb ₄₁ and Nb ₄₂ are formed by patterning. These Josephson junctions will be referred to as JJ1 and JJ2, respectively. Subsequently, patterning is performed to form an aluminum oxide Al ₂ O ₃ film pattern at a predetermined position. Further, patterning is continued to form wiring patterns of the niobium layers Nb ₃₁ , Nb ₃₂ and Nb ₃₃ . At this stage, the patterning of the three-layer laminated niobium Nb film-aluminum oxide Al ₂ O ₃ film-niobium Nb film is finished, and the niobium wiring pattern connected to the niobium layer Nb ₂ and the layers Nb ₃₁ and Nb ₃₃ are formed. .

Next, an insulating film SiO ₂ layer 3 is formed thereon and then planarized. In order to connect the niobium layer Nb ₅₁ to the Nb ₄₁ and the niobium layer Nb ₅₂ to the Nb ₄₂ , an opening is formed in the insulating film SiO ₂ layer 3 at a predetermined position. Then, after forming the niobium film over the entire surface of the substrate, the niobium layer _{Nb 51,} patterned wiring niobium layer _{Nb 51.}

In this figure, niobium is divided into several regions. Hydrogen moves at a high speed in niobium Nb and has a uniform concentration. However, since aluminum oxide Al ₂ O ₃ and molybdenum Mo do not pass through hydrogen, niobium is divided into the following six regions from the viewpoint of hydrogen concentration. The Nb region in () has the same concentration. Depending on the process, the hydrogen concentrations in these six regions may all be different.
(Nb ₁₁ ), (Nb ₁₂ ),
(Nb ₃₁ , Nb ₂ , Nb ₃₃ ), (Nb ₃₂ ),
(Nb ₅₁ , Nb ₄₁ ), (Nb ₅₂ , Nb ₄₂ )
Among these, the characteristics of the Josephson junction are determined
In JJ1, (Nb ₃₂ ) and (Nb ₅₁ , Nb ₄₁ ),
In _JJ2, a _{(Nb 31, Nb 2, Nb} 33) and _(Nb 52, Nb _42).

As a result of investigating the operation of the circuit manufactured and manufactured by the conventional method and structure, defects such as the operation range greatly deviating from the design value, the margin is narrowed, the device does not operate or malfunctions in extreme cases, are frequent. I understood it. Under such circumstances, it has been very difficult to realize a large-scale circuit in which many Josephson junctions are integrated.
Conventionally, the hydrogen in niobium has not been considered at all, and it is assumed that the hydrogen concentration is different for each region as described above, and that the junction characteristics and critical current density vary from the design values. The

  Therefore, in order to realize a device having a Josephson junction with a uniform hydrogen concentration and a critical current value as designed with little variation, the device was fabricated by the following method.

After preparing five sample wafers and forming a niobium film in the device manufacturing process shown in FIG. 1, four types of dehydrogenation treatments (1) to (4) shown in FIG. 2 were performed before patterning. One sheet was formed by a conventional method without the treatment of the present invention.
Specifically, after forming the first niobium layer to be Nb ₁₁ and Nb ₁₂ , forming the second niobium layer to be Nb _2, and then forming the fifth niobium layer to be Nb ₅₁ and Nb ₅₂ gave. The layers to be Nb ₃₁ , Nb ₃₂ , Al ₂ O ₃ , Nb ₄₁ , and Nb ₄₂ are formed as a three-layered film and are not processed here.
As an example, FIG. 3 shows a wafer cross-sectional state after the formation of the uppermost fifth layer of niobium. Thus, the processes (1) to (4) shown in FIG. 2 are performed in a state where the entire surface of the wafer is covered with the niobium film.

Here, the processes (1) to (4) will be described.
(1) Heat treatment is performed at 300 ° C. for 5 minutes in a bake furnace kept non-oxidizing by flowing pure argon gas. Vacuum may be used instead of argon, but the hydrogen gas partial pressure needs to be sufficiently low (at least about 10 −4 Pa or less at room temperature to make the concentration of hydrogen remaining in niobium sufficiently lower than 1%). In addition, a clear effect could be confirmed in the above baking furnace at a temperature of 150 ° C. or higher and a baking time of 3 minutes or longer. Needless to say, the treatment at a higher temperature for a longer time is more effective, but even if the treatment is performed at 600 ° C. or more for about 30 minutes or more, there is no significant improvement.

On the other hand, the junction structure of Nb—Al ₂ O ₃ —Nb deteriorates when the temperature is higher than 200 ° C. Therefore, after forming the junction structure, the processing temperature was lowered to 150 ° C. In this embodiment, the uppermost layer, the fifth layer of niobium, is processed.
(2) A wafer on which a niobium film was formed was introduced into a load-lock type vacuum device (degree of ultimate vacuum: 10-5 Pa level), 0.5 Pa of argon gas was introduced, and RF discharge was performed at 500 W for 10 minutes. This process is performed as a process for cleaning the wafer surface, and is not performed at the stage where the niobium film is formed. For the purpose of cleaning, it is desirable that the sputter etch rate of niobium or insulating film (SiO ₂ etc.) is high, but this time the etching rate is very slow at 1 nm / min, and the surface has an oxidizing adsorbate. It is desirable that it is slow as long as it can prevent adsorption. This is to reduce the amount of niobium loss.

In this case as well, it goes without saying that a long-time treatment has a great effect. A clear effect can be confirmed from about 3 minutes. In the case of a niobium film having a thickness of about 1 micron as in the present invention, the effect is saturated after about 20 minutes of cleaning with argon gas.
(3) The wafer temperature was raised to 150 ° C. in the processing of (2) above. The time is about 2 minutes, and the effect equivalent to (2) is obtained in a short time.

In this case as well, it goes without saying that long-time treatment at a high temperature has a great effect. The effect of shortening the time became clear at 150 ° C. or more, and the effect could be confirmed even by treatment for 1 minute or less, and the effect was saturated in about 3 minutes. The effect of shortening the time becomes larger as the treatment is performed at a higher temperature, but it is considered that the effect is shortened to 1 minute or less at 300 ° C. or higher.
(4) Using the apparatus of (2) above, the surface of the niobium film was cleaned and removed by about 10 nm of argon gas, and a very thin 5 nm thick palladium film was formed on the wafer surface by sputtering without breaking the vacuum. After holding for 10 minutes in an atmosphere of vacuum or argon gas as it is, all the palladium film is removed again by sputter cleaning with argon gas to completely expose niobium.

  In this case, the important point is the film thickness of palladium. When palladium was thinned to 2 nm or less, the effect was drastically reduced (a continuous film of palladium may not be formed). Therefore, in practice, it can be determined that a film thickness of 3 nm or more is sufficient. In consideration of the film formation time, the upper limit film thickness is about 50 nm here. Further, it goes without saying that the effect is greater as it is held for a longer time, but a clear effect is obtained in 2 minutes, and the effect is saturated in 20 minutes or more.

  The fabricated device was held in 4.2K liquid helium, and the critical current value of the junction was measured. Ten different samples of the two types of connection structures shown in FIG. 1 were measured, and the range of variation was determined. The results are shown in Table 1 in FIG.

Although the critical current value of the junction prepared by the conventional method varies in a wide range of about 20%, the junction created by the method of the present invention is within a range of about ± 5%, and the controllability is improved. I understand that.
In addition, when the distribution of critical current values is examined in detail, the occurrence of junctions with large critical current values that frequently occur in the conventional method (Ic in FIG. 1 having a large deviation of about 20%) is completely eliminated. I was able to confirm.

In the process (4) described above, the palladium film once formed was completely removed by sputtering cleaning, and then proceeded to the next patterning step. However, patterning can also be performed while leaving the palladium film on niobium. After the palladium layer is first etched by a sputter cleaning method or an ion milling method, the niobium layer may be patterned by reactive etching. Here, after a resist pattern was formed using a normal lithography method, etching was performed at about 20 nm by an ion milling method, and then the niobium layer was patterned by reactive plasma etching with sulfur hexafluoride gas. The palladium layer was thin enough that the resist pattern was not lost during both etching processes. In this treatment method, a palladium layer is left on top of the niobium layer. Furthermore, it is not a problem to form a connection hole and an upper layer niobium wiring thereon. The palladium at the bottom of the connection hole can be removed by sufficient sputter cleaning before forming the upper niobium film, and the superconducting properties are not impaired. Even if it remains, a superconducting current flows due to the proximity effect if the element enters a superconducting operating state.
The characteristics of the device thus fabricated were almost the same as (4) and superior to the conventional method.
The dehydrogenation treatment of this embodiment is performed for all the niobium layers that can be carried out, but is not necessary for the layer that is not directly connected to the junction with niobium. Needless to say, it is effective to apply only to a specific layer where the hydrogen concentration is particularly increased by the treatment in the vicinity of the junction.

<Example 2>
In this embodiment, the same dehydrogenation treatment as that in Embodiment 1 is performed after the niobium film is patterned and then niobium is in an island shape. A flow of processing equivalent to that in Example 1 is shown in FIG. In particular, when using the niobium multilayer wiring planarization method described in Patent Document 1 or Patent Documents 2 and 3, an etching process of SiO ₂ with a gas containing hydrogen, for example, CHF ₃ is required. This is particularly effective because hydrogen penetrates into the patterned niobium wiring and increases its concentration. When such flattening etching is not performed, the niobium wiring may be patterned and subsequently performed. The planarization etching may be performed after the planarization etching or after the planarization is further completed by CMP or the like.

FIG. 5 shows a flow of the planarization method of the above-mentioned patent or application, and shows a planarization process for one wiring layer. This will be described with reference to the drawings.
As shown in FIG. 5A, an insulating film SiO ₂ layer 2 was formed on the silicon substrate 1 as an insulating film. A niobium layer 3 (300 nm thickness) was formed as a first metal layer by a sputtering method.

Next, as shown in FIG. 5B, patterning was performed in a desired shape using a normal photolithography method and a dry etching method. An insulating film SiO ₂ layer 3a (SiO ₂ ; thickness of 300 nm) was formed thereon as an insulating film layer by sputtering. At that time, the thickness of the insulating film SiO ₂ layer is adjusted so that the surface of the insulating film SiO ₂ layer 3 a formed in the region where the niobium wiring layer 101 is not formed is substantially the same position as the surface of the niobium wiring layer 3. An insulating film SiO ₂ layer 3a having a thickness of 350 nm was formed. The reason why the thickness is increased by about 50 nm is to compensate for etching of the insulating film SiO ₂ layer 2 under the Nb layer by about 50 nm during the patterning of the niobium layer 3.

  If the underlying step formed by the niobium layer 3 is small, it is possible to use a normal sputtering method. However, in order to make a wiring system with good insulation reliability by filling the space between the wirings of the niobium layer 3 without any gaps. A bias sputtering method with excellent step coverage is suitable.

FIG. 5C shows a result of forming a mask for removing the convex portions of the insulating film SiO ₂ layer 3a formed in FIG. 5B using a resist film. This is a result of forming a resist film on the entire surface in the state of FIG. 5B and forming it by a photolithography technique so as to have a pattern almost opposite to the wiring pattern of the niobium wiring layer Nb101.

FIG. 5D shows a state where the insulating film SiO ₂ layer 3a is etched by the photoresist mask 53 and only the region 3b is left as a necessary portion. CHF ₃ was used as an etching gas. Thereby, the etching rate of the niobium layer Nb101 can be reduced to 1/10 to 1/20 of the etching rate of the insulating film SiO2 layer 3a. As a result, a sufficient over-etching time can be taken, and even if the etching thickness of the insulating film SiO ₂ layer 3a differs slightly depending on the location, the surface of the niobium layer Nb101 can be etched and stopped. As can be seen with reference to FIG. 5D, by thickening the reverse pattern, it is possible to prevent unwanted etching of the insulating film SiO ₂ layer 3a due to the shift of the pattern even when the over-etching time is increased.

FIG. 5E shows a state where the photoresist mask 53 is removed after the processing of FIG. 5D. The step in the region 3b of the insulating film SiO ₂ remaining at this stage is only the peripheral portion 3c of the wiring pattern formed by the niobium layer Nb ₁₀₁ . The width of these patterns is approximately 0.5 μm or less. That is, according to the present invention, the wide surface of the insulating film SiO ₂ layer 3a, which originally exists in the niobium wiring pattern Nb ₁₀₁ , has a narrow width only at the periphery of the wiring as shown in FIG. 5E. It was possible to change to the surface convex portion 3c. In addition, the density of the surface convex portions 3c having a narrow width is low, and the ratio of the convex portions can be reduced to about 10% or less in the normal pattern.

  FIG. 5F shows a structure obtained by subjecting the structure shown in FIG. 5E to a CMP (Chemical Mechanical Polishing) process, and polishing and removing the protrusions to make the structure flat.

  In this flow, the processing of the present invention may be performed at either stage of FIG. 5E or 5F. In this example, dehydrogenation processing was performed on the wafer in the state of FIG. 5F. The above-described planarization treatment was performed for each layer, and dehydrogenation treatment was performed each time.

  Five sample wafers were prepared, a niobium film was formed in the device manufacturing process shown in FIG. 1, and after patterning, four types of dehydrogenation treatments (1) to (4) shown in FIG. 4 were performed. One sheet was formed by a conventional method without the treatment of the present invention.

The processes (1) to (4) here will be described.
(1) Heat treatment is performed at 300 ° C. for 5 minutes in a bake furnace kept non-oxidizing by flowing pure argon gas. This is the same as the process (1) of the first embodiment.
(2) A wafer on which a niobium film was formed was introduced into a load-lock type vacuum apparatus (degree of ultimate vacuum: 10-5 Pa level), 0.5 Pa of argon gas was introduced, and RF discharge was performed at Vdc to 100 V for 20 minutes. . The discharge power is about 0.1 W / cm ² . Under these conditions, the niobium etching rate is very small, about 0.1 nm / min, and the amount of niobium reduced by this treatment is negligible compared to the initial film thickness of 200 nm.
When cleaning (cleaning) the niobium surface by removing a part of niobium by sputtering, the niobium surface is processed at a high etching rate. In order to achieve this at least on the order of several nanometers / minute, argon plasma with a condition of Vdc of several hundred volts is usually used.

If Vdc is too small, adsorption occurs on the surface and the effect of removing hydrogen is lost. Also, increasing Vdc is disadvantageous because the amount of niobium film loss increases. Actually, the allowable range of both was found in the range of Vdc = 50 to 150V.
(3) The processing of (2) was performed with the wafer temperature raised to 150 ° C. The time is about 5 minutes, and the effect equivalent to (2) is obtained in a short time.
(4) Same as the process (4) in the first embodiment.
The fabricated device was held in 4.2 K liquid helium, and the critical current value of the junction was measured. Ten different samples of the two types of connection structures shown in FIG. 1 were measured, and the range of variation was determined. The results are shown in Table 2 in FIG.
Although the critical current value of the junction prepared by the conventional method varies in a wide range of about 20%, the junction created by the method of the present invention is within a range of about ± 5%, and the controllability is improved. I understand that.

  In addition, when the distribution of critical current values is examined in detail, the occurrence of junctions with large critical current values that frequently occur in the conventional method (Ic in FIG. 1 having a large deviation of about 20%) is completely eliminated. This could be confirmed in the same manner as in the previous examples.

  The dehydrogenation treatment of this embodiment is performed for all the niobium layers that can be carried out, but is not necessary for the layer that is not directly connected to the junction with niobium. Needless to say, it is effective to apply only to a specific layer where the hydrogen concentration is particularly increased by the treatment in the vicinity of the junction.

<Example 3>
In this example, the same dehydrogenation treatment as in Example 2 was performed. During the bonding layer forming process, the upper niobium film was patterned to form niobium islands, and the lower niobium layer remained on the entire surface of the wafer before patterning. It is to be applied in the state. The processing will be described in order using FIG.

FIG. 6 shows in detail a process for forming a Josephson junction in the course of making the structure of FIG. 1 described in the first embodiment.
FIG. 6A shows a state in which a connection hole is opened at a predetermined position of the planarized base insulating film SiO ₂ layer to form a niobium-aluminum-niobium (Nb ₄ -Al ₂ O ₃ -Nb ₃ ) three-layer film. Show. The wafer in this state is subjected to normal photolithography and etching, and the upper niobium Nb ₄ is patterned to form niobium Nb ₄₁ and Nb ₄₂ . SF ₆ gas was used for dry etching of the niobium layer. Aluminum Al ₂ O ₃ is hardly etched by this gas. FIG. 6B shows this state. Subsequently, an SiO ₂ layer is formed on the entire surface of the wafer, and the regions SiO ₂ 41 and SiO ₂ 42 covering the previously formed niobium electrodes Nb ₄₁ and Nb ₄₂ are formed by performing the same photolithography and etching processes as described above. Further, the SiO ₂ region is used as a mask to form an aluminum layer (actually, the upper layer is oxidized to form a two-layer structure of aluminum oxide Al ₂ O ₃ -aluminum Al. For simplicity, aluminum or Al ₂ O ₃ (Abbreviated) is also etched by argon sputtering. FIG. 6C shows this state.

  Five sample wafers at this stage were prepared and subjected to the dehydrogenation treatment of the present invention in four ways (1) to (4) shown in FIG. One sheet was formed by a conventional method without the treatment of the present invention.

The processes (1) to (4) here will be described.
(1) Heat treatment is performed at 150 ° C. for 60 minutes in a baking furnace kept pure by flowing pure argon gas. At this stage, since the Josephson junction layer is formed, the treatment at a high temperature (300 ° C. in Examples 1 and 2) like other wiring layers deteriorates the junction characteristics. This is a process of holding at 150 ° C. for 60 minutes for a relatively long time.
(2) A wafer on which a niobium film was formed was introduced into a load-lock type vacuum apparatus (degree of ultimate vacuum: 10-5 Pa level), 0.5 Pa of argon gas was introduced, and RF discharge was performed at Vdc to 100 V for 20 minutes. . The discharge power is about 0.1 W / cm ² . Under these conditions, the niobium etching rate is very small, about 0.1 nm / min, and the amount of niobium reduced by this treatment is negligible compared to the initial film thickness of 200 nm.
When cleaning (cleaning) the niobium surface by removing a part of niobium by sputtering, the niobium surface is processed at a high etching rate. In order to achieve this at least on the order of several nanometers / minute, argon plasma with a condition of Vdc of several hundred volts is usually used. This is the same processing as (2) of the second embodiment.
(3) The processing of (2) was performed with the wafer temperature raised to 150 ° C. The time is about 5 minutes, and the effect equivalent to (2) is obtained in a short time. This is the same process as (3) of the second embodiment.
(4) Same as the process (4) of the second embodiment.

  The fabricated device was held in 4.2K liquid helium, and the critical current value of the junction was measured. Ten different samples of the two types of connection structures shown in FIG. 1 were measured, and the range of variation was determined. The results are shown in Table 3 in FIG.

  As in the previous examples, the critical current values of the junctions prepared by the conventional method varied in a wide range of about 20%, but the results of Examples 1 and 2 were not as high as those prepared by the method of the present invention. The variation of the non-existing ones is within a relatively narrow range, indicating that the controllability is improved.

  In addition, when the distribution of critical current values is examined in detail, the occurrence of junctions with large critical current values that frequently occur in the conventional method (Ic in FIG. 1 having a large deviation of about 20%) is completely eliminated. This could be confirmed in the same manner as in the previous examples.

  The dehydrogenation process of the present embodiment can be performed during the patterning of the junction formation layer, and only the first or second embodiment can be performed on the other wiring layers.

<Example 4>
This embodiment shows a processing method performed for the same purpose as those of Embodiments 1 to 3, and an element structure made by the method. The structure will be described with reference to FIG.
A structure in which the Josephson junction shown in FIG. 1 is connected by niobium wiring is formed on a wafer, and the surface is covered with a SiO ₂ film as shown in FIG. 9A, and then can be connected to the electrode niobium on both sides of the junction. Open the connection hole. In this case, connection holes to the upper electrode Nb ₅₁ and the lower electrode Nb _{53 of} the junction JJ1 are formed by photolithography and dry etching. The lower electrode Nb ₅₃ is provided for connection to the lower electrode Nb ₃₂ when the junction JJ1 is formed.

  This connection hole must be formed for each Josephson junction electrode, but it is common if several Josephson junctions are connected in parallel or in series to form one continuous niobium region. A connection hole may be provided. However, when the volume of the niobium region is very large, it is more effective to provide a large number of connection holes. This is because, as explained above, hydrogen diffusion in niobium takes a certain amount of time.

After opening the SiO ₂ film, a palladium layer Pd ₁ is formed on the entire surface of the wafer by sputtering. FIG. 9B shows the structure of the wafer cross section at this stage. Palladium is a region with horizontal hatching. Instead of directly forming palladium, a thin titanium layer may be provided under the palladium layer to improve adhesion to the oxide film. Here, a 50 nm palladium layer is formed on a 5 nm titanium layer. The titanium layer is not clearly displayed.
In this state, the substrate is held at room temperature or about 100 to 200 ° C. for several hours to several weeks. Although it is necessary that the hydrogen partial pressure in the holding environment is low (about 10-8 Pa or less at room temperature), a normal laboratory is sufficient unless it is close to the place where hydrogen is used. The holding time must be long enough so that the hydrogen in the element diffuses and moves in niobium and is released from the palladium region into the atmosphere, and the hydrogen concentration in niobium is sufficiently low. It also depends on the holding temperature, the complexity of the element wiring structure, and the like. In the case where the connecting portion is provided so that the distance from any position of the niobium wiring to the nearest palladium connecting position is about 1 mm or less, it is sufficient that it takes about one week at room temperature. In the case where the connection portion can be formed with a high frequency up to about 100 microns, it can be shortened to about several hours. The distance in this case is a length calculated as a path in the niobium wiring because it is a hydrogen diffusion path.

Alternatively, the structure shown in FIG. 9C may be processed and held in the atmosphere. In FIG. 9C, a photoresist pattern is formed so as to leave palladium in the vicinity of the connection hole with the Nb layer using a normal photolithography method. Subsequently, a palladium film and a titanium film (or palladium layer) are patterned by using an argon ion milling method to produce palladium electrodes Pd ₁₁ and Pd ₁₂ . Although the area of the hydrogen releasing part was much smaller than that in FIG. 9B, the required holding time was not much different.
In most cases, the hydrogen partial pressure of the use environment and the holding environment of the element having a normal Josephson junction is sufficiently low, and thus the element manufacture may be finished with the structure of FIG. 9C. In this case, as a precaution, the surface was covered with the SiO ₂ layer 4a as shown in FIG. 9D so as not to deteriorate the device performance even when exposed to an environment containing hydrogen.

Since the palladium-titanium electrodes Pd ₁₃ and Pd ₁₄ in FIG. 9C are not finally required, they may all be removed by milling as shown in FIG. 9E. Further, if the structure shown in FIG. 9F with the surface covered with the SiO ₂ layer 4 is used, there is no change in device characteristics even if it is exposed to a hydrogen atmosphere later.

When the critical current value of the Josephson junction prepared by the method described above was compared with that of the conventional structure, very good controllability equivalent to the method (4) of Examples 1 to 3 was obtained. The variation was within the range of ± several% from the design value.
In addition, when the distribution of critical current values is examined in detail, the occurrence of junctions with large critical current values that frequently occur in the conventional method (Ic in FIG. 1 having a large deviation of about 20%) is completely eliminated. This could be confirmed in the same manner as in the previous examples.

  With this structure, variation when a larger number of Josephson junctions are formed can be suppressed to a small value, and thus it is possible to manufacture a large-scale circuit element in which tens of thousands to hundreds of thousands of junctions are integrated.

Not only can the variation in bonding characteristics be suppressed by the present invention, but also the superconducting characteristics of individual bonds are improved. An example is shown in Table 4 of FIG. It can be seen that important characteristic values such as gap voltage, Vm, and Ic / Rn are large values due to the method and structure of the present invention, and the junction characteristics are improved.
Further, the present invention is effective not only for a circuit having a large number of Josephson junctions but also for an element that is required to have excellent individual junction characteristics even if the number of junctions is small.

<Example 5>
This embodiment does not aim to improve the junction characteristics by releasing the hydrogen taken into niobium out of niobium as in the first to fourth embodiments, but diffuses hydrogen into the connection with the layers having different hydrogen concentrations. A difficult structure is provided to suppress fluctuations in characteristics after manufacturing the joint. The structure will be described with reference to FIG.

  FIG. 10 shows a partial cross-sectional structure of a circuit in which Josephson junctions similar to FIGS. 1 and 8 are connected by niobium wiring. The manufacturing method is based on the conventional method described in Examples 1 to 4. FIG. 10 shows three Josephson junctions, JJ11, JJ12, and JJ13, but only the central JJ12 has a critical current value designed for actual circuit operation. The junction area is determined so that JJ11 and JJ13 on both sides have a critical current value twice that of JJ12. Even if a change in the hydrogen concentration described later and a change in the critical current value due to the change occur, if it is set so that it exceeds the maximum current value that can flow through the circuit, it does not need to be doubled, and the element area It is desirable to be smaller. In circuit operation, current exceeding the critical current value of these two junctions does not flow through this circuit, so these two junctions act as mere niobium wiring.

However, when viewed as a hydrogen transfer path, the two junctions on both sides block the hydrogen transfer and function to keep the hydrogen concentrations of both the upper and lower electrodes of the junction JJ12 that actually operates as a circuit constant. When directly connected to Nb ₃₂ via the upper electrode wirings Nb ₄₂ and Nb ₅₂ of JJ12, hydrogen flows between Nb ₂₁ connected thereto and hydrogen. Further, when Nb ₅₁ , Nb ₆₁ , and Pd ₁₁ are directly connected to the lower electrode wiring Nb ₃₁ of JJ 12, hydrogen in Nb is released to the outside through this path, and the hydrogen concentration is greatly reduced. In an actual circuit, there are junctions with different connection methods, which causes variations in hydrogen concentration, and hence junction characteristics. Although the junction characteristics of JJ11 and JJ13 vary as in this embodiment, the characteristics of JJ12 do not vary from the time when the junction is completed, and a large number of junctions in the actual circuit can be created as designed.

  Although the structure used as a barrier layer for suppressing hydrogen diffusion in the Josephson junction has been described above, this utilizes the fact that aluminum has a very small hydrogen diffusion coefficient unlike niobium. Therefore, any material that can suppress the diffusion of hydrogen can be used without being limited to bonding. A very thin aluminum layer (which may not be partly oxidized), a niobium nitride layer, or the like can have the same structure. Needless to say, it is also possible to use a material that does not become superconductive under operating conditions, such as molybdenum, if it is acceptable for the resistance component to enter the circuit.

<Example 6>
The present embodiment shows a processing method performed for the same purpose as those of Embodiments 1 to 4 and an element structure made by the method. The structure will be described with reference to FIG.
A structure in which Josephson junctions shown in FIG. 1 are connected by niobium wiring is formed on a wafer, and the surface is covered with a SiO ₂ film 5 as shown in FIG. 11A. An opening is formed at a predetermined position of the SiO ₂ film 5 by a normal photoetching method. In addition to the normal opening (V1) for forming the connection wiring between the layers, an opening (DV1) having no connection to the upper layer is provided (FIG. 11B). Subsequently, as shown in FIG. 11C, a niobium layer (Nb ₆ ) was formed on the entire surface of the wafer by a sputtering method. Normally, this niobium layer is subsequently patterned, but here it was left at room temperature for about 1 day. During this time, hydrogen diffuses through the niobium layer (Nb ₆ ), and the hydrogen concentration of the niobium layer that is not directly connected becomes uniform. In this case, hydrogen moves back and forth between the lower niobium (Nb ₃₂ ) and the electrode niobium (Nb ₄₁ ), and becomes uniform. A uniform hydrogen concentration can be reached in a short time by providing openings only for hydrogen diffusion without connection to the upper layer at narrow intervals. Here, since the openings were provided at intervals of about 500 microns, a standing time of about one day was taken. It goes without saying that the standing time can be shortened by heating to a temperature of about 100 ° C. at which the Josephson junction does not deteriorate.

Thereafter, the niobium layer is patterned by a normal photoetching method to form the wiring Nb ₅₄ . In particular, niobium in the opening (DV1) without connection to the upper layer was removed by etching. In this etching, in order to avoid deterioration due to etching on the lower layer of niobium (Nb ₃₂ ), a niobium island (Nb ₅₅ ) may be left in this portion as shown in FIG. 11E.
Similar to the above-described embodiments, this method and structure can suppress the variation when a larger number of Josephson junctions are formed, so that a large scale in which tens of thousands to hundreds of thousands of junctions are integrated is integrated. Circuit elements can be manufactured.

Sectional drawing which shows an example of the superconducting multilayer wiring to which this invention is applied. The figure which shows the process flow of the manufacturing process of this invention. Sectional drawing which shows an example to which the process of this invention is applied. The figure which shows another process flow of the manufacturing process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The element cross section in the manufacture middle process of the wafer which performs the process of this invention. The figure which shows another process flow of the manufacturing process of this invention. Sectional drawing (element process) which shows the structure of this invention. Sectional drawing (final process) which shows the structure of this invention. Sectional drawing (final process) which shows the structure of this invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. The element sectional view showing another structure of the present invention. Distribution diagram of critical current value at the junction measured with the test pattern. The distribution diagram of critical current values at junctions measured with different test patterns. The schematic diagram of critical current value distribution in the junction in an actual circuit. The correlation diagram of junction resistance variation and niobium wiring resistance variation. The correlation diagram of niobium wiring resistance fluctuation amount and the hydrogen concentration in niobium. The table | surface which shows the measured critical current value corresponding to the various hydrogen desorption processing methods after Nb film-forming. The table | surface which shows the measured critical current value corresponding to the various hydrogen-release process methods after Nb patterning. The table | surface which shows the measured critical current value corresponding to the various hydrogen-release process methods after Nb patterning. A table showing Josephson junction characteristics corresponding to various hydrogen release treatment methods.

Explanation of symbols

1 ... silicon substrate,
2 ... Silicon thermal oxide film,
3, 3a, 3b, 3c, 4, 4a ... silicon oxide film, SiO ₂ 41, SiO ₂ 42 ... silicon oxide film (SiO ₂ ),
Nb ₃ , Nb ₄ , Nby ... niobium layer,
_{Nb 11, Nb 2, Nb 31} , Nb 32, Nb 33, Nb 41, Nb 42, Nb 51, Nb 52, Nb 53, Nb101 ... niobium wiring layer (pattern),
Al ₂ O ₃ ... aluminum pattern with oxidized surface,
Mo ... Mo pattern,
JJ1, JJ2, JJ11, JJ12, JJ13 ... Josephson junction,
53. Photoresist,
Pd ₁ ... palladium layer,
Pd ₁₁ , Pd ₁₂ , Pd ₁₃ , Pd ₁₄ ... Palladium electrode.

Claims (18)

A first step of forming an insulating film on the substrate;
A second step of forming a niobium film on the insulating film;
And a third step of forming a niobium wiring by patterning the niobium film into a desired shape using a resist formed on the first niobium film as a mask,
A method for manufacturing an electronic device having a Josephson junction, comprising: a surface treatment step for the niobium film surface before the second step is completed and the third step is started.   The method for manufacturing an electronic device with a Josephson junction according to claim 1, wherein the surface treatment step is performed using argon sputtering for 3 to 20 minutes.   2. The method of manufacturing an electronic device with a Josephson junction according to claim 1, wherein the surface treatment step is performed using argon sputtering at a treatment temperature of 150 to 300 ° C. for 1 to 3 minutes.   2. The method of manufacturing an electronic device with a Josephson junction according to claim 1, wherein the surface treatment step is performed in pure argon at a treatment temperature of 150 to 600 ° C. for 3 to 30 minutes.   In the surface treatment step, the surface of the niobium film is cleaned and removed by approximately 10 nm by argon sputtering, and then a palladium film is deposited on the surface of the niobium film by 3 to 50 nm, and further in vacuum or argon for 2 to 20 minutes. 2. The method of manufacturing an electronic device having a Josephson junction according to claim 1, wherein the surface of the palladium film is exposed to about 10 nm by argon sputtering, and thereafter the surface of the palladium film is cleaned and removed by approximately 10 nm. A first step of forming an insulating film on the substrate;
A second step of forming a niobium film on the insulating film;
A third step of forming a niobium wiring by patterning the niobium film into a desired shape using the resist formed on the niobium film as a mask,
A method of manufacturing an electronic device having a Josephson junction, comprising: a surface treatment step for the niobium wiring surface after the third step is completed.   The method of manufacturing an electronic device with a Josephson junction according to claim 6, wherein the surface treatment step is performed using argon sputtering in which a DC bias condition is Vdc = 50 to 100V for 3 to 20 minutes. .   The Josephson junction according to claim 6, wherein the surface treatment step is performed using argon sputtering with a DC bias condition of Vdc = 50 to 100 V at a treatment temperature of 150 to 300 ° C. for 1 to 3 minutes. A method of manufacturing an electronic device comprising:   7. The method of manufacturing an electronic device with a Josephson junction according to claim 6, wherein the surface treatment step is performed in pure argon at a treatment temperature of 150 to 600 [deg.] C. for 3 to 30 minutes.   In the surface treatment step, the surface of the niobium film is cleaned and removed by about 10 nm by argon sputtering, and then a palladium film is deposited on the surface of the niobium film by 3 to 50 nm, and further in vacuum or argon for 2 to 20 minutes. 7. The method of manufacturing an electronic device having a Josephson junction according to claim 6, wherein the surface of the palladium film is exposed to about 10 nm and then removed by argon sputtering. A first step of forming an insulating film on the substrate;
A second step of forming a first niobium film on the insulating film;
A third step of forming a very thin insulating film on the first niobium film;
A fourth step of forming a second niobium film on the ultrathin insulating film;
Have
A fifth step of patterning the second niobium film into a desired shape using the resist formed on the second niobium film as a mask; and the pattern exposed on the patterned second niobium film and exposed by the patterning. A sixth step of patterning the ultrathin insulating film into a desired shape using a resist formed on the ultrathin insulating film as a mask; the patterned second niobium film; and the ultrathin insulating film; Forming a device portion having a niobium Josephson junction by a seventh step of patterning the first niobium film into a desired shape using a resist formed on the first niobium film as a mask. ,
A method of manufacturing an electronic device having a Josephson junction, comprising: a surface treatment step for the surface of the first niobium film before the sixth step is completed and the seventh step is started.   12. The method of manufacturing an electronic device with a Josephson junction according to claim 11, wherein the surface treatment step is performed for 3 to 20 minutes using argon sputtering in which a DC bias condition is Vdc = 50 to 100V. .   The Josephson junction according to claim 11, wherein the surface treatment step is performed using argon sputtering with a DC bias condition of Vdc = 50 to 100 V at a treatment temperature of 150 to 300 ° C. for 1 to 3 minutes. A method of manufacturing an electronic device comprising:   12. The method of manufacturing an electronic device with a Josephson junction according to claim 11, wherein the surface treatment step is performed in pure argon at a treatment temperature of 150 [deg.] C. or less for 30 to 60 minutes.   In the surface treatment process, the surface of the first niobium film is cleaned and removed by approximately 10 nm by argon sputtering, and then a palladium film is deposited on the surface of the first niobium film by 3 to 50 nm, and further for 2 to 20 minutes. 12. The method for manufacturing an electronic device with a Josephson junction according to claim 11, wherein the surface of the palladium film is exposed to vacuum or argon, and thereafter the surface of the palladium film is removed by cleaning by approximately 10 nm by argon sputtering. An insulating film provided on the substrate;
A first Josephson junction having a first junction area in which a first niobium film, an ultrathin insulating film, and a second niobium film are stacked in this order from the substrate side on the insulating film; ,
A second Josephson junction having a larger junction area than the first junction area;
The first or second niobium film of the first Josephson junction and the first or second niobium film of the second Josephson junction are connected to each other and separated from other niobium wirings. An electronic device having a Josephson junction. An insulating film provided on the substrate;
A first Josephson junction formed by laminating a first niobium film, an ultrathin insulating film, and a second niobium film on the insulating film in this order from the substrate side;
The first niobium film is connected to a palladium film directly or via a third niobium film provided on a region where the first niobium film extends, and there is no conductor on the palladium film. An electronic device with a featured Josephson junction. An insulating film provided on the substrate;
A first Josephson junction formed by laminating a first niobium film, an ultrathin insulating film, and a second niobium film on the insulating film in this order from the substrate side;
The second niobium film is connected to a palladium film directly or via a third niobium film provided on a region where the second niobium film extends, and there is no conductor on the palladium film. An electronic device with a Josephson junction.

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