CN117542839A - Method for producing superconducting qubits, test junction, and production and use thereof - Google Patents
Method for producing superconducting qubits, test junction, and production and use thereof Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 186
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000005259 measurement Methods 0.000 claims abstract description 17
- 239000000523 sample Substances 0.000 claims description 34
- 230000005540 biological transmission Effects 0.000 claims description 23
- 239000010955 niobium Substances 0.000 claims description 14
- 229910052758 niobium Inorganic materials 0.000 claims description 13
- 229910052715 tantalum Inorganic materials 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 11
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000002096 quantum dot Substances 0.000 claims description 8
- 238000012216 screening Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 52
- 230000004888 barrier function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910000484 niobium oxide Inorganic materials 0.000 description 3
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000007735 ion beam assisted deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- 241000238366 Cephalopoda Species 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007542 hardness measurement Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
The application discloses a method for manufacturing superconducting quantum bits, a test junction and manufacturing and application thereof, and belongs to the technical field of quantum computing. Wherein the test junction has a superconducting film and a second test electrode. The superconducting film has a junction electrode, and a first test electrode mated with a second test electrode. Wherein the materials of the first and second test electrodes are selected such that the oxides of the two have different hardness. Thus, measuring the resistance of the Josephson junction with the test junction can reduce the operational difficulty in measurement and avoid damaging the Josephson junction.
Description
Technical Field
The present application relates to the field of quantum information, and in particular to the field of quantum computing technology, and in particular, to a method of fabricating superconducting qubits, a test junction, and fabrication and application thereof.
Background
The josephson junction has a specific and important impact on the computational performance of the "computation center" -superconducting quantum chip-in superconducting quantum computers.
In the actual fabrication of superconducting quantum chips, the fabricated josephson junctions are tested to determine whether the quality or performance parameters thereof meet the requirements. Other structures in the superconducting quantum chip after testing can avoid the problem of subsequent junction discovery that requires full-disk remanufacturing.
The performance of the superconducting quantum chip is related to the frequency of superconducting qubits constructed based on the Josephson junctions and the like. Whereas the ambient resistance of a josephson junction is related to the critical current and to the frequency of the superconducting qubit. Therefore, the measurement of the room temperature resistance of the josephson junction is an important test means for researching the bit performance of the quantum chip.
Because of the small size (e.g., micron size) of the josephson junctions, it is measured by probe contact energization. However, the existing probe test mode has low efficiency and is easy to stab and damage the Josephson junction.
Disclosure of Invention
Examples of the present application provide a method of fabricating superconducting qubits, test junctions, and fabrication and application thereof. The scheme can be used for accelerating the development speed of superconducting qubits. The hardness of the electrode portion material of the test junction is controlled by selecting the material, so that the measurement operation can be performed more efficiently when the junction resistance is tested. In this way, the measurement of junction resistance is accomplished quickly using such a scheme, and can be used to quickly complete a screening-qualified josephson junction operation.
The scheme exemplified by the application is implemented as follows.
In a first aspect, examples of the present application present a test junction for fabricating a superconducting quantum chip.
The test junction defines a junction region and a test region, and further includes:
a superconducting film including an integrated junction electrode and a first test electrode having no oxide on the surface; and
the second test electrode is laminated on the surface of the first test electrode;
the junction electrode is positioned in the junction region and forms a superconducting layer of the Josephson tunnel junction, and the first test electrode is positioned in the test region;
the first test electrode and the second test electrode have different materials, and the hardness of each oxide is determined by the materials such that the hardness of the oxide of the first test electrode is greater than the hardness of the oxide of the second test electrode.
According to some examples of the present application, the material of the first test electrode comprises tantalum or niobium;
alternatively, the second test electrode is aluminum;
alternatively, the two superconductive layers in the josephson tunnel junction have the same extension direction;
alternatively, the two superconductive layers in the josephson tunnel junction have different directions of extension;
alternatively, the two superconductive layers in the josephson tunnel junction are perpendicular to each other.
According to some examples of the present application, at least one josephson tunnel junction is included in the test junction;
optionally, at least part of the josephson tunnel junctions in the test junction form a superconducting quantum interferometer.
According to some examples of the present application, the test structure further comprises a first transmission line and a second transmission line, the central signal line of the first transmission line being connected to one of the superconducting layers of the josephson tunnel junction, the central signal line of the second transmission line being connected to the other superconducting layer of the josephson tunnel junction.
In a second aspect, examples of the present application provide for the use of the aforementioned test junction in the manufacture of superconducting quantum chips;
alternatively, the test junctions are used to screen manufacturing process or structural parameters of the superconducting qubits.
According to some examples of the present application By using Applications include measuring junction resistance of josephson junctions with test junctions;
the measuring method comprises the following steps:
based on the probe method, the measurement is performed by puncturing the second test electrode to make electrical contact with the first test electrode.
In a third aspect, examples of the present application provide a method of fabricating superconducting qubits.
The method comprises the following steps:
determining fabrication parameters of the superconducting qubit, wherein the fabrication parameters comprise structural parameters of the josephson tunnel junctions, the structural parameters being determined by testing and screening using a plurality of test junctions as previously described having different configurations;
superconducting qubits are fabricated by performing a micro-nano machining process based on fabrication parameters.
In a fourth aspect, examples of the present application provide a method of manufacturing a test junction, the method comprising:
depositing selected regions of the superconducting film of the josephson junction to form a second test electrode;
the superconducting film comprises a junction electrode and a first test electrode, wherein the junction electrode is positioned in a defined junction area, and the first test electrode is positioned in a test area which is defined to be far away from the junction area;
the selected area is a deposition window of a first test electrode positioned in the test area, and the surface of the first test electrode is removed with an oxide layer;
the hardness of the oxide of the first test electrode is greater than the hardness of the oxide of the second test electrode.
In a fifth aspect, examples of the present application provide for forming a window by undercut photoresist etching a first test electrode prior to fabrication of a second test electrode by deposition.
According to some examples of the present application, the undercut photoresist is retained after the test junction is fabricated.
The beneficial effects are that:
the need for rapid and convenient testing of junction resistance of josephson junctions, the design in the examples of this application, is made of a test junction for measurement use. The junction resistance and other electrical parameters of the designed Josephson junction can be measured efficiently by testing the junction. In an example, the test junction is based on the construction of the josephson junction, the oxide layer on the junction is removed in selected areas and the electrodes for the test are also arranged, and the junction electrodes of the josephson junction and the materials of the electrodes for the test are also selected such that the oxides of the two have different hardness pointing. Thus, when the junction resistance is measured using the probe method, the probe can conveniently pierce the electrode for test and make conductive contact with the junction electrode.
Drawings
For a clearer description, the drawings that are required to be used in the description will be briefly introduced below.
Fig. 1 is a schematic structural diagram of a josephson junction in the example of the present application;
fig. 2 is a schematic structural diagram of a coplanar waveguide transmission line in an example of the present application;
fig. 3 discloses a schematic structural diagram of two configurations of josephson junctions in the examples of the present application;
FIG. 4 discloses a schematic structure of a junction region and a test region in the in-line junction of FIG. 3;
FIG. 5 discloses a schematic structural view of the junction region and the test region in the cross-junction of FIG. 3;
FIG. 6 depicts a process flow diagram for fabricating superconducting qubits based on test junctions in an example of the present application;
fig. 7 illustrates a process flow diagram for fabricating a test junction in an example of the present application.
Detailed Description
Currently, superconducting qubits are generally manufactured based on josephson junctions. Wherein the josephson junction comprises the form of a track-following junction. The josephson junction is formed by two superconducting layers and a barrier layer in between the two superconducting layers, see fig. 1.
Where the superconducting layer is selected to be located, for example, in tantalum/Ta or niobium/Nb or Al-aluminum, the barrier layer is then selected to be the corresponding oxide. For example, in the case of a superconducting layer of tantalum, the barrier layer is tantalum oxide; in the case of a superconducting layer of niobium, then the barrier layer is niobium oxide; in the case of the superconducting layer of Al, the barrier layer is alumina. Thus, such a Josephson junction is Ta/TaO x Structure of Ta; alternatively, such a Josephson junction may also be Nb/NbO x Structure of/Nb, or Al/AlO x Structure of/Al.
More preferably, tantalum and niobium are also well suited for the fabrication of quantum chip transmission lines. Thus, tantalum or niobium materials can be used to achieve the desired manufacturing efficiency and quality by combining the structure of the josephson junction and transmission line. Where the transmission line is for example a coplanar waveguide (Coplanar Waveguide, CPW for short), such a structure can be described in fig. 2. In fig. 2, the coplanar waveguide includes a central signal line and a ground plane spaced apart from it on both sides thereof. One location in the central signal line is the junction region, where the josephson junction is fabricated.
The above-described structure may be formed by fabricating a josephson junction in the form of a tunnel junction at a selected location, and also fabricating two coplanar waveguide lines. And wherein the central signal line of the coplanar waveguide line is connected to the two superconductive layers of the josephson junction, respectively, for example, the central signal line is connected to the pad region of the superconductive layer of the josephson junction.
In a superconducting quantum computer scenario, a josephson junction is used to construct superconducting qubits, and its junction resistance is related to critical current and thus also to other properties of the josephson junction, such as frequency, etc. The Josephson junction normal temperature resistance measurement is an important test means for researching the bit performance of the quantum chip.
In the actual fabrication of superconducting quantum chips, it is tested whether the fabrication of the josephson junctions therein meets design goals and expectations in order to ensure the quality of the quantum chips. The junction resistance can be measured by the probe method.
In the above example of using tantalum or niobium to fabricate josephson junctions, transmission lines, after fabricating the josephson junctions (or also including the transmission lines connected thereto), probes may be used to contact areas such as the transmission lines or pads of the josephson junctions in order to test the junction resistance at normal temperature of the josephson junctions, and then power-on testing.
Since tantalum or niobium is easily oxidized and forms an oxide on the surface, the probe penetrates the oxide to contact the metallic niobium/metallic tantalum. However, in practice, oxide layers of Ta, nb and the like are hard, and a probe cannot easily puncture the oxide layer during testing, so that the normal-temperature resistance of the Josephson junction cannot be tested; or the probe is required to be tested for multiple times, so that the efficiency is low; alternatively, improper force control of the puncture will result in ligation failure.
In some solutions, it may be selected to re-measure by removing the oxide layer. However, such a solution may present a potential risk that the removal operation may be incomplete. Or removing the oxide layer and regenerating the oxide layer before the probe test; because the probe measurement of the resistance of the josephson junction is performed in an air atmosphere, oxygen in the air may cause reoxidation.
Alternatively, in other cases, the fabrication materials may be selected to be modified so that they do not readily form an oxide layer; but such materials may not be easily selected because they need to meet superconductivity, ease of fabrication of junctions and transmission lines, etc., and such conditions may not be so easily met.
In view of such problems and situations, in the examples of the present application, the inventors have proposed a solution by removing the oxide layer at the site where the junction is expected to contact the probe, and then manufacturing a material that can meet the requirements (such as superconducting) in this region, and it may be difficult to form the oxide layer, or it may be less hard (for example, compared to tantalum oxide or niobium oxide) although the oxide layer is also easily generated.
That is, by treating a material (material a) which is easily oxidized and has a harder oxide, the oxide is removed from selected locations of the oxidized portion, and then covered by manufacturing another superconducting material (material B) so that the group prevents the material a from being oxidized again. Meanwhile, by selecting the material a and the material B, the hardness of the oxide B of the material B is made smaller than that of the oxide a of the material a. Thus, since material a is not oxidized, and material B is softer, allowing the probe to more easily pierce oxide B, material B, and then contact material a in sequence.
In some examples of the present application, the aforementioned selected material is, for example, aluminum/Al. Aluminum can also be used to make Josephson junctions and has Al/AlO as previously described x Structure of/Al.
Aluminum meets superconducting requirements and, due to the nature of the aluminum material, is easily oxidized but has a lower hardness, at least less than tantalum oxide or niobium oxide. Thus, when the test is performed by the probe method, the probe penetrates through the oxide layer on the surface of the Al layer to complete the test, and then the test is performed by electrifying when the metal tantalum/niobium without oxide on the surface contacts. The probe method can be 4 probes or 2 probes, the probes are tied at two ends of the Josephson junction (namely two layers of superconducting electrodes), and the resistance of the Josephson junction is tested by testing current and voltage through direct current.
For the 2-probe method, one of the probes is in electrical contact with one superconducting electrode of the junction and the other probe is in electrical contact with the other superconducting electrode of the junction. For the 4-probe method, two of the probes are in electrical contact with one superconducting electrode of the junction (and the contact points of the two probes are separated), and the other two of the probes are in electrical contact with the other superconducting electrode of the junction (and the contact points of the two probes are separated).
Based on the above description, a test junction is disclosed in the examples of the present application. The test junction may be used to fabricate superconducting quantum chips. The portion of the test junction used for manufacturing the superconducting quantum chip is integrated into the superconducting quantum chip, or the test junction is used for determining manufacturing parameters (including process condition parameters, component structure parameters and the like, for example) for manufacturing the superconducting quantum chip through testing, but the whole or part of the test junction does not enter the superconducting quantum chip as an integral part.
And for ease of discussion and illustration, junction regions and test regions are defined in the test junction. Wherein the junction region is the location of the Josephson junction, more focused, the interlayer overlap region in the layered structure of the junction; the test area is the area to be tested later by using the probe.
On this basis, the test junction comprises a superconducting film and a second test electrode. Wherein the superconducting film comprises an integrated junction electrode and a first test electrode with no oxide on the surface. The second test electrode is laminated on the surface of the first test electrode.
The junction electrode in the superconducting film is located in the junction region and is used to form the superconducting layer of the josephson tunnel junction, while the first test electrode is located in the test region. In particular, the first test electrode and the second test electrode have different materials, and the hardness of each oxide is determined by the materials so that the hardness of the oxide of the first test electrode is greater than that of the oxide of the second test electrode. For example, the first test electrode and the junction electrode are made of the same material, such as tantalum or niobium; the second test electrode is, for example, aluminum.
Wherein the two superconducting layers in the josephson tunnel junction may have the same extension direction; for example, a josephson tunnel junction of in-line configuration can be formed in this way; see fig. 3. Alternatively, the two superconductive layers in the josephson tunnel junction have different directions of extension; for example, two superconducting layers are interdigitated. For example, the two superconducting layers in the josephson tunnel junction may be mutually perpendicular; thus, a Josephson tunnel junction with a cross-shaped structure can be formed; see fig. 3. For test junctions with two different configurations of josephson tunnel junctions, the junction regions and test regions therein may be distributed in the manner disclosed in fig. 4 and 5.
The hardness for the oxide mentioned in the foregoing may be, for example, mohs hardness, rockwell hardness; or by other forms of measurement, hardness measurements on different oxides with the same criteria to distinguish the magnitudes of hardness. Alternatively, in the examples herein, it may be determined by a probe station test whether oxides can be penetrated under the same operating parameters and conditions.
Furthermore, the number of josephson tunnel junctions in the test structure may be arbitrarily chosen. Thus, at least one josephson tunnel junction is included in the test junction. When there are multiple josephson tunnel junctions, at least some of the josephson tunnel junctions in the test junction form a superconducting quantum interferometer. For example, for a frequency tunable superconducting qubit, there may be two josephson tunnel junctions in the test structure, and both constitute a superconducting quantum interferometer SQUID that may be in the form of a symmetrical junction (or asymmetrical).
In some examples, such test junctions (josephson junctions in) may be connected to transmission lines in order to transmit signals (which may be electrical signals, or other intentionally selected electromagnetic signals). Thus, in some examples, the test structure may alternatively further comprise a first transmission line and a second transmission line. The two transmission lines may optionally share a ground plane on both sides of the central signal line, as shown in fig. 2.
Wherein the central signal line of the first transmission line is connected to one of the superconducting layers of the josephson tunnel junction and the central signal line of the second transmission line is connected to the other superconducting layer of the josephson tunnel junction. Thus, for a word junction, the two superconducting layers may alternatively extend in the same direction, and thus the central signal lines of the transmission lines connected to the two superconducting layers may be distributed in a substantially straight line.
By the above description, a test structure capable of more conveniently, rapidly and accurately testing at least room temperature resistance/room temperature resistance of the josephson junction can be obtained. And from what has been described, by measuring the resistance of the josephson junction, it is possible to infer its performance, as well as the performance based on the frequency of the superconducting qubit it is fabricated from.
Then, in the examples of the present application, one application of the aforementioned test junction in the fabrication of superconducting quantum chips may be disclosed. Applications include, for example, fabrication processes or structural parameters in which test junctions are used to screen superconducting qubits.
Since the fabrication of josephson junctions is involved in superconducting qubits, it includes, for example, junction metal materials, photolithography, etching, junction formation, and the like. Thus, the manufacturing process includes, for example, the temperature, atmosphere, raw material amount, etc. in the manufacturing process. While the structural parameters may include, for example, junction electrode width, thickness, length of the josephson junction, as well as junction area, structural type, etc.
Exemplary screening methods include, for example: the test junctions of the expected design of the josephson junctions are first fabricated by a certain process and then measured. If the junction resistance obtained by measurement does not meet the requirements, the manufacturing process or the structure of the junction can be changed and then measured. The structure and fabrication process of the corresponding suitable junction is determined by such multiple iterative experiments to have the desired junction resistance. It is noted that the structural design of the junction and the fabrication process may be independent or combined to influence or correlate the junction critical current, and the superconducting qubit frequency based thereon.
In addition, the use of test junctions includes measuring junction resistance of josephson junctions with the test junctions. Exemplary measurement methods include, for example: based on the probed method (e.g., two probes or four probes as described above; four probes have higher measurement accuracy) the measurement is performed by puncturing the second test electrode into electrical contact with the first test electrode. The josephson junction resistance is tested, for example, by using direct current test currents and voltages.
Similarly, referring to fig. 6, a method of fabricating superconducting qubits using the above-described test junctions may include:
determining fabrication parameters of the superconducting qubit, wherein the fabrication parameters include structural parameters of the josephson tunnel junction, the structural parameters being determined by testing and screening using a plurality of test junctions having different configurations. After determining the fabrication parameters, superconducting qubits are fabricated by performing a micro-nano processing method based on the fabrication parameters.
It should be noted that various conditions, parameters, etc. may be used in the process involving the fabrication of superconducting qubits, and thus, the fabrication parameters determined by using test junctions in the examples of the present application may not be, and are not implied, all of the parameters required to fabricate the bits. I.e. the manufacturing parameters determined in the manner described above may be only some of the total parameters.
In order to make it easier for a person skilled in the art to implement the solution illustrated in the present application, the method of manufacturing the test junction is briefly described below.
Referring to fig. 7, the manufacturing method includes: a selected region of the superconducting film of the josephson junction is deposited to form a second test electrode.
In the above, the superconducting film includes the junction electrode and the first test electrode. The superconducting films described above may be fabricated by a combination of deposition, photolithography, lift-off, and other means, and various suitable micro-nano processing techniques may be used.
In the superconducting film, a junction electrode is located in a defined junction region, and a first test electrode is located in a test region defined to be distant from the junction region; the distribution of the regions can be seen, for example, in fig. 2, 4 and 5. The selected area is a deposition window of a first test electrode located in the test area, and the oxide layer is removed from the surface of the first test electrode. Wherein the hardness of the oxide of the first test electrode is greater than the hardness of the oxide of the second test electrode.
In the above process, the deposition window may be etched through the undercut photoresist to form a window through the first test electrode using a photolithography process (e.g., photoresist application, exposure, development, etc.). It is known that the deposition window is manufactured before the second test electrode is manufactured by deposition.
The undercut photoresist may be removed in different steps based on different test operation sequences. For example, after manufacturing the test junction, the undercut photoresist is left. Thus, undercut photoresist remains when the resistance is measured using the test junction, i.e., the photoresist is removed after measurement using the test junction. Alternatively, in other examples, the undercut photoresist has been removed before the resistance is measured using the test junction, i.e., the glue is removed in advance before the resistance is measured using the test junction.
In addition to the timing of removing the glue, the timing of removing the second test electrode may also be selected. Since the second test electrode is used when measuring electrons using the test junction, the second test electrode is removed after the measurement is completed.
For example, after measuring the resistance once, the second test electrode (which may be an aluminum film) is removed. This is advantageous at least in that: if the performance of the first test electrode (e.g., nb or Ta film) needs to be tested, no effect of other factors caused by the second test electrode is introduced. And if the second test electrode is left after the resistance measurement is performed once, the resistance measurement can be performed at any time and a plurality of times.
In the above-described processes, one or more materials, such as superconductors, dielectrics, and/or metals, may be selectively deposited. And depending on the material selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or Sputtering), or epitaxy techniques, as well as other deposition processes, including, for example, ion Beam Assisted Deposition (IBAD), vacuum Evaporation plating (evap), molecular Beam Epitaxy (MBE), pulsed Laser Deposition (PLD), chemical Vapor Deposition (CVD), sol-gel (sol-gel), and Magnetron 25Sputtering, among others.
In combination or independently, in the process, it may also be desirable to remove one or more materials from the device during the manufacturing process. The removal process may include, for example, a wet etching technique, a dry etching technique, or a lift-off (lift-off) process, depending on the material to be removed. The materials forming the circuit elements described herein may be patterned using known exposure (lithographic) techniques, such as photolithography or electron beam exposure.
For brevity, conventional techniques related to semiconductor and/or superconducting devices and Integrated Circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, the various steps in the fabrication of semiconductor and/or superconducting devices and semiconductor/superconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.
The embodiments described above by referring to the drawings are exemplary only and are not to be construed as limiting the present application.
For purposes of clarity, technical solutions, and advantages of embodiments of the present application, one or more embodiments have been described above with reference to the accompanying drawings. Wherein like reference numerals are used to refer to like elements throughout. In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that such embodiments may be incorporated by reference herein without departing from the scope of the claims.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
The foregoing detailed description of the construction, features and advantages of the present application will be presented in terms of embodiments illustrated in the drawings, wherein the foregoing description is merely illustrative of preferred embodiments of the application, and the scope of the application is not limited to the embodiments illustrated in the drawings.
Claims (10)
1. A test junction for fabricating a superconducting quantum chip, the test junction defining a junction region and a test region, the test junction comprising:
a superconducting film including an integrated junction electrode and a first test electrode having no oxide on the surface; and
the second test electrode is laminated on the surface of the first test electrode;
wherein the junction electrode is located in a junction region and constitutes a superconducting layer of a Josephson tunnel junction, and the first test electrode is located in a test region;
the first test electrode and the second test electrode have different materials, and the hardness of each oxide is determined by the materials such that the hardness of the oxide of the first test electrode is greater than the hardness of the oxide of the second test electrode.
2. The test junction of claim 1, wherein the material of the first test electrode comprises tantalum or niobium;
or, the second test electrode is aluminum;
alternatively, the two superconducting layers in the Josephson tunnel junction have the same extension direction;
alternatively, the two superconductive layers in the josephson tunnel junction have different directions of extension;
alternatively, the two superconductive layers in the josephson tunnel junction are perpendicular to each other.
3. The test junction of claim 1, wherein the test junction comprises at least one josephson tunnel junction;
optionally, at least part of the josephson tunnel junctions in the test junction form a superconducting quantum interferometer.
4. The test junction according to any of claims 1 to 3, characterized in that the test structure further comprises a first transmission line and a second transmission line, the central signal line of the first transmission line being connected to one of the superconducting layers of the josephson tunnel junction, the central signal line of the second transmission line being connected to the other superconducting layer of the josephson tunnel junction.
5. Use of a test junction according to any one of claims 1 to 4 in the manufacture of a superconducting quantum chip;
optionally, the test junctions are used to screen manufacturing process or structural parameters of superconducting qubits.
6. The use of claim 5, comprising measuring junction resistance of a josephson junction with the test junction;
the method of measuring includes:
based on the probe method, the measurement is performed by puncturing the second test electrode to make electrical contact with the first test electrode.
7. A method of fabricating a superconducting qubit, the method comprising:
determining fabrication parameters of superconducting qubits, wherein the fabrication parameters comprise structural parameters of josephson tunnel junctions, the structural parameters being determined by testing and screening using a plurality of test junctions of any one of claims 1 to 4 having different configurations;
the superconducting qubit is fabricated by performing a micro-nano processing method based on the fabrication parameters.
8. A method of manufacturing a test junction, the method comprising:
depositing selected regions of the superconducting film of the josephson junction to form a second test electrode;
the superconducting film comprises a junction electrode and a first test electrode, wherein the junction electrode is positioned in a defined junction area, and the first test electrode is positioned in a test area which is defined to be far away from the junction area;
the selected area is a deposition window of a first test electrode positioned in the test area, and the surface of the first test electrode is removed with an oxide layer;
the hardness of the oxide of the first test electrode is greater than the hardness of the oxide of the second test electrode.
9. The method of fabricating a test junction according to claim 8, wherein the window is formed by undercut photoresist etching the first test electrode prior to fabricating the second test electrode by deposition.
10. The method of manufacturing a test junction according to claim 9, wherein the undercut photoresist is retained after manufacturing the test junction.
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