JPH03263884A - Manufacture of josephson integrated circuit - Google Patents

Abstract

PURPOSE:To enable a critical current to be increased at a contact part or a stepped part and further to contribute to improvement in integration and miniaturization of a Josephson integrated circuit by applying a high-frequency bias power to a substrate when forming an upper-side superconductive wiring layer by the sputtering method with an inactive gas. CONSTITUTION:A surface of a second Nb layer 14 and that of a first Nb layer 14 which are exposed within a contact hole are subjected to Ar sputter cleaning before forming a third Nb layer 16. Then, the third Nb layer 16 is formed on the entire surface by DC magnetron sputtering. In that case, a high-frequency bias power is being applied to a substrate.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a Josephson integrated circuit, more specifically, a method for manufacturing a Josephson integrated circuit having fine contacts and superconducting wiring, in which the upper superconducting wiring is sputtered. To provide a method for forming an upper superconducting interconnect that can increase critical current by avoiding a decrease in the thickness of the interconnect at a step portion (side wall portion) such as a contact hole when forming the upper superconducting interconnect. For the purpose of manufacturing a Josephson integrated circuit, a lower superconducting wiring layer, an insulating layer having a stepped portion, and an upper superconducting wiring layer covering the insulating layer including the stepped portion are sequentially formed on a substrate. In the method,
The configuration is such that high frequency bias power is applied to the substrate when forming the upper superconducting wiring layer by sputtering with an inert gas.

[Industrial application field]

The present invention For more details, see joseph so with wiring related.

a method for manufacturing integrated circuits; Fine details of superconductivity and superconductivity integrated circuit manufacturing method. [Conventional technology] A typical Josephson integrated circuit is Nb/in.

/Nb structure Josephson junction element, Nb (niobium) superconducting wiring, interlayer insulating layers such as 5102, S+3Nm, and resistance layers such as Mo, Ti, Zr, and W, and these are laminated to form a circuit configuration. be done. In order to increase the degree of circuit integration, it is necessary to reduce the junction area, further reduce the contact area between wirings and the dimensions (thickness, width) of the wirings.

[Problem to be solved by the invention]

A contact structure for connecting lower superconducting wiring 1 and upper superconducting wiring 2 in a Josephson integrated circuit through a contact hole provided in interlayer insulating layer 3 is as shown in FIG. These are laminated on an insulating substrate 4. For example, the thickness of the lower Nb superconducting layer 1 is 2001
m, and the thickness of the SiO□ interlayer insulating layer 3 is 250 to 350 nm.
It is m. When forming a contact hole in this insulating layer 3 by selective etching using a reactive ion etching (RIE) method, etc., as the contact area is reduced, the aspect ratio of the hole (insulating layer thickness/ The size of the contact hole becomes thicker, and the upper N
b When the superconducting layer 2 is formed in the contact hole and on the insulating layer 3 by normal direct current (DC) or radio frequency (RF) magnetron sputtering method, it adheres to the side wall in the contact hole as shown in Fig. 5. The thickness of the (deposited) Nb layer 2 becomes considerably thinner than the thickness of the Nb layer 2 deposited on the flat portion. For this purpose, a superconducting critical current 1. c is (1) the current flowing through the thin upper Nb layer 2 attached to the side wall of the contact hole, or (
2) It is determined by the smaller of the currents that can flow through the natural oxide film (removed as much as possible by sputter cleaning before forming the Nb layer) on the surface of the lower Nb layer at the bottom of the contact hole. Further, the current factor (1) above depends on the size of the contact hole and the hole aspect ratio, and the current factor (2) above depends on the contact area and sputter cleaning conditions. That is, the current of factor (1) is proportional to the side length of the contact hole, and the current of factor (2) is proportional to the area of the contact hole.

Therefore, in an experiment conducted by the inventors, results of the critical current Ic at the contact portion as shown in FIG. 6 were obtained. In this case, the thickness of the interlayer insulation (S102) layer 3 is 3
00 nm, the contact hole area was 1 to 9p2 (contact hole shape is square), and sputter cleaning was performed for 3 minutes at an applied voltage of 300 V in argon (Ar) of 10 mTorr before forming the upper Nb layer. Then, the upper Nb layer 2 was formed by DC sputtering with the thickness changed to 500 and 300 nm at 80° C., and the critical current was measured. As can be seen from FIG. 6, as the thickness of the Nb layer becomes smaller, the critical current also becomes smaller.

In particular, when the thickness is 800 nm, the critical current is approximately proportional to the contact area, and is determined by the factor (2) above. As the thickness of the Nb layer decreases, not only A, which has a small critical current, but also linearity deteriorates. This suggests that at a thickness of 500 nm or less, the critical current is determined by the factor (1) above.

In order to increase the integration density of Josephson integrated circuits, it is necessary to reduce not only the line width but also the thickness of the superconducting wiring, and as shown in Figure 6, when using thin Nb wiring, The reduction in the critical current of the contact portion is a major problem in terms of circuit operation.

An object of the present invention is to avoid a reduction in the thickness of the upper superconducting wiring at a step part (side wall part) such as a contact hole when forming the upper superconducting wiring by sputtering.
It is an object of the present invention to provide a method for forming an upper superconducting wiring that can increase critical current.

Another object of the present invention is to provide a method for manufacturing a Josephson integrated circuit that contributes to miniaturization of superconducting wiring and contacts that improves the degree of integration of the Josephson integrated circuit.

[Means to solve the problem]

The above-mentioned object is a method for manufacturing a Josephson integrated circuit, in which a lower superconducting wiring layer, an insulating layer having a stepped portion, and an upper superconducting wiring layer covering the insulating layer including the stepped portion are sequentially formed on a substrate. This is achieved by a method of manufacturing a Josephson integrated circuit characterized in that high frequency bias power is applied to the substrate when the upper superconducting wiring layer is formed by sputtering with an inert gas.

[For production]

In the present invention, the electric field of the bias power applied to the contact hole or the edge of the step portion of the insulating layer is concentrated, so that the inert gas (A
(r, etc.) ions will etch (re-sputter) the superconducting material (upper superconducting wiring) attached to the end. Then, the etched superconducting material re-attaches to the sidewalls or bottoms of the contact holes and stepped portions, causing the thickness of the superconducting wiring inside the contact holes to be less than the thickness of the superconducting wiring on the flat portions. L (10-20% thicker), and the thickness on the side wall is also thicker than in the conventional case.

This makes it possible to increase the critical current while miniaturizing the contact hole and the superconducting wiring.

The upper and lower superconducting interconnects are made of niobium, niobium compounds (NbN, Nb3Sn, Nb3Ge, etc.) and alloys (Nb-T+), and high-temperature oxide superconducting materials (Y-B
a-Cu-0°B 1-31-Ca-Cu-0, etc.) (especially Nb).

Also, the voltage of high frequency bias power is -100 to -300
V is preferable; lower voltages have a smaller effect, while higher voltages deteriorate the superconducting properties of the film itself and cause excessive removal of the portions corresponding to the ends of the insulating layer of the upper superconducting wiring to be formed. This causes a problem that the thickness becomes thinner than on the flat part.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of embodiments with reference to the accompanying drawings.

First Embodiment As shown in FIGS. 1 and 2a-2d, a Josephson integrated circuit is fabricated in accordance with the present invention as follows.

First, a silicon single crystal substrate is thermally oxidized to form a 5in2 insulating layer, and this is used as the substrate 11. Then, as shown in FIG. 2a, an 11Nb layer 12 is deposited on this substrate 11 to a thickness of 100 to 100 nm by normal DC magnetron sputtering.
It is formed (deposited) on the entire surface with a thickness of 200 nm.

A1 layer (thickness: about 7 nm) for Josephson junction
is formed on the first Nb layer 12 by DC magnetron sputtering, and oxygen is introduced into the vacuum chamber of the sputtering device to form an AAO, layer (thickness: 1 to 2 nm). Form. Bonding layer 1
A second Nb layer 14 is formed on the substrate 3 by DC magnetron sputtering to a thickness of 30 to 200 nm.

Next, as shown in FIG. 2b, a photoresist layer 20 is photolithographically formed on the second Nb layer 14 in the shape of a Josephson junction. Using this resist layer 20 as a mask, RI using CF and gas as an etchant
The second Nb layer 14 is removed using E and then the i-^β junction layer 13 is removed by sputter etching using Ar, leaving the portion covered by the resist layer 20.

As shown in FIG. 2C, a photoresist layer 21 having a predetermined wiring pattern is formed on the second Nb layer 14 and the first Nb layer 12 by photolithography.

Using this resist layer 21 as a mask, the first Nb layer 12 is selectively etched by RIE using CF and gas.

Next, as shown in Figure 2d, 5102 insulation layers (thickness +
C) I
81 by RIE using F3 gas as an etchant.
02 layer 15 is selectively etched to form contact holes 22 at junctions and contact holes 2 for connecting interconnections.
form 3.

As shown in FIG. 1, before forming the third Nb layer 16, the surfaces of the second Nb layer 14 and the first Nb layer 12 exposed in the contact hole are cleaned by Ar sputtering. The cleaning conditions are a pressure of 1.3 Pa, an applied voltage of -200 to -300 V, and a shatter time of 2 to 5.
It's a minute. Then, the third Nb layer 16 (thickness: 300~
600nm) to DC? It is formed on the entire surface by Dunnetron sputtering, and at that time, high frequency bias power (frequency: 13.56 MHz, voltage knee 100 to -300
V) is kept applied. Sputtering is performed with this bias applied. The film formation rate is 100 to 200 nm/min. A resist layer (not shown) is formed according to the usual phosphorography method, and CF2
The third Nb layer 16 is selectively etched by RIE using etching to form a predetermined wiring pattern.

A Josephson integrated circuit having a contact portion A and a Josephson junction portion B can be manufactured by the above-described process. In addition, in an actual integrated circuit, it is necessary to form a superconducting ground plane, a resistance layer, a Josephson junction control line, and an interlayer insulating layer accompanying these, but these steps are performed according to known processes. Since it is only necessary to form it, its explanation will be omitted in this specification.

In the contact portion shown in FIG. 1, the contact characteristics between the first Nb layer (lower superconducting layer) 12 and the third Nb layer (upper superconducting layer) 16 were evaluated under the following conditions.

The thickness of the first Nb layer 12 was 2001 m, the thickness of the Sin□ insulating layer 15 was 300 nm, and the thickness of the third Nb layer 16 was 300 nm or 500 nm. The shape of the contact hole 23 (Fig. 2C) is a square, and the lengths of the negative sides are 1.0, 1.5, 2.0, 2.5 and 3°O.
There were five types of pM. Sputter cleaning with Ar was performed at a pressure of 1.3 Pa and an applied voltage of -300 V for 3 minutes. The third Nb layer 16 is applied at a bias voltage (200V
.

150 V), and as a comparative example, sputtering was performed in an argon atmosphere (1.3 Pa) without applying a bias voltage (OV). The critical power Ic of such a contact portion was measured at 4.2 K (liquid helium temperature), and the obtained results are shown in FIG.

In FIG. 3a, the horizontal axis is the side length of the square contact hole, and the vertical axis is the critical current. As can be seen from FIG. 3a, the critical current is considerably larger, 2 to 10 times, when formed by bias sputtering than when no bias electric field is applied.

In particular, the improvement in critical current is remarkable when the contact area (length of one side of the square contact) is small (1.0 to 1.57 = =) and the Nb layer thickness is thin (300 nm). As shown in Figure 3a, the critical current has a linear relationship with the contact hole peripheral length, indicating that it is determined by the factor (1).Compared with the conventional sputtering method (non-bias sputtering method), The reason why the critical current can be increased with the same contact size (area) is thought to be due to the improvement of factor (1) above.

In addition, if the third Nb layer formed by bias sputtering is as thick as 500 nm, a critical current of 180 mA will occur with a 2.0p angle contact, and the Nb layer with a thickness of 800 nm without bias (Figure 6) will have a critical current of 180 mA. Critical current (approximately 60m
A) Much larger. The critical current of the former is shown in (2) above.
The latter is thought to be determined by the factor (1) above. Therefore, in the case of bias sputtering (former), the critical current determined by the factor (2) above is naturally 180 m
(This is because the critical current is determined by the smaller of factors (1) and (2).) - On the other hand, the critical current determined by factor (2) above is:
Originally, it should be determined only by the sputter cleaning conditions before Nb film formation, and should not depend on the thickness of the upper Nb layer.

Therefore, in the case of bias sputtering, the fact that the critical current determined by factor (2) above is large is considered to be due to the fact that bias sputtering is used. it is,
This is considered to be because the natural oxide film on the surface of the lower Nb layer is removed again by applying a high frequency bias immediately before or at the beginning of bias sputtering film formation. [In normal sputter Nb film formation, a thin oxide film is expected to be formed again on the Nb surface during several minutes after sputter cleaning of the lower Nb layer and before Nb is formed. This oxide film can also be removed by bias sputtering. ] Therefore, in forming the Nb layer by bias sputtering, it is preferable to apply only a bias electric field to the substrate in advance and then start bias sputtering film formation.

Another feature of the contact using bias sputtered Nb is that it has excellent annealing resistance. Generally, the critical current of Nb interconnects and contacts is degraded by annealing even in a nitrogen atmosphere. The reason for this is thought to be that oxygen in the Nb oxide film formed on the surface diffuses into the Nb film. Figure 3b shows the annealing characteristics of the contact. The vertical axis represents the critical current ratio before and after annealing, and the horizontal axis represents the annealing temperature. In the case of Nb without applying bias,
Even with 200° C. annealing, the critical current decreases to 10% of its original value. On the other hand, when a bias is applied, the deterioration of the critical current is at most 10 to 40%. The reason for this is thought to be that the thicker Nb film on the contact sidewall portion reduces the influence of oxygen diffusion during annealing. In this way, the contact using bias sputtered Nb not only has a larger critical current, but also shows a remarkable improvement in annealing resistance.

Second Embodiment Step coverage in forming superconducting wiring (Nb film) by sputtering with a bias electric field applied to the substrate will be explained with reference to FIGS. 4a and 4b.

The shape of the Nb layer 34 formed by bias sputtering largely depends on the step shape of the underlying insulating layer 33, as shown in FIG. 4a. A first Nb layer 32 is formed on a substrate 31 similar to that of the first embodiment by normal sputtering, formed into a predetermined pattern by selective etching, and then insulated (S102).
When the layer 33 is formed (deposited) by normal sputtering, a step that is not smooth and has a concave shape (reverse tapered step) may occur at the step of the base (Nb layer). If a second Nb layer (wiring) 34 extending over the step is formed on this insulating layer 33 by bias sputtering, the film thickness may become thinner at the end of the step, as shown in FIG. 4b. . In this case, the critical current of the Nb layer (superconducting wiring) 34 is determined by the thin portion at the step and becomes low.

In order to prevent such a decrease in critical current, as shown in FIG.
After forming (filming) 5 thinner than in the case of Fig. 4a,
Subsequently, the third Nb layer 36 may be formed by normal sputtering without applying a substrate bias. 2nd and 3rd Nb
Layers 35 and 36 form one Nb layer,
It has a two-layer structure.

For example, the thicknesses of the second and third Nb layers 35 and 36 are both 300 nm. It is also possible to have a multilayer structure instead of two layers, and even in this case, the lowermost Nb layer is formed by bias sputtering. In this example, the thickness of the Nb layer at the step sidewall can be made thicker than before by applying a bias electric field to make the Nb layer step surface profile (profile) gentler and forming an additional Nb layer thereon. (1) Critical current determined by factors can be increased.

〔Effect of the invention〕

As mentioned above, according to the present invention, the upper superconductor (Nb)
It is possible to increase the critical current at the contact portion or step portion by applying a substrate bias during wiring formation or film formation. Furthermore, even a fine contact hole can prevent a decrease in the critical current of the upper superconducting wiring, making it possible to form a fine wiring structure, contributing to improved integration and miniaturization of Josephson integrated circuits. Furthermore, a significant improvement can be seen in terms of stability against annealing treatment.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a Josephson integrated circuit manufactured by the manufacturing method according to the present invention, and FIGS. FIG. 3a is a schematic cross-sectional view of superconducting (Nb) in the contact hole.
FIG. 3B is a graph showing the relationship between the critical current of the wiring and the side length of the rectangular contact hole, FIG. 3B is a graph showing the change in the critical current of the contact due to annealing, and FIG. FIG. 4b is a schematic partial cross-sectional view of the Josephson integrated circuit showing a two-layer structure of superconducting (Nb) wiring at a stepped portion; FIG. , is a schematic cross-sectional view of a Josephson integrated circuit having an upper superconducting interconnect formed by conventional sputtering, and FIG. 6 shows the relationship between critical current and contact hole area of a superconducting (Nb) interconnect formed by conventional sputtering. It is a graph showing a relationship. 11... Substrate, 12.14... Nb layer,
13...1 port, -A1 layer, 15...insulating layer, 16
...Nb layer by bias sputtering, A...contact part, B...Josephson junction, 32...N
b layer, 34.35...Nb layer formed by bias sputtering. Figure 2d Contact 1 - Hole side length (pm) Figure 3o Cross-sectional view of Josephson integrated circuit Figure 1 Figure 20 Figure 2b Figure 2c Figure 3b Figure 32 Figure 4b Cross-section of conventional Josephson integrated circuit 9 Figure

Claims (1)

[Claims] 1. A Josephson integrated circuit in which a lower superconducting wiring layer, an insulating layer having a stepped portion, and an upper superconducting wiring layer covering the insulating layer including the stepped portion are sequentially formed on a substrate. A method for manufacturing a Josephson integrated circuit, characterized in that when forming the upper superconducting wiring layer by sputtering with an inert gas, high frequency bias power is applied to the substrate. 2. The upper and lower superconducting wirings are made of niobium, niobium compounds and alloys, and high-temperature oxide superconducting materials, and the voltage applied by the high-frequency power is -100 to -300V. Claim 1 characterized by
Manufacturing method described.