JPH0322101B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit made up of semiconductor elements.

The main configuration of an output circuit of a typical semiconductor device is shown in FIG. That is, it consists of 3 and 4 MOSFETs with two series connections between V _DD and V _SS , and the input signal is transmitted to gate electrodes 1 and 2 in a differential manner, and the output terminal 6 goes high accordingly. , and are supposed to output low level respectively. Also gate 1,
When transistors 2 and 2 are both at ground level, transistors 3 and 4
are both turned off, and the output terminal 6 becomes a high impedance state. The diode 9 is formed by a PN junction between the commonly connected source and drain regions of the transistors 3 and 4 and the substrate.
Here, when this output circuit is in a high impedance state and a negative voltage is applied from the outside to the output terminal 6, the source potential of the transistor 3 whose gate is at the ground level becomes a negative potential, and the absolute value of this negative potential becomes the absolute value of the transistor 3. When the voltage becomes larger than the threshold, the transistor 3 is turned on. This on state is performed in a pinch off state, so that an impact ionization current is generated in the transistor 3, and a large number of holes are injected into the substrate. Therefore, along with the abnormal current flowing through the transistor 3, the substrate potential, which is biased to a negative potential different from the power supply potential and ground potential by the built-in substrate potential generation circuit, also rises due to hole injection into the substrate. This lowers the effective threshold of transistors in the circuit, leading to malfunction. Note that since the substrate potential generation circuit is a charge pump circuit that uses charging and discharging to a capacitor, the output impedance is large. Therefore, it does not have the ability to prevent an abnormal potential rise due to hole injection or the like.

The purpose of the present invention is to provide a means for solving this new failure mode.

Below, the cause of this failure mode will be elucidated and the effectiveness of the present invention will be explained.

This failure mode is attributable to the previously reported ionization current. That is,
When a MOSFET is operated in a pinch-off state, a hole current is observed in the substrate. This situation will be explained with reference to FIG. This Hall current (hereinafter i _B
) strongly depends on the source-drain voltage V _DS and has a peak near the threshold value for the gate potential V _GS . As shown in FIG. 4, i _B increases depending on the conductance Gm of the transistor, so i _B increases especially when the size of the output MOSFET is large. 1st
In the figure, when a negative voltage is applied to output terminal 6, but a value shallower than V _BB , MOSFET 3 or 4 is
Attempts to become ON. At this time, the potentials of the gates 1 and 2 are at the ground level, but since a negative potential is applied to the source, a positive potential is effectively applied between the gate and the source. For example, if this negative voltage is about -1v, the threshold of the output MOSFET is +0.5v.
If it is, the output MOSFET will be in the ON state. In MOSFET 3, V _DS becomes 6 V when using a +5 V power supply, resulting in a large Hall current i _B3 flowing. Also, in the case of MOSFET4, V _DS is
Since it is about 1V, the Hall current will only flow about i _B1 . This hole current is absorbed by the substrate potential generation circuit, but because its ability is weak, the substrate potential becomes shallow, and depending on the degree, it disappears. In this state, the diode 9 is forward biased, which adversely affects the peripheral circuits as described above.

The present invention is designed for output for such negative voltage application.
This provides a means to prevent the MOSFET from turning on.

According to the present invention, in an output circuit whose main component is a series connection of two MOSFETs (for example, N-channel type) of a semiconductor device incorporating a substrate bias generation circuit, a voltage that forward biases the MOSFETs is applied. (for example, a negative voltage) is applied to the output terminal of the output circuit.
A semiconductor circuit is obtained in which at least one gate electrode of the MOSFET is provided with means for transmitting the voltage. The means has a grounded gate electrode, and its source and drain are respectively connected to the output circuit.
It is connected to the gate and source or drain of the MOSFET, and its threshold value is that of the output circuit.
Set lower than MOSFET threshold
Can be configured with MOSFET. An embodiment of the present invention will be described below with reference to FIG. The circuit of the present invention is achieved by inserting a MOSFET 8 between the gate electrode 1 and the source 6 of the output MOSFET 3, that is, the output hemp terminal. The threshold value of this MOSFET8 is for output
It is set smaller than the threshold of MOSFET3. In a normal operating state, the output terminal 6 takes a value between the ground level and the MOSFET 8 is in an OFF state because its gate electrode is grounded, and has no effect on the circuit operation. However, when there is no output signal and gates 1 and 2 are fixed at ground level, MOSFET 3 is fully turned on at output terminal 6.
When a negative voltage sufficient to
The potential of the output terminal 6 is set to the same potential as that of the output terminal 6. Therefore, output MOSFET3 cannot be turned on.
Since MOSFET 8 can be made sufficiently smaller than output MOSFET 3, that is, the capacitance to be driven is sufficiently small, the Hall current generated by this MOSFET is absorbed by the ability of the substrate potential generation circuit, causing the failure mode described above. will disappear. In this manner, the circuit of the present invention can effectively prevent malfunctions caused by external noise without requiring a complicated configuration.

Although the present invention has been described above with respect to an N-channel MOST, the present invention can be similarly applied to a P-channel MOST.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional output circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the relationship between Hall current and gate potential, and Fig. 4 is a diagram showing the relationship between Hall current and gate potential. FIG. 3 is a diagram showing the relationship with the conductance of a transistor. 1 and 2 are gate electrodes that receive differential input, 3 and 4 are MOSFETs for output, 5 is a power supply, 6 is an output terminal, 7 is a GND potential, and 8 is a MOSFET inserted according to the present invention.

Claims (1)

[Claims] 1 first and second field effect transistors provided on a semiconductor substrate of one conductivity type, connected in series between a power supply terminal and a ground terminal, and having an internal signal applied to their respective gate electrodes; an external output terminal provided at a connection node of the second field effect transistor, and a substrate potential generation circuit that supplies the semiconductor substrate with a predetermined potential different from both of the potentials applied to the ground terminal and the power supply terminal; In an output circuit in which the external output terminal assumes a high impedance state when gate electrodes of the first and second transistors are both at an inactive level, a source and a drain electrode are connected to the gate electrode of the first field effect transistor and the external output terminal. the first terminal, the gate electrode is connected to the ground terminal, and the threshold voltage is the first terminal.
The third field effect transistor is set lower than the field effect transistor of
A semiconductor circuit characterized in that it is provided with a field effect transistor.