JPH0322063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor device having a memory in which the presence or absence of information writing is known depending on the presence or absence of a carrier injected into a substrate or the like.

Conventionally, a semiconductor device as shown in FIG. 1 has been known in principle.

In the figure, 1 is an n-type silicon semiconductor substrate, 2
is a field insulating film, 3 is a p-type well, 4 is a gate insulating film, 5 is a silicon gate electrode, and 6 is an n ⁺
The type impurity regions are shown respectively. In this device, silicon gate electrode 5 is connected to word line Wd, and impurity region 6 is connected to bit line Bt.

Now, the operation of this conventional example will be explained. First, the bit line Bt is set to 0 [V], and when a voltage V ₁ (V ₁ >Vth) is applied to the word Wd, the interface between the well 3 and the insulating film 4 is inverted to form an inversion layer. Since the carrier of the inversion layer (electrons in this case) is supplied from the bit line Bt, a current flows through the bit line Bt, region 6. In this state, when the voltage of the word line Wd is changed from V ₁ to 0 [V], some of the carriers in the inversion layer are injected into the p-type well 3, biasing it negatively. Therefore, it is assumed that "1" has been written. Then, Vth, which is the gate voltage for inverting the interface between the well 3 and the insulating film 4, becomes large, so even if the word line Wd is set to a potential of _V1 next time, the value of the current flowing through the bit line Bt becomes small. Therefore, it is possible to detect whether or not electrons are injected into the p-type well 3, which is a read operation. Note that this readout is a destructive readout. When "1" is written as described above, that is, when the p-type well 3 is negatively biased, in order to return to the original neutral state ("0" state),
It is sufficient to apply a high voltage _V2 to the bit line Bt, generate avalanche multiplication at the p/n junction surface, and inject holes into the p-type well 3. This results in writing "0".

Figure 2 shows the device shown in Figure 1 as an SOS (Silicon on
Sapphire), the operating principle is the same, and the major difference is that the substrate 1' is a single crystal insulator.

Now, in the device shown in Figures 1 and 2,
The maximum value of charge that can flow into the interface of well 3 and insulating film 4 is given by Q = AC _OX (V ₁ - V _th ) A: electrode area C _OX : insulating film capacitance per unit area, V ₁ Even if a voltage of V ₁ −V _th is applied, the voltage of V 1 −V th only acts to induce a charge Q.

Further, some of the electrons in the inversion layer return to the bit line _Bt , making it impossible to inject all the charges into the well 3. Furthermore, since electrons are injected into the well 3, if recombination does not occur within the well 3, they will flow out into the region 6 or, in the case of the device shown in FIG. 1, into the n-type substrate 1. Although a recombination center can be formed in well 3, p・n
It is difficult to avoid distributing recombination centers within the depletion layer of the junction. If recombination centers are distributed within the depletion layer, the leakage current of the p/n junction will increase, and the information storage time as a memory will become shorter.

For the reasons mentioned above, in the device having the structure shown in FIGS. 1 and 2, the p-type well 3 cannot be made sufficiently negative by a single "1" writing operation.

The present invention aims to improve the structure of the semiconductor device to enable highly efficient information storage, and will be described in detail below.

FIG. 3 is an explanatory side sectional view of a main part showing one embodiment of the present invention.

In the figure, 11 is an n-type silicon semiconductor substrate;
12 is a field insulating layer, 13 is a gate insulating film,
14 is a p ⁺ type barrier layer, 15 is a p type well region, 1
6 is an n ⁺ type carrier accumulation region, 17 is a silicon
Gate electrode, 18 is p ⁺ type transfer region, 1
Reference numeral 9 indicates an n ⁺ type carrier supply region, 20 a phosphosilicate glass film, and 21 an aluminum electrode/wiring.

The main difference between this embodiment and the device shown in FIGS. 1 and 2 is that it has an n ⁺ type carrier storage region 16. With this configuration, the maximum value of the charge flowing into the region 16 is: Q=AC _OX V ₁ A: Area of the electrode 17 excluding the overlapping portion with the regions 18 and 19 C _OX : It is given by the insulating film capacitance per unit area.

Now, the operation in this embodiment is as follows.

That is, the electrode/wiring 21 (bit line) is set to 0 [V]
When a voltage V ₁ is applied to the electrode 17 (word line), the surface of the transfer region 18 is inverted to form a channel, and a large amount of electrons flows from the region 19 to the region 16 and is accumulated.

When the voltage application to the electrode 17 is stopped, the channel on the surface of the transfer region 18 disappears, the electrons accumulated in the region 16 are retained as they are, and the number of electrons returning to the region 19 is extremely small.

When electrons are accumulated in region 16, it becomes negatively biased. Therefore, region 16 is in the forward direction when viewed from regions 15 and 18. However, in terms of potential, region 16 and regions 15 and 18 are equal, so the more electrons are accumulated in region 16, the more transfer region 1
V _th on the surface of 8 becomes high. Therefore, this state is used to indicate that "1" has been written.

When voltage V ₁ is applied to electrode 17 in this state, the current flowing through the bit line is extremely small compared to the previous case. Therefore, it can be read that "1" has been written. The current at this time is I ₁ ,
If the current that flows when no electrons are accumulated in the region 16 is I ₀ , then I ₀ > I ₁ , and this is defined as “0”,
It is sufficient if it corresponds to “1”.

The p ⁺ -type barrier layer 14 is formed to prevent even the slightest amount of electrons from the n ⁺ -type accumulation region 16 from flowing into the substrate 11 .

The device of this example is easy to manufacture.

As shown in FIG. 4, a field insulating layer 12 is formed on a substrate 11 by selective oxidation, and then a gate insulating film 13 is formed.

After boron ions are implanted using an ion implantation method to form a p ⁺ -type barrier layer 14, the implantation energy and dose are reduced to form a p-type well 15.

Similarly, phosphorus ions are implanted using the ion implantation method to form an n ⁺ -type accumulation region 16.

As shown in FIG. 5, a polycrystalline silicon layer is formed by chemical vapor deposition and patterned by photolithography to form a silicon gate electrode 17.

The gate insulating film 13 is patterned using the electrode 17 as a mask to expose a part of the surface of the substrate 11.

Boron ions are implanted using the ion implantation method to make p ⁺
After forming the type transfer region 18, phosphorus ions are implanted to form the n ⁺ type carrier supply region 19.

Thereafter, a phosphosilicate glass film, electrode contact windows, and electrodes/wirings are formed using conventional techniques to obtain the device shown in FIG. 3.

Here, dimensional data regarding the embodiment in FIG. 3 will be listed.

Thickness of field insulating layer 12 l ₁ : About 8000 [Å] Thickness of gate insulating film 13 L ₂ : About 600 [Å] P ⁺ type Barrier layer 14 Thickness l ₃ : About 3000 [Å] P ⁺ type Depth l ₄ of barrier layer 14: about 1 [μm] Depth l ₅ of n ⁺ type carrier accumulation region 16:
Thickness l ₆ of silicon gate electrode 17 approximately 3000 Å:
Thickness l ₇ of p ⁺ type transfer region 18 of about 4000 [Å]:
Depth l ₈ of n ⁺ type carrier supply area 19 of about 3000 [Å]:
Thickness of the phosphosilicate glass film 20: about 3000 [Å] Thickness l ₉ of the electrode/wiring 21: about 6000 [Å] Thickness l ₁₀ of the electrode/wiring 21: about 7000 [Å] Figures 6 to 8 show the present invention in SOS format. This figure shows an example implemented in the apparatus shown in FIG. Note that in all three embodiments, aluminum dioxide, ie, sapphire, is used for the substrate 11'.

In the embodiment shown in FIG. 6, an island-shaped semiconductor layer is formed into a mesa shape by etching. Further, since it does not have a p-type well region, the impurity concentration of the carrier accumulation region 16 is set low. However, the transfer region 18 must have a high impurity concentration because V _th must change greatly with respect to a predetermined substrate bias.

In the embodiments shown in FIGS. 7 and 8, an island-shaped semiconductor layer is obtained by forming a field insulating layer 12. In the embodiment shown in FIGS. In the embodiment shown in FIG. 8, the p-type well region 1
5. An n ⁺ type carrier accumulation region 16 is provided,
The structure is similar to that of the embodiment shown in FIG.

Figure 9 shows the device of the present invention as a matrix memory.
This is a diagram showing a cell array, and the main parts are shown as capacitors. Samp is a sense amplifier, Dio is a data input/output circuit, Wd is a word line, Bt is a bit line, Vin is an input terminal, and V _put is an output. Each end is shown.

As can be seen from the above description, according to the present invention, a carrier storage region of one conductivity type is opposed to a carrier supply region of one conductivity type connected to a bit line via a transfer region of an opposite conductivity type, and the carrier storage region of one conductivity type is opposed to the carrier supply region of one conductivity type connected to the bit line. A semiconductor device having a structure in which electrodes are provided on the carrier region and the carrier storage region through a thin insulating film is obtained,
According to this device, a large amount of carrier, ie, a high information level, can be stored while applying the same voltage as conventional devices, so that the operating efficiency is extremely good.

[Brief explanation of the drawing]

1 and 2 are side cross-sectional explanatory views of the main parts of different conventional examples, FIG. 3 is a side cross-sectional view of the main parts of an embodiment of the present invention, and FIGS. 4 and 5 are the embodiment shown in FIG. FIGS. 6 to 8 are side sectional explanatory views of essential parts showing different embodiments of the present invention, and FIG. The figure is an explanatory diagram of the device of the present invention assembled in a matrix. In the figure, 11 is a substrate, 12 is a field insulating layer, 13 is a gate insulating film, 14 is a barrier layer, 15 is a
16 is a well region, 16 is a carrier storage region, 17 is a gate electrode, 18 is a transfer region, 19 is a carrier supply region, 20 is a phosphosilicate glass film, and 21 is an electrode/wiring.

Claims (1)

[Claims] 1. A high impurity concentration carrier supply region of one conductivity type formed on the surface of a semiconductor layer of one conductivity type, a high impurity concentration transfer region of the opposite conductivity type in contact with the carrier supply region, and a high impurity concentration carrier of one conductivity type in contact with the same. an accumulation region; a well region of opposite conductivity type formed to cover the transfer region and the carrier accumulation region; a high impurity concentration barrier layer of opposite conductivity type formed to cover the well region; and the transfer region. and a gate electrode formed over the carrier accumulation region with a thin insulating film interposed therebetween.