JPH03212747A - Computer device - Google Patents

Abstract

PURPOSE:To realize the computer device to get out from a non-ready state and continue the succeeding processing by controlling the device to forcedly end a read/write signal when an end signal is not formed even after the lapse of a prescribed time. CONSTITUTION:A protection circuit 4 monitors the state of a ready signal B, and when the ready signal B continues the non-ready state for previously determined time in the system, forcedly forms a ready signal F and sends the signal F to a CPU 1. The CPU 1 turns a read/write signal C to an end state in response to the generation of the forced ready signal F. Thus, necessary processing can be continued.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a computer device, and more particularly to a method for controlling read/write of a memory in a computer device.

Technical field Conventionally, when accessing memory or input/output devices in computer equipment, the access time for these memories is C
When the CPU cycle time is slower than the CPU cycle time, CPU ready control is performed to extend the CPU cycle time so that these memories are apparently in time for the CPU access time.

FIG. 3 is a block diagram of such a conventional computer device, in which the CPU generates an address A to read and write the memory 3 and performs memory access (C). Memory 3 performs input/output control of data D in response to this access C, and reads/writes!・When the operation is completed, the end signal E
occurs.

When the ready control circuit 2 receives this end signal E, it generates a ready signal B to notify the CPU that the read/write of the memory has ended.

FIG. 4 is a time chart showing the read/write operation of the CPUI to the memory 3, and FIG. 5 is a time chart showing ready control. The operation of the conventional example will be explained with reference to FIGS. 3 to 5.

When the CPUI reads or writes to the memory 3, it outputs an address signal A and a read or write signal C to the memory 3. The memory 3 controls the output of the data D or human input based on the address signal A and the read/write signal C from the CPU (FIG. 4).

In these series of operations, the minimum time of the control signal C output by the CPU 1 to read/write the memory 3 is predetermined by the CPU. If memory 3
If the time required to read/write is longer than the minimum time of read/write signal C, read/write signal C
needs to be made as long as necessary. Ready signal B performs this control.

Ready signal B of CPUI is in non-ready state (logic “0”)
At this time, the address signal A and the read/write signal C continue to be output until the ready signal B becomes ready (logic "1"). When the CPUI reads or writes the memory 3, the ready control circuit 2 keeps the ready signal B in a non-ready state. The memory 3 detects that the read/write signal has been valid for a required period of time and outputs a read/write end signal E.

Ready control circuit 2 is this read dry!・Receive the end signal E and set the ready signal B to the ready state.

The CPUI detects that the ready signal B has become valid and ends the read/write operation (FIG. 5).

In this way, even if the time required to read and write the memory is longer than the read/write control signal of the CPU, the process can be performed normally by increasing the time by the necessary amount. .

In the conventional computer device described above, if the CPU accesses a memory or input/output device that does not exist, the ready state remains in a non-ready state, and the access cycle does not end, making it impossible to continue processing. It disappears. Normally, in such a case, it is necessary to perform some kind of error handling, but there is a problem in that error handling cannot be done because the access cycle is not completed.

OBJECTS OF THE INVENTION An object of the present invention is to provide a computer device that monitors the ready state of memory accessed by a CPU, extracts it from the non-ready state, and continues subsequent processing.

According to the present invention, the present invention includes a processor and a memory accessed by the processor during the generation of the read/write signal from the Bromo Sosa, and the memory is configured to read/write in response to the generation of the read/write signal from the Bromo Sosa. A computer device configured to generate a read/write termination signal after a time period necessary for accessing its own memory, and to terminate generation of the read/write signal in response to generation of the termination signal. Accordingly, there is obtained a computer device characterized in that it has a termination signal monitoring means for controlling the read/write signal to be forcibly terminated when the termination signal is not generated even after a predetermined period of time has elapsed.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts and signals equivalent to those in FIG. 3 are indicated by the same symbols. In this embodiment, a protection circuit 4 is added between the ready control circuit 2 and the CPUI.

This protection circuit 4 receives a ready signal B from the ready control circuit 2.
It has a function of constantly monitoring the state of the controller and generating a forced ready signal F if the non-ready state continues for a certain period of time or more and the ready state is not reached.

FIG. 2 is a diagram showing such an operating state as a time chart 1. If the long-term end signal E is not generated from the memory in response to memory access (C) from the CPUI,
The ready control circuit 2 does not generate the ready signal B and remains in the non-ready state.

Therefore, the protection circuit 4 monitors the state of the ready signal B, and if the ready signal B continues to be in a non-ready state for a predetermined period of time in the system, it forcibly generates a ready signal F and sends it to the CPUI. Therefore, in response to the generation of this forced ready signal F, the CPUI brings the read/write signal C to an end state.

Therefore, even when the memory to be accessed does not exist or when a failure occurs in the memory and the termination signal E is not generated, the forced ready signal F is generated by the protection circuit 4, so that the CPU can perform subsequent processing. For example, error handling can be performed.

Effects of the Invention As described above, according to the present invention, even if the CPU accesses a memory, input/output device, etc. that does not exist and remains in the non-ready state, the non-ready state can be restored by monitoring the ready signal. Since it can be forcibly extracted from the state, it has the effect of allowing subsequent necessary processing to continue.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the blocks in FIG. 1, FIG. 3 is a block diagram of a conventional computer device, and FIG. 4 is a memory shown in FIG. 3. Time charts 1, 5 showing the read/write operations of
The figure is a time chart showing the ready control of the block in FIG. 3. Explanation of symbols of main parts 1...CPU 2...Ready control circuit 3...Memory 4...Protection circuit

Claims (1)

[Claims] (1) A processor and a memory that is accessed by the processor during the generation period of a read/write signal from the processor, and the memory has a memory that is accessed for a period of time necessary for accessing its own memory in response to the generation of the read/write signal. The computer device is configured to generate a read/write end signal after a predetermined period of time has elapsed, and the processor is configured to end the generation of the read/write signal in response to generation of the end signal, 1. A computer device comprising: a termination signal monitoring means for forcibly terminating the read/write signal when the read/write signal is not generated.