JPH05128851A - Dram control system - Google Patents

Abstract

PURPOSE:To efficiently realize the refreshing of a DRAM as a storing part without affecting the performance of an MPU and the design of an F/W. CONSTITUTION:An MPU 1 performs the read and write operation through a DRAM control part 5 to a DRAM part 6, and a refreshing request generating part 4 gives a request signal to perform the refreshing of the DRAM part 6 to the DRAM control part 5. At this time, a timer part 8 to perform a timer action considering the refreshing cycle period varied by the capacity of the DRAM part 6 and kind of using element and an MPU bus cycle checking part 7 considering the bus cycle of the MPU 1 give the refreshing request generating part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM control system, and more particularly to a DRAM control system for refreshing a DRAM section.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 2, a DRAM control system uses an MPU 1 to latch a latch unit 2 and a DRAM.
Required data is written to and read from the DRAM section 6 via the control section 5.

Conventionally, in this DRAM control system, D
The refreshing of the RAM unit 6 is configured to activate the refreshing of the DRAM unit 6 via the refresh request generating unit 4 by the output signal of the decoder unit 3 which receives the address information from the MPU 1. That is, the execution of the refresh cycle is requested by the output of the decoder unit 3 via the refresh request generation unit 4, and is executed within the time required for the DRAM unit 6 (for example, 8 mS).

[0004]

However, in this conventional DRAM control system, since the address signal output from the MPU 1 is decoded and the refresh operation is performed only by the decoded output result, the sub-block DMA transfer is performed. There was a limitation on F / W (microprogram) such as not being possible.

The present invention has been made in view of the above problems, and a DRAM control system for efficiently refreshing a DRAM section so as not to affect the performance of an MPU and the design of F / W. For the purpose of providing.

[0006]

In order to achieve the above object, the DRAM control system of the present invention uses a DRAM by an MPU.
Necessary data is written in and read from
In a DRAM control method for refreshing a DRAM section, a timer section for controlling a refresh cycle time for the DRAM section, a type of a bus cycle of an MPU are determined, and a refresh cycle is started based on the determination result of the type of the bus cycle. The MPU bus cycle check unit is provided.

If necessary, the MPU bus cycle check unit has a function of starting a refresh cycle after waiting for a bus cycle in which the MPU does not access the DRAM unit.

[0008]

According to the DRAM control system having the above structure,
The timer unit constantly monitors and controls the time for refreshing the DRAM unit, the MPU bus cycle check unit determines the type of MPU bus cycle, and the DRAM unit is refreshed based on the determination result of the type of bus cycle. Let it start.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing a DRAM control system according to an embodiment of the present invention.

In FIG. 1, 1 is an MPU, 2 is a latch unit, and the latch unit 2 latches an address signal from the MPU 1. A decoder unit 3 receives the output of the latch unit 2 and outputs a chip select signal. 5 is DRA
The M control unit generates a control signal for the DRAM unit 6. The DRAM section 6 is a memory circuit composed of a normal DRAM.

A timer unit 8 monitors the time for refreshing the DRAM unit 6 and outputs a refresh request signal to the refresh request generating unit 4 in a predetermined cycle. Reference numeral 7 denotes an MPU bus cycle check unit which determines the type of bus cycle of the MPU 1 and outputs a signal indicating whether a refresh cycle is possible. In the embodiment, the MPU bus check unit 7 uses the M
The PU 1 sends a signal for starting the refresh cycle to the refresh request generating section 4 after waiting for a bus cycle in which the DRAM section 6 is not accessed.

Further, the refresh request generation unit 4 uses the MP
When the output from the U-bus cycle check unit 7 and the decode output from the decoder unit 3 are both present, the DRAM
The control unit 5 is requested to perform the refresh operation.

Next, the operation of the embodiment will be described in detail. The MPU 1 writes and reads necessary data in the DRAM section 6. In that case, the DRAM control unit 5 supplies control signals such as a row address and a column address to the DRAM unit 6 according to the address signal, data, address strobe signal, and read / write control signal in accordance with the bus cycle of the MPU 1.

The DRAM section 6 needs to be refreshed periodically. Although the DRAM is also mapped in the address space accessible by the MPU1, refresh is executed when the DRAM unit 6 is not accessed in the bus cycle of the MPU1. Decoder unit 3 is M
The address signal from PU1 is decoded, information indicating that MPU1 is not accessing DRAM section 6 in the bus cycle is output, and refresh request generating section 4 is activated.

The timer unit 8 is a DRAM of the DRAM unit 6.
, The information requesting refreshing is output, and the refresh request generator 4 is activated. DRAM
If a device having a capacity of 1 Mbit is used as, a refresh cycle of 512 times is required within 8 mS. Therefore, the timer unit 8 is 15.6μ.
A refresh request signal is output every s.

The MPU 1 has a unique address space, can be accessed anywhere in the space, and executes bus cycles such as read cycles and write cycles. The MPU bus cycle check unit 7 detects that the bus cycle executed by the MPU 1 is not accessing the DRAM unit 6. Therefore, the DRAM controller 5
The refresh request generating unit 4 is activated.

The refresh request generation unit 4 receives the refresh start signal from the MPU bus cycle check unit 7 and the decode output from the decoder unit 3 as input, and receives the DRA.
Request the M control unit 5 to perform the refresh operation.
The refresh cycle is executed only when both of these two input conditions require refresh.

Further, the refresh request signal from the timer unit 8 causes a loss in the processing capability of the MPU 1, but it is surely received periodically to activate the refresh cycle, which is indispensable for guaranteeing the stored data.

That is, the MPU 1 performs the READ and WRITE operations on the DRAM section 6 via the DRAM control section 5, but the refresh request generating section 4 also performs DR.
DR request signal for refreshing AM section 6
It is given to the AM control unit 5. At this time, the DRAM controller 5
Performs CAS before RAS refresh.

Then, the refresh request generation unit 4 performs a timer operation in consideration of the refresh cycle period which differs depending on the capacity of the DRAM unit 6 and the element used, and the MP operation in consideration of the bus cycle of the MPU 1.
By issuing a refresh request with the U-bus cycle check unit 7, the limitation of F / W is prevented.

[0021]

As described above, according to the DRAM control method of the present invention, the refresh cycle time is controlled by the timer section and the refresh request is activated by the MPU bus cycle check section in consideration of the operation of the MPU bus cycle. Therefore, there is an effect that the refresh can be efficiently performed and the limitation on F / W in the sub-block DMA transfer and the like can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DRAM control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional DRAM control method.

[Explanation of symbols]

 1 MPU 2 Latch section 3 Decoder section 4 Refresh request generation section 5 DRAM control section 6 DRAM section 7 MPU bus cycle check section 8 Timer section

Claims (2)

[Claims] 1. A DRAM control system in which a MPU writes and reads necessary data to and from a DRAM section and refreshes the DRAM section.
A MPU bus cycle check unit for determining a refresh cycle time for the M unit and a MPU bus cycle check unit for determining the type of the MPU bus cycle and starting the refresh cycle based on the determination result of the type of the bus cycle. Characteristic DRAM control method. 2. The MPU bus cycle check unit comprises:
2. The DRAM control method according to claim 1, wherein the MPU has a function of starting a refresh cycle after waiting for a bus cycle in which the DRAM section is not accessed.