JPH0321057A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable inputting low-level signals by applying voltage generated by a voltage generation circuit to the gate of a high-dielectric strength MOS transistor. CONSTITUTION:The present inventions, which includes a high-dielectric strength MOS transistor 8 formed between an input terminal 6 and the gates of the MOS transistors of an input circuit 15 and a voltage generation circuit 10 to generate voltage outside the range of the source voltage based thereon, applies the voltage generated by the voltage generation circuit 10 to the gate of the high-dielectric strength MOS transistor 8. Therefore, when the high-dielectric strength MOS transistor 8 used is of a P channel type, the voltage generation circuit 10 generates lower voltage than the earth voltage VSS and applies said generated voltage to the gate of the high-dielectric strength MOS transistor 8. Thereby the signal level of the input terminal 6 to turn the high-dielectric strength MOS transistor 8 off can be lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a semiconductor integrated circuit composed of MOS transistors, and in particular to prevention of electrostatic damage when a high voltage is applied to an input terminal. .

(Example) Conventional technology Generally speaking, semiconductor integrated circuits (
(hereinafter referred to as an IC), an input terminal is connected to the gate of an input inverter via a protection resistor. However,
If a high voltage (for example, about -40V) is applied to the input terminal, the gate insulating film of the input inverter will be destroyed.

Therefore, conventionally, protection circuits shown in FIGS. 3 and 4 have been used.

In Figure 3, input terminal (1>) and input inverter (2)
), a resistor (3) and a P-/-Yannel MOS transistor (4) are connected in series, and the gate of the MOS transistor (4>) is connected to the ground voltage VSS.

Also, between the gate of the input inverter (2) and the ground, there is an N-channel MO whose gate is connected to the power supply voltage VDD.
An S+- transistor (5) is provided. This N-channel MOS transistor (5) functions as a pull-down resistor.

On the other hand, the circuit shown in FIG. 4 has the same circuit configuration as shown in FIG. 3, but a control signal XIODSB is applied to the gate of the MOS transistor (4). The control signal X I ODSB is connected to the ground voltage V5, (“L ++
It is a signal that becomes the power supply voltage V11 level) when input is not required, and is created by an internal circuit (not shown) that receives the output of the input inverter (2).

According to the circuits shown in FIGS. 3 and 4, when a voltage equal to or lower than the ground voltage Vss is applied to the input terminal (1), the MO
In order to output S transistor (4), input terminal (1)
The voltage applied to the inverter (2) is not applied to the gate of the inverter (2), thereby preventing electrostatic damage.

(c) Problems to be Solved by the Invention However, in the circuits of FIGS. 3 and 4 described above, the threshold value V tp of the MOS transistor <4> and the MOS
} Due to the bias voltage of the transistor (4), the threshold voltage seen from the input terminal (1) becomes high, making it impossible to input low-level signals. Transistor (5
) acts as a pull-down resistor, so the input terminal (1
), current flows through the MOS transistor (5), making it impossible to reduce power consumption.Furthermore, when an H'' level signal is applied to the input terminal (1), current flows through the MOS transistor (5), making it impossible to reduce power consumption. In this case, a voltage determined by the ratio of the combined impedance of the resistor (3) and the MOS transistor (4) to the impedance of the MOS transistor (5) is applied to the input inverter (2), and the input inverter There were cases where the threshold voltage of (2) was not reached.

(2) Means for Solving the Problems The present invention was created in view of the above points, and includes a high voltage MOS transistor provided between the input terminal and the gate of the MOS transistor of the input circuit, and a power supply voltage. and a voltage generation circuit that generates a voltage outside the range of the power supply voltage based on the voltage, and the voltage generated by the voltage generation circuit is transferred to a high voltage MOS.
It is applied to the gate of the transistor. Furthermore, it is provided with a level shift circuit which uses the voltage generated in the voltage generation path as a power source and to which a control signal for controlling the input of the signal applied to the input terminal is applied, and output signals of the level shift circuit 1 to 4 are applied. is applied to the gate of the high voltage MOS+- transistor.

(E) Effect In the above-mentioned means, when a P-channel type is used as the high voltage MOS transistor, the voltage generating circuit is connected to the ground voltage y
Generates a voltage lower than ss and uses this voltage as a high voltage MOS
By applying it to the gate of the transistor, high breakdown voltage M
The signal level of the input terminal at which the OS transistor is turned off can be lowered. Furthermore, since the output signal level of the level shift circuit to which the control signal is applied is a voltage lower than the voltage generated by the voltage generation circuit, that is, the ground voltage VSS, the high voltage MOS+- transistor is similarly turned off. The signal level of the terminal can be lowered. That is, since the threshold voltage seen from the input terminal becomes low, low-level signal input can be realized. Furthermore, by making the voltage generated by the voltage generation circuit sufficiently higher than the voltage level that destroys the MOS transistor in the input circuit, the high-voltage MOS transistor will be able to function effectively when a breakdown voltage is applied to the input terminal. This prevents destruction.

(to) Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.

(6) is an input terminal, (7) is a protection resistor, (8) is a P-channel type MOS transistor formed with high withstand voltage,
9〉 is an input inverter composed of (,-MOS, (1
0) is a voltage generation circuit. One end of the protective resistor (7) is connected to the input terminal (6), and the other end of the protective resistor (7>
The source of the OS transistor (8) is connected. The protective resistor (7) is usually formed as a diffused resistor in the semiconductor substrate, and this diffused resistor forms a common region with the source region of the MOS transistor (8). In order to make the MOS transistor (8) high withstand voltage, its gate insulating film is similar to that of other MOS transistors (8).
It is formed thicker than the gate insulating film of the transistor. Also,
The drain of the MOS transistor (8>) is connected to the gate of the input inverter (9>).

The voltage generation circuit (10) includes a ring oscillator (11), a capacitor (12), and MOS transistors (13) (14).
This is a well-known voltage generation circuit consisting of a ring oscillator (1
The AC signal outputted from the power supply voltage ■DD and the ground voltage Vss from the MOS+- transistor (13) (1)
4) to generate a negative voltage -■Bll. This voltage -VBB is the MOSI transistor (13) (14)
It can be set arbitrarily by the threshold voltage of
M when ground voltages V and S are applied to the input terminal (6)
The voltage is set to be at least as low as the threshold voltage including the influence of the backgate 1 bias of transistors O31 to transistor <8>, for example, to about -3.0V.

Therefore, the MOS transistor (8) to which the voltage -V RB of the voltage generating circuit (10) is applied is always in a state where an input signal voltage in the range from the ground voltage VSS to the power supply voltage VDD is applied to the input terminal (6). Since it is turned on, the input signal is reliably transmitted to the gate of the input inverter (9>).

Therefore, by setting the threshold voltage of the input inverter (9) low, low-level input is possible, and the pull-down MOS transistor (5) shown in FIGS. 3 and 4 is unnecessary. becomes.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. The input terminal (6), the protective resistor (7), the high voltage MOS transistor (8), and the voltage generating circuit (10) are the same as the circuit shown in FIG. 1, so their explanation will be omitted. Input circuit (5> is C
- It is a NOR gate composed of MOS, and the drain of the MOS transistor (8>) is connected to one input of the input circuit (15), and the other input is connected to the control signal XIODSB.
is applied. The control signal XI ODSB is a signal that controls the internal capture of the input signal applied to the input terminal (6>), and is set to the ground voltage Vss level when the capture is allowed, and is set to the ground voltage Vss level when the capture is prohibited. Power supply voltage v becomes DD level.Level shift circuit (16
) C, power supply voltage■. D and the voltage generated by the voltage generating circuit (10〉 -■, lR are used as power supplies, and the input control signal X
IODSB signal level is set to power supply voltage ■DD and voltage -V
This is to convert to the JIB level. Level shift circuit (16) (7) output signal XIODSB' is MOSI-
Connected to gate 1 of transistor (8).

8 In FIG. 2, the control signal XIODSB is set to the power supply voltage V
DD, the output signal XIODSB' is the power supply voltage V
DD level, the MOS transistor (8) is turned off, and the output of the input circuit (15) is at the ground voltage VSS.
fixed at the level. This prohibits the input signal applied to the input terminal (6) from being taken in. On the other hand, when the control signal XIODSB becomes the ground voltage VSS, the input circuit (15) has the same configuration as the C-MOS inverter, and the M
It becomes possible to output a signal according to the signal transmitted from the OS transistor <8>. Furthermore, a level shift circuit (16
) output signal XIODSB' is at the voltage -VBB level, so the MOS transistor (8) is completely turned on even if the signal applied to the input terminal (6) is at the ground voltage Vss level. The signal applied to the input terminal (6>) is transmitted to the input circuit (15).

Therefore, by setting the threshold voltage of the input circuit <15> low, it is possible to input a low-level signal, and a pull-down transistor is not required.

In addition, in the circuits of FIGS. 1 and 2, the input terminal (6
> When a negative high voltage is applied to the MOS transistor (
8), that is, the voltage applied to the gate of the voltage generating circuit (
10) because the output voltage -V BB will be significantly lower than
The MOSI transistor (8>) is completely turned off, preventing destruction of the input inverter (9) and input circuit (15).

In addition, the voltage generation circuit (10
> is P where an N-channel MOS transistor is formed.
It is also possible to use it also as a substrate bias generation circuit for biasing the type semiconductor layer.

In this case, the MOS transistor (
8) When increasing the gate voltage, the ground voltage V s
N-channel MOS or P-channel MO with drain and gate connected between s and substrate bias voltage output
A plurality of MOS transistors S are connected in series, and a voltage at an arbitrary connection point is applied to the gate of the MOS transistor (8).

(G) Effects of the Invention As described above, according to the present invention, it is possible to prevent electrostatic damage to input terminals with high input impedance, and it is also possible to input low input levels, thereby diversifying IC applications and increasing It has the advantage of improving reliability.Furthermore, since there is no need to provide a pull-down element, no current flows even if the "H+1" level is constantly applied to the input terminal, reducing power consumption in standby mode. It's also effective.

[Brief explanation of drawings]

Figures 1 and 2 are circuit diagrams showing embodiments of the present invention;
4 are circuit diagrams showing a conventional example. (6)...Input terminal, (7)...Protection resistor, (
8)...MOS transistor, (9)...input inverter, (10>...voltage generation circuit, (15)...
...Input circuit, <16>...Level shift circuit.

Claims (2)

[Claims] (1) MOS with an input terminal, a resistance element with one end connected to the input terminal, and a gate connected to the other end of the resistance element
In a semiconductor integrated circuit comprising a transistor, between the input terminal and the gate of the MOS transistor,
a high-voltage MOS transistor connected in series with the resistance element; and a voltage generation circuit that generates a voltage outside the range of the power supply voltage based on the power supply voltage, the voltage generated by the voltage generation circuit is High voltage MOS
A semiconductor integrated circuit characterized in that a voltage is applied to the gate of a transistor. (2) In a semiconductor integrated circuit comprising an input terminal, a resistance element having one end connected to the input terminal, and a MOS transistor having a gate connected to the other end of the resistance element, the input terminal and the MOS transistor between the gates of
a high-voltage MOS transistor connected in series with the resistance element; a voltage generation circuit that generates a voltage outside the range of the power supply voltage based on the power supply voltage; and a voltage generated by the voltage generation circuit as a power supply; and a level shift circuit to which a control signal for controlling the input of the signal applied to the input terminal is applied, and an output signal of the level shift circuit is applied to the gate of the high voltage MOS transistor. integrated circuit.