JPH03209753A - Electronic parts - Google Patents
Electronic partsInfo
- Publication number
- JPH03209753A JPH03209753A JP513490A JP513490A JPH03209753A JP H03209753 A JPH03209753 A JP H03209753A JP 513490 A JP513490 A JP 513490A JP 513490 A JP513490 A JP 513490A JP H03209753 A JPH03209753 A JP H03209753A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- parts
- lead
- package
- soldering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000003779 heat-resistant material Substances 0.000 claims abstract description 7
- 239000006071 cream Substances 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract description 7
- 230000006355 external stress Effects 0.000 abstract description 3
- 230000002787 reinforcement Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000011176 pooling Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はラジオ受信機、テレビ受像機、ビデオテープレ
コーダー、通信機器、電子計算機等に使用されるＩＣパ
ッケージその他の電子部品に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to IC packages and other electronic components used in radio receivers, television receivers, video tape recorders, communication equipment, electronic computers, and the like.
従来の技術
近年、ＩＣパッケージその他の電子部品は、電子機器の
小型軽量化さらに高機能化に伴なって、高密度に実装さ
れる。又、ＱＦＰ （４方向フラツトパツケージＩＣ）
で代表される電子部品のリード端子も多端子で狭ピッチ
化されてくるので、益々これらリード端子の半田付けが
難しくなってきており、半田付は不良の起りにくい信頼
性の高い実装方法が要求されてきた。2. Description of the Related Art In recent years, IC packages and other electronic components have been packaged with high density as electronic devices have become smaller and lighter and more sophisticated. Also, QFP (4-way flat package IC)
As the lead terminals of electronic components, such as those represented by It has been.
以下、図面に従い一般的なＩＣパッケージの構造および
その実装方法について説明する。The structure of a general IC package and its mounting method will be described below with reference to the drawings.
第８図はＩＣパッケージ１の構造を示すもので、１１は
リードフレームで、主にＦｅ−Ｎｉアロイで構成されて
おり、このリードフレーム１１は回路基板とＩＣチップ
を電気的に接続する役目を果たしている。リードフレー
ムＩＩとＩＣチップ１２間は金やＣｕを主成分としたワ
イヤー１３で接続されている。又、ＩＣチップ１２はレ
ジン１４により覆われており、ＩＣチップ１２の表面や
ワイヤー１３の接続部を保護する作用を持っている。FIG. 8 shows the structure of the IC package 1. The lead frame 11 is mainly made of Fe-Ni alloy, and the lead frame 11 serves to electrically connect the circuit board and the IC chip. Fulfilling. The lead frame II and the IC chip 12 are connected by a wire 13 mainly made of gold or Cu. Further, the IC chip 12 is covered with a resin 14, which has the effect of protecting the surface of the IC chip 12 and the connection portion of the wire 13.
このようなＩＣパッケージは、第７図に示すようにあら
かじめ用意された回路基板１５の電極１６上に半田１７
により電気的に接合され実装される。実装方法の例を示
すと、先ず回路基板１５の電極１７に合わせてエツチン
グされたステンレス製のスクリーンを用いてクリーム半
田１７を印刷する。ここで使用されるステンレススクリ
ーンの厚さは１００μｍ〜３００μｍ程度であって、印
刷するクリーム半田の厚みにより使い分けられている。Such an IC package is manufactured by applying solder 17 on electrodes 16 of a circuit board 15 prepared in advance, as shown in FIG.
electrically connected and mounted. To give an example of the mounting method, first, cream solder 17 is printed using a stainless steel screen etched to match the electrodes 17 of the circuit board 15. The thickness of the stainless steel screen used here is approximately 100 μm to 300 μm, and is used depending on the thickness of the cream solder to be printed.
ＩＣパッケージｌは自動装着機により位置決めされ、回
路基板上１５に塗布したクリーム半田１７上に装着され
る。この基板はその後リフロー装置により、約２５０℃
まで加熱され、クリーム半田中の半田が溶融し冷却する
ことによって再度固体化して電極とＩＣパッケージのリ
ード部が電気的に接合される。The IC package 1 is positioned by an automatic mounting machine and mounted on the cream solder 17 applied to the circuit board 15. This board is then heated to approximately 250°C using a reflow machine.
The solder in the cream solder melts and solidifies again as it cools, thereby electrically joining the electrodes and the leads of the IC package.
発明が解決しようとする課題
しかし上記のような一連の半田付は工程において、最も
起り易い不良は半田ブリッジであって、これは半田の表
面張力により溶融時に近接したリード間が短絡し、その
まま冷却固化してしまうものである。その原因としては
クリ、−ム半田の印刷不良、クリーム半田の塗布量が多
い場合ＩＣパッケージの装着ズレ等が挙げられ、特に近
年の高槻能のＩＣパッケージにおいては０．５ｍｍ以下
の狭ピッチのリードでとりわけ半田ブリッジの発生率が
高く大きな問題となる場合がある。第７図に示すように
ＩＣパッケージ１と電極＋７が少しづつ離れて行くリー
ド部１８の折曲部に半田のたまりが発生するためと考え
られる。Problems to be Solved by the Invention However, in the series of soldering processes described above, the most likely defect is solder bridging, which occurs when adjacent leads are shorted due to the surface tension of the solder, and when the solder is melted, it continues to cool. It solidifies. The causes include poor printing of cream solder, misalignment of the IC package when a large amount of cream solder is applied, etc. Especially in recent years, Noh Takatsuki's IC packages have leads with a narrow pitch of 0.5 mm or less. In particular, the occurrence rate of solder bridges is high and may become a major problem. This is believed to be because solder pools are generated at the bent portion of the lead portion 18 where the IC package 1 and the electrode +7 are gradually separated as shown in FIG.
本発明の目的は上記のような問題点を解消し、実装時に
半田のたまりが発生しないリード部を有するＩＣパッケ
ージを提供しようとするものである。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an IC package having a lead portion that does not cause solder pooling during mounting.
課題を解決するための手段
本発明は上記目的達成のため、ＩＣパッケージその他の
電子部品で狭ピッチで多数並列したリード部において、
折曲部を経て回路基板の電極へ半田付は可能とした端部
を除くリード部に、半田付は不可能で耐熱性の材料で作
られ且つリード部間を連結する形の半田障壁部を設けた
電子部品とした。Means for Solving the Problems In order to achieve the above-mentioned object, the present invention provides a method for achieving the above-mentioned purpose in the lead portions of IC packages and other electronic components arranged in large numbers in parallel at a narrow pitch.
A solder barrier section, which is made of a heat-resistant material that cannot be soldered, is provided on the lead section, except for the end section, which can be soldered to the electrode of the circuit board through the bent section, and which connects the lead sections. The electronic components were installed.
作用
上記のようにＩＣパッケージのリード部には半田付けが
行なえない耐熱性の材料で作られた半田障壁部が設けら
れ、リード間を連結する形に形成されている。従ってク
リーム半田やデイツプ槽によるリード部の半田付けの際
、折曲部への半田たまりが防止できるようになった。ま
たリード間を連結する形で形成された半田障壁部はリー
ド部の外部応力による変形を防止してリード部を補強す
る作用があり、リード部間ピッチ０．５ｍｍ以下のリー
ド幅のＱＦＰでは特に有効な補強材の役目を果たしてい
る。Function As described above, the lead portion of the IC package is provided with a solder barrier portion made of a heat-resistant material that cannot be soldered, and is formed to connect the leads. Therefore, when soldering the lead portion using cream solder or a dip bath, it is now possible to prevent solder from accumulating on the bent portion. In addition, the solder barrier part formed to connect the leads has the effect of preventing deformation of the lead part due to external stress and reinforcing the lead part, especially in QFP with a lead width of 0.5 mm or less between lead parts. It plays the role of an effective reinforcing material.
実施例
以下、本発明の一実施例であるＩＣパッケージを図面に
基いて説明する。EXAMPLE Hereinafter, an IC package which is an example of the present invention will be explained based on the drawings.
第１図はＩＣパッケージ本体のリード部間の折曲部に半
田障壁部を設けたもので、ｌはＩＣパッケージ本体、２
はリード部で、折曲部３を経て回路基板の電極へ端部が
電気的に接続されるようになっている。４は半田障壁部
で、半田不可能で且つ耐熱性のある材料で、前記リード
部間を連結する形で設けられている。In Figure 1, a solder barrier is provided at the bend between the leads of the IC package body, where 1 is the IC package body, and 2 is the IC package body.
is a lead portion whose end portion is electrically connected to the electrode of the circuit board through the bent portion 3. A solder barrier section 4 is made of a non-solderable and heat-resistant material and is provided to connect the lead sections.
また、第２図はＩＣパッケージ本体から折曲部にかけて
半田障壁部５を設けた場合である。いづれの方法におい
てもリード部２間を連結する形で半田障壁部４．５を形
成している。リード部２の端部で回路基板６側の電極７
との接合部８には半田障壁部を形成していない。Further, FIG. 2 shows a case where a solder barrier portion 5 is provided from the IC package body to the bent portion. In either method, a solder barrier portion 4.5 is formed to connect the lead portions 2. Electrode 7 on the circuit board 6 side at the end of lead part 2
No solder barrier portion is formed at the joint portion 8 with.
第３図から第５図は半田障壁部を有するＩＣパッケージ
の断面図で、第３図は半田障壁部４をリード部２の内面
に形成したもの、第４図はリード部２の外壁に半田障壁
部９を形成したものである。また、第５図はリード部２
の内面および外面に半田障壁部４．９を設けた複合型で
ある。3 to 5 are cross-sectional views of IC packages having solder barrier portions. FIG. 3 shows the solder barrier portion 4 formed on the inner surface of the lead portion 2, and FIG. 4 shows the solder barrier portion 4 formed on the inner surface of the lead portion 2. A barrier portion 9 is formed therein. In addition, FIG. 5 shows the lead part 2.
This is a composite type in which solder barrier portions 4.9 are provided on the inner and outer surfaces of the solder barrier section 4.9.
第６図はＩＣパッケージ本体１の部分と半田障壁部１０
とを一体に形成した例である。上記半田障壁部４．５．
９．１０はＩＣパッケージ本体ｌのパッケージ材質と同
等のエポキシ樹脂やテフロン樹脂を用いＩＣパッケージ
本体ｌの封止成形を行なう行程と同時に行なうことがで
きる。この場合封止モールド用金型と半田障壁部用金型
は兼用とし、ＩＣパッケージはリード部を所定位置にフ
ォ−ミンクし、半田障壁部を同時にフォーミングするよ
うにすればよい。Figure 6 shows the IC package main body 1 and the solder barrier section 10.
This is an example in which the two are integrally formed. Above solder barrier section 4.5.
Step 9.10 can be performed simultaneously with the step of sealing and molding the IC package body 1 using an epoxy resin or Teflon resin that is the same as the package material of the IC package body 1. In this case, the mold for the sealing mold and the mold for the solder barrier portion may be used together, and the IC package may be formed so that the lead portion is formed in a predetermined position and the solder barrier portion is formed at the same time.
発明の効果
本発明は上記のようにＩＣパッケージその他の電子部品
のリード部において、半田付は可能なリード部の端部を
除いて、これらリード部間を連結するように半田付は不
可能で且つ耐熱性のある材料で半田障壁部を設けたこと
により狭ピッチの多数のリード部間に半田たまりが生じ
るのを防止され、特に０．５ｍｍ以下の狭ピッチのリー
ド部においても半田ブリッジの発生率を大幅に低減する
ことができ、外部応力によるリード部の変形を防止でき
密度が高く高精度な実装が可能な電子部品を提供できる
ようになった。Effects of the Invention As described above, the present invention provides a method for connecting the lead parts of IC packages and other electronic components, except for the ends of the lead parts, which can be soldered, so that soldering is not possible. In addition, by providing the solder barrier part with a heat-resistant material, it is possible to prevent solder pools from forming between the many lead parts with a narrow pitch, and in particular, the occurrence of solder bridges even in the lead parts with a narrow pitch of 0.5 mm or less. It has become possible to provide electronic components that can be mounted with high density and high precision, and can prevent deformation of the lead portion due to external stress.
第１図は本発明の一実施例を示すＩＣパッケージの斜視
図、第２図は同地実施例を示す斜視図、第３図は第１図
のＩＣパッケージの要部断面図、第４図、第５図、第６
図はそれぞれ他実施例を示す要部断面図、第７図はＩＣ
パッケージの実装状態を示す要部断面図、第８図はＩＣ
パッケージの構成を示す一部切欠き斜視図である。
２・・・リード部 ３・・・折曲部
４．５．９、ｌＯ・・・半田障壁部
用願人 松下電器産業株式会社Fig. 1 is a perspective view of an IC package showing an embodiment of the present invention, Fig. 2 is a perspective view showing an embodiment of the present invention, Fig. 3 is a sectional view of a main part of the IC package shown in Fig. , Figure 5, Figure 6
The figures are sectional views of main parts showing other embodiments, and Figure 7 is an IC.
A cross-sectional view of the main parts showing the mounting state of the package, Figure 8 is the IC
FIG. 2 is a partially cutaway perspective view showing the configuration of the package. 2... Lead part 3... Bent part 4.5.9, lO... Solder barrier part Applicant Matsushita Electric Industrial Co., Ltd.
Claims (1)
列したリード部において、折曲部を経て回路基板の電極
へ半田付け可能とした端部を除くリード部に、半田付け
不可能で耐熱性の材料で作られ且つリード部間を連結す
る形の半田障壁部を設けたことを特徴とする電子部品。In IC packages and other electronic components, where a large number of leads are arranged in parallel at a narrow pitch, non-solderable, heat-resistant materials are used for the lead parts, excluding the ends that can be soldered to the circuit board electrodes through the bent parts. What is claimed is: 1. An electronic component characterized in that a solder barrier section is formed to connect lead sections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP513490A JP3048236B2 (en) | 1990-01-11 | 1990-01-11 | Electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP513490A JP3048236B2 (en) | 1990-01-11 | 1990-01-11 | Electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03209753A true JPH03209753A (en) | 1991-09-12 |
| JP3048236B2 JP3048236B2 (en) | 2000-06-05 |
Family
ID=11602841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP513490A Expired - Fee Related JP3048236B2 (en) | 1990-01-11 | 1990-01-11 | Electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3048236B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632682A1 (en) * | 1993-06-28 | 1995-01-04 | International Business Machines Corporation | Compliant lead for surface mounting a chip package to a substrate |
| JP2010080574A (en) * | 2008-09-25 | 2010-04-08 | Koyo Electronics Ind Co Ltd | Joining structure and joining method of bus bar |
-
1990
- 1990-01-11 JP JP513490A patent/JP3048236B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632682A1 (en) * | 1993-06-28 | 1995-01-04 | International Business Machines Corporation | Compliant lead for surface mounting a chip package to a substrate |
| JPH0722570A (en) * | 1993-06-28 | 1995-01-24 | Internatl Business Mach Corp <Ibm> | Elastic lead for electrical and mechanical connection of integrated circuit chip package to substrate surface and preparation thereof |
| JP2010080574A (en) * | 2008-09-25 | 2010-04-08 | Koyo Electronics Ind Co Ltd | Joining structure and joining method of bus bar |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3048236B2 (en) | 2000-06-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |