JPH03207082A - Memory access system - Google Patents

Abstract

PURPOSE:To secure the decode time of access, to prevent erroneous access from being generated and to perform access at the highest speed by providing a delay circuit to delay an address determine signal to be outputted from a CPU. CONSTITUTION:A delay circuit 4 is provided to delay an address determine signal AS6 to be outputted from the CPU. When the delay time of the circuit 4 is defined as D1, the delay time of a decoder 5 is defined as D2 and time from the determination of an address 7 to the assertion by the AS6 is defined as T, under the condition of T<D2, the D1 becomes the optimum value in the case of D1=D2-T. For this value, under the condition of D1=Da, there is the danger of erroneous access generation in the case of D1<Da and under the condition of D1>Da, the time of D1-Da is made useless. Thus, since the delay time D1 is set at the optimum value, the decode time of the address is secured and the access is performed to the memory at the highest speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method for dynamic RAM of a microprocessor.

[Conventional technology]

, When using dynamic RAM (DRAM) as an external storage element of a microprocessor (CPtJ),
Since DRAM requires refreshing, a refresh arbiter is used to arbitrate between the CPU's access request and a refresh request, and a timing generator is used to output the row address strobe signal (RAS), as shown in Figure 2.
) is generally used.

In Figure 2, CPLlREQ14 is the D
An access request to the RAM, REFREQ8, is an access request from the refresh circuit, and is arbitrated by the refresh arbiter 1. Timing generator 2 is C
Creates RAS9 and column address strobe signal (CAS) to be given to DRAM by access from PU. Timing 3 Generator 1 controls RASIO during refresh, RAS9 and 10 are outputted via OR circuit 11. DRAM is refreshed using RAS-only refresh. Figure 3 shows a block diagram of a conventional example of the memory access method whose concept is shown in Figure 2. [Problems to be Solved by the Invention] The conventional memory access method described above has no problems when the access speed of CPtJ is slow, but it
Used with a clock of MHz or higher, access speed 50
When driving a DRAM at the maximum speed of ~100 nS, the time from when the address 7 output from the CPU becomes stable until the address confirmation signal (AS) 6 is asserted is very short, and the decoder 5 AS6 asserts before the address decode output is confirmed,
There is a risk that an erroneous DARM access request may occur.

For example, when a 32-bit CPU MC68020 (Motorola) is used at 20 MHz with no wait, the minimum time from address confirmation to AS assertion is 10 nS, and the decoding of address 7 must be completed during this time.

[Means to solve the problem]

The memory access method of the present invention uses a dynamic RAM that requires refreshing as an external storage element, and handles access requests from the CPU that occur from time to time as a logical combination of an address decode result obtained by decoding an address output by the CPU and an address confirmation signal. The memory access method uses a refresh arbiter to arbitrate the refresh request, and includes a delay circuit that delays the address determination signal output from the CPU.

The delay time of the delay circuit may be set so that the address confirmation signal is input to the refresh arbiter earliest, not earlier than the address decoding result. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. This embodiment is modified from the conventional example shown in FIG. 3 by adding a delay circuit 4 that delays AS6. Delay time of delay circuit 4 is DI, delay time of decoder 5 is D2, address 7
Let T be the time from when AS6 is asserted to when AS6 is asserted, and let T(D2 be the optimum value of D1.If D1=D2-T is the optimal value for D1.If this value is D1=Da, then Di<D
If DI>Da, the time for Di-Da is wasted (wasted). In reality, it should be set with some leeway. In Figure 4, Di
> Da is shown in the timing diagram. The access request l2 in FIG. 4 is the waveform of the access request from the CPU as the refresh arbiter 1 output. The waveform of the corresponding access request 13 in the conventional example of FIG. 3 is also shown in FIG. 4. The value of the hatched portion of the output of the decoder 5 is not guaranteed because AS6 is asserted before the output of the decoder 5 is determined.

〔Effect of the invention〕

As described above, according to the memory access method of the present invention,
Because the CPU is using a high-speed clock, the CPU
After the address output by is stable, the address confirmation signal (
AS) is asserted for a very short time, and even if the AS output is asserted before the address decode output is determined, the address decode time can be secured to prevent erroneous accesses from occurring. , by setting the delay time of the AS signal to an optimal value, it is possible to realize the fastest access to the memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a conceptual diagram of a general memory access method, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a block diagram of the embodiment shown in FIG. 4 is a timing diagram of the conventional example shown in FIG. 3. FIG. DESCRIPTION OF SYMBOLS 1... Refresh arbiter, 2, 3... Timing generator, 4... Delay circuit, 5... Decoder, 1 1... OR circuit.

Claims (2)

[Claims] (1) A dynamic RAM that requires refreshing is used as an external storage element, and the CPU's access request and the refresh request are generated at any time as a logical product of the address decoding result obtained by decoding the address output by the CPU and the address confirmation signal. What is claimed is: 1. A memory access method in which a refresh arbiter arbitrates the address determination signal, the method comprising: a delay circuit for delaying the address determination signal output from the CPU. (2) The memory access method according to claim 1, wherein the delay time of the delay circuit is set so that the address confirmation signal is inputted to the refresh arbiter earliest, not earlier than the address decoding result.