JPH0320450U - - Google Patents
Info
- Publication number
- JPH0320450U JPH0320450U JP8079189U JP8079189U JPH0320450U JP H0320450 U JPH0320450 U JP H0320450U JP 8079189 U JP8079189 U JP 8079189U JP 8079189 U JP8079189 U JP 8079189U JP H0320450 U JPH0320450 U JP H0320450U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- ground pattern
- chip mounting
- insulating substrate
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示す概念構成図、
第２図はチツプキヤリアの具体例を構成説明図、
第３図は第１図の具体例を示す構成説明図、第４
図は従来のＩＣチツプ実装の一例を示す構成説明
図である。
１……絶縁基板、２，３，１０，１２……グラ
ウンドパターン、５……ＩＣチツプ、７……ボン
デイングワイヤ、８……チツプキヤリア、９……
誘電体基板、１３……配線パターン。
FIG. 1 is a conceptual configuration diagram showing an embodiment of the present invention.
Figure 2 is a configuration explanatory diagram of a specific example of Chippukiyaria.
Figure 3 is a configuration explanatory diagram showing a specific example of Figure 1;
The figure is a configuration explanatory diagram showing an example of conventional IC chip mounting. 1... Insulating substrate, 2, 3, 10, 12... Ground pattern, 5... IC chip, 7... Bonding wire, 8... Chip carrier, 9...
Dielectric substrate, 13... wiring pattern.
Claims (1)
実装構造において、 前記絶縁基板とＩＣチツプの間に、 誘電体基板の一方の面に第１のグラウンドパタ
ーンが形成され、他方の面のＩＣチツプの実装領
域には第１のグラウンドパターンと電気的に接続
された第２のグラウンドパターンが形成されると
ともに第２のグラウンドパターンの周辺部に位置
するように電源パターンを含む複数のパターンが
離散的に形成されたチツプキヤリアを介在させる
ことを特徴とするＩＣチツプ実装構造。[Claims for Utility Model Registration] In an IC chip mounting structure in which an IC chip is mounted on an insulating substrate, a first ground pattern is formed on one surface of a dielectric substrate between the insulating substrate and the IC chip, A second ground pattern electrically connected to the first ground pattern is formed in the IC chip mounting area on the other surface, and includes a power pattern located around the second ground pattern. An IC chip mounting structure characterized by interposing a chip carrier in which a plurality of patterns are discretely formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8079189U JPH0320450U (en) | 1989-07-11 | 1989-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8079189U JPH0320450U (en) | 1989-07-11 | 1989-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320450U true JPH0320450U (en) | 1991-02-28 |
Family
ID=31626155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8079189U Pending JPH0320450U (en) | 1989-07-11 | 1989-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320450U (en) |
-
1989
- 1989-07-11 JP JP8079189U patent/JPH0320450U/ja active Pending