JPH03201554A - Electronic part to be packaged on board - Google Patents

Electronic part to be packaged on board

Info

Publication number
JPH03201554A
JPH03201554A JP34210789A JP34210789A JPH03201554A JP H03201554 A JPH03201554 A JP H03201554A JP 34210789 A JP34210789 A JP 34210789A JP 34210789 A JP34210789 A JP 34210789A JP H03201554 A JPH03201554 A JP H03201554A
Authority
JP
Japan
Prior art keywords
lead
electronic component
board
shape memory
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34210789A
Other languages
Japanese (ja)
Inventor
Yoshikazu Kawai
良和 川合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzuki Motor Corp
Original Assignee
Suzuki Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzuki Motor Corp filed Critical Suzuki Motor Corp
Priority to JP34210789A priority Critical patent/JPH03201554A/en
Publication of JPH03201554A publication Critical patent/JPH03201554A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To approximately securely prevent a lead from floating at the time of joint by a method wherein each lead is subjected to thermoelastic martensitic transformation exhibiting a shape memory effect at a temperature higher than room temperature and lower than soldering temperature as well as is formed of shape memory alloy having conductivity. CONSTITUTION:Each lead 3 of a flat package IC 3 is mounted on soldering paste 54 adhered on a pad 53 on a board 51. Even if a lead 32 is deformed and floated upward, the lead which is deformed at the time of heating wherein the lead is passed through a re-flow furnace as a heating means reaches a temperature of martensitic transformation or higher and is restored to an original state before the deformation by a shape memory effect so that contact faces 3b of all leads 3a are positioned on the same plane. At the same time the soldering paste 54 is melted, all the leads 3 are uniformly soldered and after the lead is passed through the re-flow furnace it is cooled to have the solder solidified so that the pad 53 and the lead 3 are electrically (and mechanically) connected to each other.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は基板実装用の電子部品に係り、更に詳しくはセ
ラミック、有機材料等の絶縁性材料からなる印刷配線基
板上の導体形成面に半田付は等により実装される基板実
装用の電子部品に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an electronic component for mounting on a board, and more specifically, the present invention relates to an electronic component for mounting on a board, and more specifically, to solder on a conductor-forming surface of a printed wiring board made of an insulating material such as a ceramic or an organic material. The appendix relates to electronic components for board mounting that are mounted by et al.

〔背景技術〕[Background technology]

近年、民生用機器は小型、薄型、軽量化の趨勢にあり、
゛電子部品に対する小型化と自動組立の要求が強まって
きている。かかる状況のもと、フラットパッケージIC
等の電子部品の印刷配線基板への実装も殆どの場合、自
動組立の一環として行われている。
In recent years, consumer devices have become smaller, thinner, and lighter.
``Requirements for miniaturization and automatic assembly of electronic components are increasing. Under such circumstances, flat package IC
In most cases, electronic components such as electronic components are mounted on printed wiring boards as part of automatic assembly.

従来のフラットパッケージIC等の印刷配線基板への実
装工程は、次のようにして行われている。
The process of mounting a conventional flat package IC or the like onto a printed wiring board is performed as follows.

すなわち、第5図に示すように、セラミック。That is, as shown in FIG. 5, ceramic.

有機材料等の絶縁性材料からなる印刷配線基板51の表
面に予め形成された数本の導体パターン52.52.・
・・・・・の先端に半田パッド〔以下、「バッド」とい
う)53.53・・・・・・が形成され、当1亥各バッ
ド53上に半田ペースト54が付着されている。この第
5図においては、導体パターン52が10本設けられ、
各導体パターン52の先端部にパッド53がそれぞれ形
威されている状態が示されている。
Several conductor patterns 52.52. are formed in advance on the surface of the printed wiring board 51 made of an insulating material such as an organic material.・
Solder pads (hereinafter referred to as ``pads'') 53, 53, . In this FIG. 5, ten conductor patterns 52 are provided,
A pad 53 is shown at the tip of each conductive pattern 52, respectively.

そして、パッド53に対応して10本、具体的には二方
向に導出された各5本の外部端子(以下、「リード」と
いう)41..41□、・・・・・・、411゜を備え
たフラットパッケージIC等の電子部品40を、各リー
ド41が各パッド53上に一致するよう位置決めして載
置し、この状態で加熱手段(図示せず)により半田をリ
フロー(再溶融)させ、冷却凝固せしめて接合、導通せ
しめることがなされていた。
Then, there are ten external terminals (hereinafter referred to as "leads") 41 corresponding to the pads 53, specifically five external terminals (hereinafter referred to as "leads") led out in two directions. .. An electronic component 40 such as a flat package IC having an angle of 41□, . (not shown), the solder is reflowed (remelted), cooled and solidified to achieve bonding and conduction.

しかしながら、かかる方法によると、第5図に示すリー
ド4hのように変形により浮き上がったリードがあると
、第6図に示すように浮き上がったまま旨く接合されな
いことがあるが、半田付は不良の検査は難しいため、後
々問題を引き起こしていた。
However, according to this method, if there is a lead that has been lifted up due to deformation, such as lead 4h shown in FIG. 5, the lead may remain lifted and not be properly joined as shown in FIG. was difficult and caused problems later on.

かかる問題点を解決するため、以下に示す幾つかの提案
がなされている。
In order to solve these problems, several proposals have been made as shown below.

■電子部品の各リードの先端以外の部分に切欠等を設け
て応力集中を起こす箇所を予め形威し、該各リードの先
端を基板に対して鋭角に対向せしめ、当該電子部品を半
田パッド上にiS!置した後、該電子部品の本体の部分
を基板に向けて押圧し、前記応力集中箇所に塑性変形を
生ぜしめてリードの先端部を半田パッドに当接せしめて
半田をリフローする手法。例えば、特開昭59−178
790号等がある。
■Preliminary shaping of stress concentration points by providing notches, etc. in parts other than the tip of each lead of the electronic component, making the tip of each lead face the board at an acute angle, and placing the electronic component on the solder pad. iS! After placing the electronic component on the board, the main body of the electronic component is pressed toward the board, causing plastic deformation at the stress concentration area and bringing the tip of the lead into contact with the solder pad, thereby reflowing the solder. For example, JP-A-59-178
There are issues such as No. 790.

■基板の導体パターン上に半田ペースト等を介して載置
された電子部品のリード上に、全てのリードに当接可能
に形成された枠型の硝子とこの硝子の外縁部上に固着さ
れた磁性体とから成る特殊の押さえ工具を載置し、基板
下に配置された磁石で前記磁性体を吸引することにより
リードを導体パターン上に当接せしめ、リードの接続部
を透視しながら放射エネルギービーム(YAGレーザ等
)をガラス等を介して照射し、半田等を溶融する手法。
■A frame-shaped glass is formed on the leads of electronic components placed on the conductor pattern of the board via solder paste etc. so that it can come into contact with all the leads, and a frame-shaped glass is fixed on the outer edge of this glass. A special holding tool made of a magnetic material is placed on the board, and a magnet placed under the board attracts the magnetic material to bring the leads into contact with the conductor pattern, and the radiant energy is applied while looking through the connection parts of the leads. A method of irradiating a beam (YAG laser, etc.) through glass, etc. to melt solder, etc.

例えば、特開昭59−217388号等がある。For example, there is Japanese Patent Application Laid-Open No. 59-217388.

■電子部品のリードの先端部を半田ペースト内に埋め込
み可能な形状に形威し、該先端部を所定速度で半田ペー
スト内に埋め込ませた後、半田をリフローさせる手法。
■A method in which the tip of an electronic component lead is shaped into a shape that can be embedded in solder paste, the tip is embedded in the solder paste at a predetermined speed, and then the solder is reflowed.

例えば、特開昭60−60795号等がある。For example, there is Japanese Patent Application Laid-Open No. 60-60795.

■電子部品の上部から力を加え、該電子部品の全てのリ
ードが基板上のパッドに密着した状態を維持しながら半
田付けする手法。例えば、特開昭62−37992号等
がある。
■A method in which force is applied from above the electronic component and all leads of the electronic component are soldered while maintaining close contact with the pads on the board. For example, there is Japanese Patent Application Laid-Open No. 62-37992.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記従来例の■、■に示すものにあって
は、次のような不都合があった。すなわち、通常フラッ
トパッケージIC等の電子部品40は、第7図に示すよ
うに、半導体素子30をエポキシやシリコン等の合成樹
脂31でモールドし二方向(或いは四方向)にリード4
1を引き出し、半導体素子30と各リード間をボンディ
ングワイヤ42で接続して構成されている。このため、
力Fにより生じる押圧時の機械的ストレスは、ボンディ
ングワイヤ42の断線や半導体素子30のクラック発生
の要因となり、ひいては信頼性の低下を招く原因となっ
ていた。
However, the conventional examples shown in (1) and (3) have the following disadvantages. That is, as shown in FIG. 7, an electronic component 40 such as a flat package IC usually has a semiconductor element 30 molded with a synthetic resin 31 such as epoxy or silicone, and leads 4 in two directions (or four directions).
1 is drawn out, and the semiconductor element 30 and each lead are connected with bonding wires 42. For this reason,
The mechanical stress generated by the force F during pressing causes breakage of the bonding wire 42 and cracks in the semiconductor element 30, which in turn causes a decrease in reliability.

また、上記従来例の■に示すものにあっては、上述した
ような特殊の押さえ工具を必要とするとともに、放射エ
ネルギービーム部品実装以外の手法には不向きであると
いう本質的欠点を有している。
In addition, the conventional example shown in (■) above requires a special holding tool as described above, and has the essential drawback that it is unsuitable for methods other than radiant energy beam component mounting. There is.

一方、上記従来例の■の手法にあっては、押圧時の機械
的ストレスによる信頼性の低下は防止できると考えられ
るが、リード41の変形が大きい場合、加熱して半田ペ
ースト54を溶融しても、第8図に示すように、変形し
たリード41は基板51上の導体パターン52に半田付
けされず、この手法によっても接合不良を完全には防止
できないという不都合があった。
On the other hand, in the method (2) of the conventional example above, it is thought that a decrease in reliability due to mechanical stress during pressing can be prevented, but if the deformation of the lead 41 is large, the solder paste 54 may be melted by heating. However, as shown in FIG. 8, the deformed leads 41 are not soldered to the conductor pattern 52 on the substrate 51, and even this method has the disadvantage that poor bonding cannot be completely prevented.

ところで、上述したような電子部品のリードの変形は製
造時に幾ら精密に製造しても、輸送時及び途中での取扱
いにより生じるものであるため完全には防止できないと
考えられる。
Incidentally, no matter how precisely the lead of the electronic component is manufactured, the deformation of the lead of the electronic component as described above cannot be completely prevented because it occurs during transportation and handling during transportation.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、かかる従来例の有する不都合を改善し
、とくに、実装時の機械的ストレスに起因する信頼性の
低下を防止し得るとともに、半田付は方法を限定される
ことなく接合時のリードの浮き上がりを略確実に防止す
ることが可能な基板実装用の電子部品を提供することに
ある。
An object of the present invention is to improve the disadvantages of the conventional example, and in particular, to prevent a decrease in reliability due to mechanical stress during mounting, and to solve the problem of soldering during bonding without limiting the method of soldering. It is an object of the present invention to provide an electronic component for mounting on a board, which can substantially reliably prevent lifting of leads.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、半導体素子を合成樹脂でモールドしてなる電
子部品本体と、この電子部品本体から外部に向かって少
なくとも二方向に導出された少なくとも4本の外部端子
とを有し、セラミック、有機材料等の絶縁性材料からな
る配線基板上に実装される基板実装用の電子部品におい
て、各リードを、常温より高く且つ半田付は温度より低
い温度において形状記憶効果を示す熱弾性型マルテンサ
イト変態を起こすとともに、導電性を有する形状記憶合
金により形成し、当該各リードの変形前の形状を、該各
リードの先端に予め設けられた配線基板上の導体部との
当接面が相互にほぼ同一平面上に位置する形状とすると
いう構成を採っている。
The present invention has an electronic component body formed by molding a semiconductor element with a synthetic resin, and at least four external terminals led out in at least two directions from the electronic component body, and is made of ceramic, organic material, etc. In electronic components for board mounting mounted on wiring boards made of insulating materials such as The shape of each lead before deformation is made of a conductive shape memory alloy, and the contact surface with the conductor portion on the wiring board provided in advance at the tip of each lead is approximately the same. The configuration is such that the shape is located on a plane.

これによって、前述した目的を達成しようとするもので
ある。
This aims to achieve the above-mentioned purpose.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図ないし第4図に基づい
て説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

第1図には本発明に係る電子部品としてのフラットパッ
ケージICIと、このフラットパッケージIC1が実装
される基板51とが示されている。
FIG. 1 shows a flat package ICI as an electronic component according to the present invention and a substrate 51 on which this flat package IC1 is mounted.

フラットパッケージICIは、電子部品本体としてのパ
ッケージIC本体2と、このパッケージIC本体2から
外部に向かって二方向に導出されたリード31.3□、
・・・・・・、3、。とを有している。
The flat package ICI includes a package IC main body 2 as an electronic component main body, leads 31.3□ led out in two directions from the package IC main body 2 toward the outside,
......3. It has

この内、パッケージIC本体2は、前述した従来例の電
子部品40と同様に、半導体素子(ここでは図示せず)
と、この半導体素子をモールドする合成樹脂モールド2
Aと、半導体素子と各リード3を電気的に接続するボン
ディングワイヤ(ここでは図示せず)とを備えて構成さ
れている。
Of these, the package IC body 2 includes a semiconductor element (not shown here), similar to the electronic component 40 of the conventional example described above.
and a synthetic resin mold 2 for molding this semiconductor element.
A, and bonding wires (not shown here) that electrically connect the semiconductor element and each lead 3.

前記各リード3は、常温より高く且つ半田付は温度より
低い温度において形状記憶効果を示す熱弾性型マルテン
サイト変態を起こす導電性の形状記憶合金により形成さ
れている。また、これらの各リード3は、断面Z字状に
形成され、その一端が合成樹脂モールド2A内に埋め込
まれるとともに、その他端に配線基板51上の導体部と
しての導体パターン52の先端に形成されたバッド53
に当接する当接部3Aが形成されている。そして、各当
接部3Aの下面が導体部との当接面3bになっている。
Each lead 3 is formed of a conductive shape memory alloy that undergoes thermoelastic martensitic transformation exhibiting a shape memory effect at a temperature higher than room temperature and lower than soldering temperature. Further, each of these leads 3 is formed to have a Z-shaped cross section, and one end thereof is embedded in the synthetic resin mold 2A, and the other end is formed at the tip of a conductive pattern 52 as a conductor portion on the wiring board 51. Bad 53
A contact portion 3A that comes into contact with is formed. The lower surface of each contact portion 3A serves as a contact surface 3b with the conductor portion.

そして、変形前の元の形状は、第2図に示すように、全
ての当接面3bが、相互にほぼ同一平面上に位置するよ
うな形状に形成されている。この第2図において、符号
10は仮想平面を示す。
As shown in FIG. 2, the original shape before deformation is such that all the contact surfaces 3b are located on substantially the same plane. In this FIG. 2, reference numeral 10 indicates a virtual plane.

一方、基板51は、セラミック、有機材料等の絶縁性材
料からなり、その第1図における上面には10本の導体
パターン52が形成されている。
On the other hand, the substrate 51 is made of an insulating material such as ceramic or organic material, and has ten conductor patterns 52 formed on its upper surface in FIG.

この導体パターン52のそれぞれの一端には、パッド5
3が形成され、この上に半田ペースト54が付着されて
いる。
A pad 5 is provided at one end of each of the conductive patterns 52.
3 is formed, and a solder paste 54 is adhered thereon.

次に本実施例に係るフラットパッケージICIを基板5
1に実装する場合の作用等について説明する。
Next, the flat package ICI according to this embodiment is attached to the substrate 5.
The effects etc. when implemented in 1 will be explained.

まず、フラットパッケージICIの各リード3を基板5
1上のバッド53上に付着されたハンダペースト54上
に載置する。この状態を第3図に示す。この第3図に示
すように、リード3□が変形して、前述した第5図に示
すリード41t と同様に、上方に浮き上がっている状
態であっても、加熱手段としてのりフロー炉(図示せず
)を通過させて加熱する際に当該変形したり−ド4.は
、マルテンサイト変態温度以上に達し形状記憶効果によ
り変形前の元の状態に戻るので(第4図参照)、全ての
り一ド3の当接面3bが同一平面上に位置することとな
る。これと同時に、ハンダペースト54も溶融され、全
リード3が均一に半田付けされ、リフロー炉通過後、冷
却されて半田は固化しパッド53とリード3は電気的(
及び機械的)に接続される。
First, connect each lead 3 of the flat package ICI to the board 5.
It is placed on the solder paste 54 that is adhered to the pad 53 on the top of the solder paste 54. This state is shown in FIG. As shown in FIG. 3, even if the lead 3□ is deformed and floating upwards, similar to the lead 41t shown in FIG. 4. The deformation occurs when the material is passed through and heated. reaches the martensitic transformation temperature or higher and returns to its original state before deformation due to the shape memory effect (see FIG. 4), so that the abutment surfaces 3b of all the adhesives 3 are located on the same plane. At the same time, the solder paste 54 is also melted, and all the leads 3 are evenly soldered. After passing through a reflow oven, the solder is cooled and solidified, and the pads 53 and leads 3 are electrically (
and mechanically).

以上説明したように、本実施例によれば、リフロー炉を
通過する過程で各リード3が形状記憶効果により変形前
の形状に戻り全てのり一ド3の当接面3bが同一面上に
位置するため、フラットパッケージICIの何れのリー
ド3が変形していても、全てのり一ド3の当接面3bが
パッド53の表面と密着した状態で半田付けが行われる
ため、リードの浮き上がりに起因する半田付は不良や接
続不良をほぼ完全に防止できる。また、形状記憶合金の
形状記憶効果を利用するため、パッケージIC本体2を
基板方向に強く押圧する必要がないので、押圧時の機械
的ストレスに起因するボンディングワイヤの#fr線や
、半導体素子のクランクの発生を有効に防止することが
できる。
As explained above, according to this embodiment, each lead 3 returns to its pre-deformation shape due to the shape memory effect during the process of passing through the reflow oven, and the contact surfaces 3b of all the leads 3 are positioned on the same plane. Therefore, even if any of the leads 3 of the flat package ICI are deformed, soldering is performed with the contact surfaces 3b of all the adhesives 3 in close contact with the surface of the pad 53. Soldering can almost completely prevent defects and poor connections. In addition, since the shape memory effect of the shape memory alloy is utilized, there is no need to strongly press the package IC body 2 toward the substrate. The occurrence of crank can be effectively prevented.

なお、本発明に係る電子部品の実装の方法は、上述した
半田付けによるものに限定されるものではなく、例えば
いわゆる導電性接着材をハングペーストの代わりに用い
上記実施例と同様にリフローロを利用してリードとパッ
ドの電気的(及び機械的)接続を行うことも可能である
Note that the method of mounting electronic components according to the present invention is not limited to the above-mentioned method of soldering, but may also include, for example, using a so-called conductive adhesive instead of a hang paste and using reflow roller as in the above embodiment. It is also possible to make electrical (and mechanical) connections between the leads and the pads.

また、リフローロとしては、窒素ガス雰囲気炉。In addition, a nitrogen gas atmosphere furnace is used for reflow.

或いは窒素ガスの代わりに高温の空気を利用したもの等
が用いられる。更には、YAGレーザ或いはCO□レー
ザ等の放射エネルギービームによる基板への実装も可能
である。
Alternatively, a method using high temperature air may be used instead of nitrogen gas. Furthermore, mounting on the substrate using a radiant energy beam such as a YAG laser or a CO□ laser is also possible.

この他、電子部品をベース基板上に接着剤で仮止め後、
電子部品の搭載面を加熱溶融した半田槽内へ浸漬する半
田デイツプ法においても、接着材同化のための加熱工程
や加熱溶融半田槽内への浸漬工程時に変形したリードは
形状記憶効果により変形前の状態に戻るので、本発明は
容易に適用できる。このように、本発明では、半田等の
融点以上の温度に加熱できさえすれば良いので殆どの方
法に適用できるので、汎用性の広いものとなっている。
In addition, after temporarily fixing electronic components on the base board with adhesive,
Even in the solder dip method, in which the mounting surface of electronic components is immersed in a heated and molten solder bath, the leads that are deformed during the heating process to assimilate the adhesive or the immersion process in the heated and molten solder bath are not deformed due to the shape memory effect. The present invention can be easily applied. As described above, the present invention can be applied to most methods as long as it can be heated to a temperature higher than the melting point of solder, etc., and thus has wide versatility.

〔発明の効果) 以上説明したように、本発明によれば、各リードを、常
温より高く且つ半田付は温度より低い温度において形状
記憶効果を示す熱弾性型マルテンサイト変態を起こす導
電性の形状記憶合金により形成するとともに、当該各リ
ードの変形前の形状を、該各リードの先端に予め設けら
れた基板上の導体部との当接面が相互にほぼ同一平面上
に位置する形状としたことから、実装工程中の加熱時に
各リードが形状記憶効果により変形前の形状に戻って全
てのリードの当接面が同一面上に位置する状態となる。
[Effects of the Invention] As explained above, according to the present invention, each lead has a conductive shape that causes a thermoelastic martensitic transformation that exhibits a shape memory effect at a temperature higher than room temperature and lower than soldering temperature. In addition to being made of a memory alloy, the shape of each lead before deformation is such that the contact surfaces with the conductor portion on the substrate provided in advance at the tip of each lead are located on substantially the same plane. Therefore, during heating during the mounting process, each lead returns to its pre-deformation shape due to the shape memory effect, and the contact surfaces of all the leads are positioned on the same plane.

このため、全てのリードの当接面がバンドの表面と密着
した状態で半田付けが行われ、これによりリードの浮き
上がりに起因する半田付は不良や接続不良をほぼ完全に
防止でき、また、形状記憶効果を利用するため、電子部
品本体を基板方向に強く押圧する必要がないので、押圧
時の機械的ストレスに起因する信頼性の低下を防止する
ことができ、さらには、半田の融点以上に加熱できれば
良いので、あらゆる半田付けの方法が適用可能であると
いう従来にない汎用性に優れた基板実装用の電子部品を
提供することができる。
Therefore, soldering is performed with the contact surfaces of all the leads in close contact with the surface of the band, which almost completely prevents soldering defects and connection failures caused by lifting of the leads, and also improves the shape. Since the memory effect is used, there is no need to strongly press the electronic component body toward the board, so it is possible to prevent a decrease in reliability caused by mechanical stress during pressing. Since all that is required is heating, it is possible to provide an electronic component for board mounting that has unprecedented versatility and can be applied to any soldering method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係る電子部品とこれを実装
するための基板の実装前の状態を示す概略斜視図、第2
図は第1図の電子部品の変形前の形状を示す説明図、第
3図は第1図の電子部品の実装工程を示す説明図、第4
図は第1図の電子部品の実装工程中における作用説明図
、第5図ないし第8図は従来例を示す説明図である。 1・・・・・・電子部品としてのフラットパッケージI
C12・・・・・・電子部品本体としてのパッケージ本
体、2A・・・・・・合成樹脂モールド、3・・・・・
・リード、3b・・・・・・当接面、51・・・・・・
配線基板、52・・・・・・導体部としての導体パター
ン。
FIG. 1 is a schematic perspective view showing an electronic component according to an embodiment of the present invention and a board for mounting the electronic component before mounting, and FIG.
The figure is an explanatory diagram showing the shape of the electronic component in Figure 1 before deformation, Figure 3 is an explanatory diagram showing the mounting process of the electronic component in Figure 1, and Figure 4 is an explanatory diagram showing the shape of the electronic component before deformation.
The drawings are explanatory diagrams of operations during the mounting process of the electronic component shown in FIG. 1, and FIGS. 5 to 8 are explanatory diagrams showing conventional examples. 1...Flat package I as an electronic component
C12...Package body as electronic component body, 2A...Synthetic resin mold, 3...
・Lead, 3b...Contact surface, 51...
Wiring board, 52... Conductor pattern as a conductor part.

Claims (1)

【特許請求の範囲】[Claims] (1).半導体素子を合成樹脂でモールドしてなる電子
部品本体と、この電子部品本体から外部に向かって少な
くとも二方向に導出された少なくとも4本の外部端子と
を有し、セラミック、有機材料等の絶縁性材料からなる
配線基板上に実装される基板実装用の電子部品において
、 前記各外部端子を、常温より高く且つ半田付け温度より
低い温度において形状記憶効果を示す熱弾性型マルテン
サイト変態を起こすとともに、導電性を有する形状記憶
合金により形成し、当該各外部端子の変形前の形状を、
該各外部端子の先端に予め設けられた前記配線基板上の
導体部との当接面が相互にほぼ同一平面上に位置する形
状としたことを特徴とする基板実装用の電子部品。
(1). It has an electronic component body made of a semiconductor element molded with synthetic resin, and at least four external terminals led out in at least two directions from the electronic component body, and is made of an insulating material such as ceramic or organic material. In electronic components for board mounting mounted on a wiring board made of a material, each of the external terminals undergoes thermoelastic martensitic transformation exhibiting a shape memory effect at a temperature higher than room temperature and lower than the soldering temperature, and It is formed from a shape memory alloy that has conductivity, and the shape of each external terminal before deformation is
1. An electronic component for mounting on a board, characterized in that surfaces of the external terminals that come into contact with conductor portions on the wiring board provided in advance at the tips of the external terminals are shaped so that they are located on substantially the same plane.
JP34210789A 1989-12-28 1989-12-28 Electronic part to be packaged on board Pending JPH03201554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34210789A JPH03201554A (en) 1989-12-28 1989-12-28 Electronic part to be packaged on board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34210789A JPH03201554A (en) 1989-12-28 1989-12-28 Electronic part to be packaged on board

Publications (1)

Publication Number Publication Date
JPH03201554A true JPH03201554A (en) 1991-09-03

Family

ID=18351204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34210789A Pending JPH03201554A (en) 1989-12-28 1989-12-28 Electronic part to be packaged on board

Country Status (1)

Country Link
JP (1) JPH03201554A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0548584A3 (en) * 1991-12-24 1994-07-06 Minnesota Mining & Mfg Contact device for an electrical component and method for manufacture
US7776651B2 (en) 2003-03-31 2010-08-17 Intel Corporation Method for compensating for CTE mismatch using phase change lead-free super plastic solders

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0548584A3 (en) * 1991-12-24 1994-07-06 Minnesota Mining & Mfg Contact device for an electrical component and method for manufacture
US7776651B2 (en) 2003-03-31 2010-08-17 Intel Corporation Method for compensating for CTE mismatch using phase change lead-free super plastic solders

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