JPH03192598A - Shift circuit - Google Patents

Abstract

PURPOSE:To attain a high-speed shift operation independently of a shift bit number with small scale circuit constitution by specifically connecting (m) selectors having 2 set input terminals of (n) bits and (n+1) output terminals and selecting terminals. CONSTITUTION:The output terminal of a prestage selector is connected to the first input terminal of the succeeding stage selector, (m) selectors are respectively connected to a second input terminal so as to supply the signal shifted by 2<k-1> bit from an input digital signal to a first input terminal, each bit of (m) bit selective signal is supplied to each selective terminal of (m) selectors. Here 2<m=n, the first stage of K is 1. After all from the final stage selector 10m-1 the input digital signals D0-Dn-1 are bit shifted by bit number corresponding to the value of the binary number shown by (m) bit selective signals S0-Sm-1 and outputted. Consequently, the selectors are enough with the small number proportioned to an exponent (m).

Description

[Detailed Description of the Invention] [Summary] Regarding a shift circuit that shifts an input digital signal by an arbitrary number of bits and outputs it, the purpose is to perform a high-speed shift operation with a small-scale circuit configuration. In a shift circuit that shifts a signal by an arbitrary number of bits and outputs the signal, input signals of an n-pit first input terminal, an n-bit second input terminal, an n+1 output terminal, and the first and second input terminals are provided. m selectors (however, 2m≦n) are connected in cascade, and the output terminal of the previous selector is connected to the select terminal of the next selector. 1 input terminal, and each of the m selectors divides the input digital signal to the first input terminal into 2 to 1 bits (k is equal to the connection order of the selectors, and The output terminal of the previous stage selector and the second input terminal of the next stage selector are connected so as to supply the shifted digital signal (1 in the selector) to the second input terminal, and the m selectors The configuration is such that each bit of the m-bit select signal is supplied to each select terminal of.

[Industrial application field]

The present invention relates to a shift circuit, and particularly to a shift circuit that shifts an input digital signal by an arbitrary number of bits and outputs the shifted signal.

Shift circuits that shift a digital signal with an arbitrary bit width to an arbitrary bit width have been widely used in digital devices. It is necessary to be able to shift at high speed.

[Conventional technology]

FIG. 3 shows a circuit diagram of a conventional example. In the same figure, 1° to 1
Each has 70 D-type flips, and there are n pieces in total. 20 to 2o-1 are logic circuits, which are provided in one-to-one correspondence to the D-type flips 70 and the knobs 10 to 1. The logic circuits 20 to 2o-1 each have the same configuration, and each logic circuit 2. (However, i is 0 to n-1
) is the inverter 3 to which the select signal is input, the AND circuit 41 to which the output of the inverter 31 and the 1-bit data D of the input gage signal are input, and the select signal and the Q output signal of the D-type flip 70. It consists of an AND-1 circuit 51 to which is input, and an OR circuit 61 which takes the logical sum of the respective outputs of the AND circuits 41 and 51 and supplies the output to the data input terminal of the D-type flip 70. In addition, AN
Similar to the AND circuit 51, the D circuit 5o receives the select signal and the Q output signal of the D-type flip 70 tube 1o.

Next, the operation of the conventional circuit shown in FIG. 3 will be explained.

In the figure, each bit D o of the n-bit digital signal
"' D n-1 data is AND circuit 4°~4o-
1, and in this state, the select signal is set to a low level (hereinafter referred to as "L"). As a result, each data of D o "" D n-1 is AND
The voltage is applied to each data input terminal of the D-type flip-flop 70 through the circuits 40-4 and the OR circuits 60--16, respectively, and the D-type flip-flop 1° is applied at the time of input of the clock pulse. ~1
latched to.

-1 Next, the select signal is at a high level (hereinafter referred to as "H")
can be switched to As a result, AND circuits 50 to 5n-
1 is in the gate "open" state, and AND circuit 4
0 to 4o-1 enter the gate "leap" state, blocking the input data D o ''-D n-1 from passing through the OR circuits 60 to 6n-1. In this state, one clock pulse is input. Then, AND circuit 51+1 and OR circuit 61+
The Q output signal of the D-type flip 70, which is applied to the data input terminal of the D-type flip 70 through 1+1, respectively, is latched.

Therefore, by inputting one clock pulse,
Each output signal Oo~0n-1 taken out from the Q-1 output terminal of the D-type flip 70 tubes 10~1 converts the input digital data Do""Dn-1 into 1.
This is equivalent to bit-shifted n-bit digital data. Therefore, by inputting clock pulses corresponding to the number of bits to be shifted while the select signal is set to "H", output digital data O0 to On-1 shifted by the desired number of bits can be obtained.

Next, another example of the conventional shift circuit will be explained with reference to FIG. In Fig. 4, 8 is a selector with 2mxn inputs and n outputs, and an m-bit select signal S is used to select n-bit input terminals A o = A , B o ~-1 B , . . . , X o -X n-1 Input digital data to -1 The n-bit input digital data to any one of the input terminals is selectively output to the output terminals O0 to On-1.

Here, the n-bit input terminals Ao to An-1 of the selector 8
Input digital data DO to Dn-1 are respectively input to the next n-bit input terminals BO to Bn-1, and data Do is input to Bo and 81, respectively, in a form shifted by one bit, and to B2. Data D1 is input, and data D is input to Bn-2. -2, and in the same way, 2m=
If n is input, data Do is input, and data D is input to x, -1.
Connections are made to the input terminal group of the selector 8 so that 1 is input.

Therefore, according to this conventional circuit, the 2m (that is, n) n-bit input terminals receive digital data D o ''-On in a form that is sequentially shifted to the right one bit at a time.
Since -1 is input, the m-bit select signal S selects the n-bit input terminal from among the 2m n-bit input terminals into which the data shifted by the desired number of bits is input, thereby outputting the output of the selector 8. Terminal O0~On
-1 to input digital data D o ”” On-1
It is possible to extract digital data that has been shifted by a desired number of bits.

[Problem to be solved by the invention]

However, although the conventional shift circuit shown in FIG. 3 does not have a large amount of circuitry, it is necessary to input clock pulses for the number of bits to be shifted. The processing time required for shifting increases.

On the other hand, the conventional shift circuit shown in FIG. 4 can obtain data shifted by the desired number of bits by simply setting the value of the n+1 bit select signal, so the processing time required for shifting is extremely short. However, on the other hand, it requires a selector with the number of input terminals equal to the product of the number of bits of input digital data and at least the maximum number of bits to be shifted. As the maximum number of bits to be shifted increases, the amount of circuitry becomes enormous.

The present invention has been made in view of the above points, and an object of the present invention is to provide a shift circuit that can perform a high-speed shift operation with a small-scale circuit configuration.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the same figure, 100~
10. -1 is a selector, and n-bit input terminal Ao
=A and n-bit input terminal B.

-1 to Bn-1, n-bit output terminals O0 to On-1, and a select terminal S. The m selectors 100 to 101-1 (however, 2≦n) are connected in cascade to the output terminal Oo of the previous stage selector 10L (however, t-o-m-2).
``On-1'' is connected to the first input terminal A o ``A n-1 of the next stage selector 10L+1, and the second selector in the cascade connection (k is 1 for the first stage). is the first input terminal A o ”” A p-
The output terminal O0 of the selector 10L at the previous stage is inputted to the second input terminal Bo=BTl so that the digital signal obtained by shifting the digital signal input to the input terminal 1 by 1 bit to 2 is input to the second input terminal Bo=BTl.
~On-1 is connected to the second input terminal B o "" B n-1 of the next stage selector 10r+1.

Further, each bit of the m-bit select signal is input to the select terminal S of the selectors 100 to 10I-1, and one of the input digital signals of the first and second input terminals of each selector 100 to 10I-1 is input. It is selected and output from the output terminals O0 to On-1 of the selector.

(Function) Each bit data Do to Dn-1 of the input digital signal is sent to the first input terminal A o "'- of the selector 100 at the first stage.
On the other hand, it is shifted by 1 (=20) bits and is supplied to the second input terminal Bo''Bo-1. When the lower bit (LSB) 80 is applied and the value is "1" (in other words, "H"), the selector 100 selects the second input terminal B o "" B n-
The 1 (=20) bit-shifted digital signal input to 1 is outputted from output terminals O0 to On-1, and '
0" (in other words, "L"), the selector 100 selects the first input 'jHfAo'"A's D o ""D
The digital-1 signal consisting of n-1 is output as is from the output terminals O0 to On-1.

Therefore, from the selector 100, the input digital signal D
o ”' D n-1 is taken out without being shifted or shifted by 1 bit, and then sent to selector 1 in the next stage.
While it is input as is to the first input terminals Ao to An-1 of selector 101, it is shifted by 2 bits and input to the second input terminal of selector 101.
As a result, when the value of the second bit S+ of the m-bit select signal applied to the select terminal S of the selector 101 from the selector 10+ is "OIf," The output digital signal of 100 is taken out as is without being bit-shifted, and when the value of Sl is "1", it is taken out after being shifted by 2 (=2) bits. Therefore, the input digital signal Do-On-1 is The value of 5O81 is bit-shifted and taken out from selector 10+ by the number of bits that make it a binary number.

Hereafter, in the same manner as above, the final stage selector 101
From 11-1, the input digital signals Do to Dn-1 are m-bit select signals S o "" S ll1-1
The bits are shifted by the number of bits corresponding to the binary value indicated by and extracted.

Therefore, in the present invention, regardless of the length of the number of bits to be shifted, the m-bit select signal S o -8m
The desired number of shift bits can be obtained by setting the value -1, and the configuration has m selectors with 2n bit input and n bit output, so the maximum number of shift bits to be shifted is 2 boxes. The circuit can be configured with a small number of selectors proportional to the index m.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are given the same reference numerals. In this example, m=5. In the example where n=32, the second input terminal So''-83t of the first stage selector 20o receives a 32-bit digital signal Do-D3 shifted by 1 (=20) bits.
0 is input. The second selector 201 selects the digital signal input to the first input terminal Ao=A3+ by 2 (
=2''') The bit-shifted digital signal is input to the second input terminal Bo=83+, and thereafter, the third selector 202, the fourth selector 203, and the fifth (final stage) selector 204 are input in the same manner. are the digital signals input to the first input terminal Ao=A3+, respectively, as 4 (
=22) bits, 8 (=23) bits and 16(=23) bits
=24>bits The bit-shifted digital signal is connected to its second input terminal Bo=83+.

Next, the operation of this embodiment having such a configuration will be explained.

If a signal is obtained by shifting the 32-bit input digital signals DO to D31, for example, 10 bits to the right, then the least significant bit S of the 5-bit select signal
o is "0", second bit S1 is "1", third bit S2 is "O", fourth bit S3 is "1", and fifth bit (most significant bit) S4 is "0". As a result, the selectors 20o, 202 and 204 respectively select and output the 32-bit digital signal of the first input terminal Ao-A3+, and the selectors 20+ and 203 respectively select and output the 32-bit digital signal of the second input terminal Bo-83+. Controlled to selectively output signals.

Therefore, the input digital signal is 32 bits.

~Dss is input to the selector 201 through the selector 20o, where it is shifted to the right by 2 bits, and then input to the selector 202, where it is taken out without being shifted and input to the selector 203, where it is shifted to the right by 8 bits. direction and is taken out, and then the selector 204
is output without being shifted. Therefore, the 32-bit digital signal D input to the first stage selector 20o
o-D3+ is eventually shifted to the right by 2 bits by the selector 201 and by 8 bits by the selector 203, m10 bits, and then taken out from the final stage selector 20<.

In this way, according to this embodiment, it is possible to output a digital signal shifted to the right by the number of bits corresponding to the value when the 5-bit select signals S0 to An-84 are expressed in binary numbers. A digital signal shifted by up to 31 bits can be output. In this embodiment, regardless of the number of bit shifts, the desired number of bit shifts can be set once using the 5-bit select signal, so the processing time required for shifting can be extremely shortened.

Moreover, in this embodiment, the selector with 64-bit input and 32-bit output can only be shifted from 20o to 2
04, which is smaller than the circuit scale of one selector with 1024 (= 32 x 32) bit input and 32 bit output required for maximum 31-bit shift of the 32-bit digital signal in the conventional circuit shown in Fig. 4. Can be done on a small scale.

〔Effect of the invention〕

As described above, according to the present invention, the desired number of shift bits can be obtained by setting the value of the m-bit select signal, so that high-speed processing can be achieved by keeping the time required for shifting constant regardless of the number of bits to be shifted. In addition, since the maximum number of shift bits to be shifted is 2, and the circuit can be configured with a small number of selectors that is proportional to the index m, it is possible to configure an efficient and small-scale circuit with a small amount of circuitry. It has features such as:

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, 3 and 4 are respective conventional circuit diagrams. In the figure, 100-10111-1 is a selector, 20o ~ 204 is 64 bit input 32 bit output selector shows.

Claims (1)

[Claims] In a shift circuit that shifts an n-bit input digital signal by an arbitrary number of bits and outputs the result, an n-bit first input terminal (A_0 to A_n_-_1) and an n-bit second input terminal (B_0 to B_n_-_1) are used. ), n-bit output terminals (O_0 to O_n_-_1), and the first and second input terminals (A_0 to A_n_-_1, B_0 to B_n_-
Select one of the input signals of _1) and output it to the n-bit output terminal (
A selector (10_0 to 10_m) having a select terminal (S) for outputting from O_0 to O_n_-_1)
____1) are connected in cascade (2^m≦n) to connect the output terminal of the previous stage selector to the
is connected to the input terminal of the m selectors (10_
0 to 10_m_-_1) input the input digital signal to the first input terminal into 2^k^-^1 bits (however,
(k is equal to the connection order of the selector concerned, and is 1 for the first stage selector) The output terminal of the previous stage selector and the second stage of the next stage selector are connected so that the shifted digital signal is supplied to the second input terminal. 1. A shift circuit characterized in that the shift circuit is connected to an input terminal and is configured to supply each bit of an m-bit select signal to each select terminal (S) of the m selectors (10_0 to 10_m_-_1).