JPH0215499A - Shift register - Google Patents

Abstract

PURPOSE:To obtain a shift register having general purpose characteristics by providing a register part for which (k) columns of registers to shift a parallel (m)-bit input for (n) bits are provided, an input side select means, an output side select means, and input side and output side control signal sending control means. CONSTITUTION:When setting information is inputted to a control means 7, the control means 7 sends an input side control signal and an output side control signal respectively corresponding to the setting information to an input side select means 5 and an output side select means 6 and controls select operations. Shift registers from that with (m)-bit kn steps to that with km-bit (n) steps can be composed with this type of structure. Namely, the shift register having the (m)-bit kn steps can be obtained when the control signals are those to serially connect all the (k)-column shift registers. Further, when the control signals are those to respectively serially connect odd-column shift registers and even-column shift registers, the shift register having 2m-bit 1/2kn steps can be obtained. After this, the shift registers of 3m bits, 4m bits, etc., can be obtained in the same manner. Thus, the shift register having the general purpose characteristics can be obtained which can correspond to the change or the number of bits and the number of shifts in parallel data.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a shift register used when accumulating and shifting input parallel data, a shift register that can cope with changes in the number of bits of parallel data and the number of shifts as much as possible. With the aim of providing a more versatile shift register, we have developed a shift register section that consists of a shift register that shifts input parallel m-bit data by n bits, and a shift register that shifts input parallel m-bit data in multiple rows. an input side select means that selects according to an input side control signal and sends it to a corresponding shift register; and an output side that selects and outputs a plurality of series of parallel m-bit data output from the shift register section according to an output side control signal. The apparatus is configured to have a selection means, and a control means for sending out the input side control signal and the output side control signal generated according to a predetermined standard corresponding to input setting information.

[Industrial application field]

The present invention relates to a shift register used, for example, when storing and shifting input parallel data.

When converting a shift register into an LSI, for example, input parallel data does not necessarily have the same number of bits. Therefore, we tried to accommodate changes in the number of bits of parallel data and the number of shifts as much as possible.

It is necessary to provide a more versatile shift register.

[Conventional technology]

FIG. 5 is a basic configuration diagram of the shift register, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. Below, the shift register is m rows x N
The operation shown in FIG. 5 will be explained with reference to FIG. 6 assuming that it is composed of a row of D-type printers.

First, when parallel m-bit data is input, the first data D is input at the rising point of the clock (hereinafter abbreviated as CK).
, is taken into the D-FF 01 to (m -1)1 of the first column, and the second data D2 in the primary CK is input to the D-FF of the first column.
- At the same time as being taken into the FF, the first data Dl that was being taken into the D-FP in the first column is transferred to the D-FF in the second column.
will be shifted to Thereafter, each time the GK inputs, the data taken in is shifted toward the D-FF ON to (m-1)N in the Nth column (see FIG. 6).

Next, FIG. 7 shows a block diagram of a conventional example.

The shift register shown in FIG. 5 has m=4. This is the case when N=4. Here, 21 to 36 are D-FF, 21g to 36
' (some symbols omitted) indicates a 3-state gate, and when a control signal of 1 is applied to this 3-state gate, it becomes a short-circuit state (referred to as on) and can take out the output of the corresponding D-FF. However, when a control signal of O is applied, it becomes high impedance (referred to as off) and it becomes impossible to extract the output.

Now, suppose that setting information for configuring a shift register (hereinafter referred to as a 4-bit 4-stage shift register) that shifts parallel 4-bit data by 4 bits is input to the control circuit 37. 3-state gate 24
', 28', 32' and 36' are turned on and control signals are sent to all three-state gates to turn off the other three-state gates, so the shift register in Fig. 7 has a four-bit
It comes to operate as a stage shift register.

In other words, when parallel 4-bit data is input, C
Every time K is added, parallel 4-bit data is sent to D-FF.
At the same time as being taken in on 21.25.29.33.

Previously captured data is shifted to the next column, D-F
Parallel 4-bit data shifted by 4 stages is output from F24, 28, 32, and 36 via the 3-state gate that is turned on.

In addition, three-state gates 23', 27', 31', 35
' is turned on and the others are turned off, the shift register in Figure 7 operates as a 4-bit, 3-stage shift register.
By controlling the position of the three-state gate to be turned on by the control circuit 37, the number of stages can be made variable.

FIG. 8 is a diagram showing an example of application of the conventional example, and is 4 bits.

By switching the switch 38, the output taken out from the four-stage shift register 39 is fed back as shown by the dotted line, and the output is circulated once, so that it can be used, for example, when generating a loop command.

[Problem to be solved by the invention]

Now, as mentioned above, in the case of a 4-bit, 4-stage shift register, the number of stages can be increased from 1 to 1 by controlling the position of the 3-state gate.
It can be varied up to 4.

Also, if the parallel data to be input is 4 bits or less, 4 bits and 3 bits can be input without using the extra -FFO row.
Can handle bit-parallel data.

That is, when the number of stages is 4 as shown in FIG. 7, it can be used as a shift register of 4 stages of 4 bits, 4 stages of 3 bits, or 4 stages of 2 bits.

However, it is not possible to increase the number of stages to four or more, for example, 16 stages for 1 bit and 8 stages for 2 bits, and there is a problem that it lacks versatility.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, reference numeral 4 denotes a shift register section consisting of columns of shift registers that shift input parallel m-bit data by n bits, and 5 selects multiple columns of input parallel m-bit data according to an input-side control signal. This is an input-side select means that selects the selected signal and sends it to the corresponding shift register. Further, 6 is an output side select means for selecting and outputting a plurality of series of parallel m-bit data outputted from the shift register section according to an output side control signal, and 7 is a predetermined selection means corresponding to input setting information. The control means sends out the input side control signal and the output side control signal generated according to the standard.

[Effect]

In the present invention, when setting information is input to the control means 7, the control means 7 sends an input side control signal and an output side control signal corresponding to the setting information to the input side selection means 5 and the output side selection means 6. By controlling the operation of these select means, it is possible to construct a shift register from 1m bits kn stages to km bits n stages.

That is, in the case of a control signal in which all shift registers in a column are connected in series as shown in FIG. 2(a), an m-bit kn stage shift register can be constructed.

However, in the case of a control signal that connects shift registers in odd and even columns in series, as shown in FIG. 2(b), a shift register with 2m pinto%kn stages can be constructed. Hereinafter, 3m bits, 4m bits, and 5m bits can be similarly configured.

This makes it possible to provide a more versatile shift register that can accommodate changes in the number of bits of parallel data and the number of shifts as much as possible.

〔Example〕

FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is an example of the configuration of the selector in FIG. 3.

Here, D-FFs 411 to 414 are components of the first shift register 41, and D-FFs 421 to 424 are components of the second shift register 41.
Components of the shift register 42, D-FF 431~
434 is a component of the third shift register 43, D-F
F 441 to 444 are constituent parts of the fourth shift register 44, selectors 51, 52, 53 are constituent parts of the input side select means 5, selectors 61, 62, and 63 are constituent parts of the output side select means 6, control circuit 71 ．． Decoder 72 represents a component of control means 7.

Hereinafter, m=1. n=4. The operation shown in FIG. 3 will be explained with reference to FIG. Note that since the number of stages is 4, the 3-state gates are 414', 42+', 434'', 44
4" is on and the other three-state gates are off.

First, selector 51.63 in FIG. 3 is a 2-1 selector that selects one signal from two input signals, and selector 52.53.62 selects one signal from three input signals. 3-1 selector, selector 61 selects one signal from four input signals 4-
1 selector.

Examples of configuration diagrams of these selectors are shown in FIG. 4, and the 2-1 selector is as shown in FIG. 4 (al). That is, the control signal from the control circuit (not shown) is When C1 is 0 and C2 is 1, the AND gate 81 is turned on, so the signal input to terminal ■ is output via the OR gate 83.However, when CI is 1° and C2 is 0, the AND gate 81 is turned on.
The D gate 82 is turned on, and the signal input to the terminal ■ is output.

In addition, in Fig. 4 (bl is a 3-1 selector, only the control signal itself is LC, when C3 is 0, only the AND gate 86 is turned on, and the signal input to the terminal ■ is passed through the OR gate 87. However, the control signal C2+ or C
When only 3 is 1, AND gate 85. Or, 84 is turned on, and the signal input to the terminal ■ or the terminal ■ is output.

Further, FIG. 4(C) shows a 4-1 selector in which only the signal input to one AND gate turned on by the control signal is outputted via the OR gate 6'15. Here, 611 to 614 indicate AND gates. That is, by controlling the polarities of the control signals C1 to C4, the signals to be output can be selected.

Next, the operation of FIG. 3 will be explained, and the terminal numbers of the selector in FIG. 1 correspond to the terminal numbers in FIG. 4. The control circuit 71 includes selectors 51 to 53 and selectors 61 to 63 for input side control signals and output side control signals so as to obtain a desired operation by decoding a pattern of 0 and 1 input from an external terminal, for example. A table of patterns corresponding to the number of bits and nine stages of the input signal is prepared in advance, and the above-mentioned patterns are selected from the table.

(1) 4-bit 4-stage shift register configuration control circuit 7
The selectors 51, 52, and 53 select the terminals ■, ■, and ■, respectively, using the input side control signals from the terminal 1, and the selectors 61, 62, and 63 all select the terminal ■ using the output side control signals. Due to this.

D-FF 411~414.421~424.431~
434.441 to 444 constitute a 4-bit 4-stage shift register, and the input parallel 4-bit data is shifted by 4 bits from the selector 61.62.63 and the D-FF 444 and output.

(2) 2-bit 8-stage shift register configuration control circuit 7
With the input side control signal from 1, selectors 51, 52, and 53 select terminal ■, terminal ■, and terminal ■, respectively, and with the output side control signal, selector 61 selects terminal ■ and selector 6.
2 selects the terminal ■, and the selector 63 selects the terminal ■. As a result, D-FF 411 to 414 and D-FF 43
1 to 434 are connected in series, and D-FF 421 to 42
4 and D-FFs 441 to 444 are connected in series to form a 2-bit 8-stage shift register. and.

The 2-bit parallel data is input to the D-FF 421 via the D-FF 411 and the selector 51, and then to the selector 6.
Any one selector from 1 to 63 and D-FF 4
44 and is output after being shifted by 8 bits.

Note that it is also possible to output from any two selectors among the selectors 6L 62 and 63 using the output side control signal.

(3) Configuration of 1-bit 16-stage shift register Similarly to the above, the selector 51 selects the terminal ■, the selector 52 selects the terminal ■, and the selector 53 selects the terminal ■ using the input side control signal, and the output side control signal selects the terminal ■. The selector 61 selects the terminal ■, the selector 62 selects the terminal ■, and the selector 63 selects the terminal ■. As a result, all D-FPs are connected in series to form a 1-bit 16-stage shift register, and D-FF 4
The 1-bit data input to 11 is shifted by 16 bits through all D-FFs.

directly from D-FF 444 or selector 61.6
It is output via any one selector of 2.63.

Note that the above explanation has been made with the number of stages fixed at four.

By changing the position where the three-state gate is turned on, a wider range of requirements can be met.

That is, it is possible to accommodate various requests for the number of bits of input parallel data and the number of shifts as much as possible. A more versatile shift register can be provided.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to meet various requests for the number of bits of input parallel data and the number of shifts as much as possible. This has the effect of providing a more versatile shift register.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is an example of the selector configuration diagram in Fig. 3. , FIG. 5 is a basic configuration diagram of a shift register, FIG. 6 is an explanatory diagram of the operation of FIG. 5, FIG. 7 is a block diagram of a conventional example, and FIG. 8 is a diagram showing an application example of the conventional example. In the figure, 4 indicates a shift register section, 5 indicates input end selection means, 6 indicates output side selection means, and 7 indicates control means. Figure 1's action gimaru-zukozu qu'koi! Inago Yushi 3 g Z Refnu Ding INK's I F'J cow 4 ni ladle (r gichen ko Q feather ρ 1 to \ me kite nigin ℃ n ko C 3. Work on the Silk Half 4 ■ Tsuchikyouhiiji] ρ) No621 et al. (4'18no (NUY已Z)
Figure 8

Claims (1)

[Claims] A shift register section (4) comprising k columns (k is a positive integer) of shift registers for shifting input parallel m-bit data by n bits (m, n are positive integers); , an input side select means (5) for selecting input parallel m-bit data of multiple columns according to an input side control signal and sending the selected data to a corresponding shift register; Output side selection means (6) for selecting and outputting parallel m-bit data according to an output side control signal, and the input side control signal and output side control generated according to a predetermined standard corresponding to input setting information. A shift register characterized in that it has a control means (7) for sending out a signal.