JPS6128165A - Bit location converting device - Google Patents

Abstract

PURPOSE:To output an input signal to an input data latch subjected to arrangement conversion from an output data latch by designating one of patterns stored in a switch designation memory externally and controlling a switch matrix to attain easily the arrangement conversion to the input signal. CONSTITUTION:The input data latch IN consists of n-bit constitution and stores picture data. An output side of a latch IN is connected to an output data latch OUT comprising n-bits in the same way as the latch IN via an nXn-bit switch matrix SMX. The matrix SMX stores p-set of control patterns and is connected to a switch designation memory MEM storing nXnXp switch designation information. When one of p-set patterns is selected and designated externally, the matrix SMX is controlled through a control line from the memory MEM, the input signal stored in the latch IN is subjected to arrangement conversion and the result is outputted from a latch OUT.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image processing device that handles bit images, and in particular to a bit arrangement converter that can invert, enlarge, and reduce/reduce human images at high speed. It is related to.

[Conventional technology]

In conventional image processing devices, when performing hint arrangement conversion operations such as barrel shift, inversion, enlargement, reduction, and OR on a bit image, it is usually performed by software, and hardware Only a shift register was used for supplementary purposes.

The barrel shifter is an operation that shifts multiple bits at once as shown in Figure 3(a), and bit inversion is as shown in Figure 4(a).
As shown in l, the arrangement of a,, b, c, d, e is changed to e, d,
This is an operation to change the arrangement of inputs a, b, c, d to a-, aSb,
This is an operation to place b, c, c, d, d, and reduction is the 6th
As shown in figure (a), input a, b, c= dSe,,I
', g, k+ are arranged as a, c, e, g, and OR is as shown in Figure 7 (a), input a or b is output, input C or d is output, input This is an operation that outputs e or r as an output and input g or h as an output, respectively.

If the bit arrangement conversion operation as described above is performed only by software, it is very time consuming and requires a large amount of software.

In addition, a control method for telephone exchanges has already been developed as a control method for the switch matrix, but this method was originally developed for connecting telephone lines, and once the switch matrix is sent, it remains in that state for several seconds. Since it is used in such a way that it persists, it also has the disadvantage that it is unsuitable for bit arrangement conversion in image processing devices that operate frequently.

[Problem that the invention seeks to solve]

The present invention eliminates the above-mentioned drawbacks, uses a switch matrix in hardware that performs bit arrangement conversion at high speed, and stores a plurality of patterns for controlling this switch matrix in memory in advance each month. By providing a mechanism for selecting one of these patterns according to the data, high-speed and various bit arrangement conversions are made possible.

[Means for solving the problem] A means for solving the problem is to divide the output of the first register, which is composed of a plurality of n bits for storing image data, into an n×n register in the image processing device. It is connected via a switch matrix to a second register consisting of the same bits as the first register, a plurality of types of control patterns of the switch matrix are stored in a memory device, the control pattern is selected from the outside, and the control pattern is connected to the memory device. This is achieved by a bit layout converter controlling the switch matrix according to the selected control pattern of outputs and storing the outputs in a second register.

[Effect]

According to the present invention, image data stored in a first register is stored in a second register via a switch matrix, and the switch matrix is controlled by arbitrarily selecting a plurality of types of control patterns stored in a memory device. Therefore, the effect that bit arrangement conversion can be performed extremely easily is produced.

〔Example〕

FIG. 1 is a conceptual diagram of a focus position converter according to the present invention.

In the figure, MEM is switch specification memory, S, MX is switch matrix, IN is input data launch, OUT
is the output de-flanch. The same symbols represent the same objects throughout all the figures below.

The present invention will be described in detail below with reference to the drawings.

The input data has an n-bit configuration, and the size of the switch matrix SMX is n×n. Therefore, the switch designation memory MEM stores switch designation information in an n×n bit×p pattern.

If one of the p patterns is selected and designated, the switch matrix SMX is controlled by n×n control lines from the switch designation memory MEM, and the input signals stored in the input data lunch IN are rearranged. The output data is output to the output data launch OUT.

FIG. 2 is a diagram showing an embodiment of a 4-bit layout converter.

FIG. 2 shows an example in which the number of registered patterns is four.

In the figure, S41-S44, S31-S34.521-S2
4, Sll-514 are switch gates, 01 to G4 respectively
is an OR gate, and PA is a control pattern address launch.

In this case, the switch designation memory MEM has a 4-word configuration, with each word consisting of 4×4 bits.

By inputting the address of the control pattern stored in the switch specification memory MEM to the control pattern address launch PA, the desired control pattern (4 x 4 bits) can be created.
are switch gates (AND circuits) S41 to S44, S
31 to S34, S21 to S24, and S11 to S14.

On the other hand, the output line 4 of the input data latch IN is
341 to S44, the output line 3 of the input defnch IN is connected to the other inputs of the switch gates 331 to S34, and the output line 2 of the input defnch IN is connected to the other inputs of the switch gates 821 to S24. Output line 1 of input defrunch IN is Swiss
14, the outputs of 341 to Sll respectively become the inputs of the OR gate G1, the outputs of 342 to S12 respectively become the inputs of the OR gate G2, the outputs of 343 to S13 respectively become the human power of the OR gate G3, and the outputs of 344 to S13 become the inputs of the OR gate G3, respectively. S14
The outputs of the respective OR gates 01-G4 are input to the respective OR gates G4, and the outputs of the OR gates 01 to G4 are respectively input to the output data lunches OUT.

FIG. 3(b) shows a case where the present invention is applied to a barrel shifter as an example of application.

In this case, by turning on the switch marked O as shown in Figure 3 (bl), you can perform a single operation of the 2-bit shift saw output to the left.

FIG. 4tb+ shows another example of application to bit inversion.

In this case, it can be realized by turning on the switch marked with a circle, as shown in FIG. 4(b).

Figure 5(b) is enlarged (for example, doubled) as another application example.
The case where it is applied is shown.

In this case, it can be realized by turning on the switch marked with a circle as shown in FIG. 5 (bl).

FIG. 6 (bl shows another example of application to reduction (thinning).

In this case, it can be realized by turning on the switch marked with a circle as shown in FIG. 6 (bl).

FIG. 7 [bl shows another example of application to OR.

In this case, it can be realized by turning on the switch marked with a circle, as shown in FIG. 7 fb).

Various application examples have been described above, but by registering a plurality of types of patterns in advance and selectively using them, the bit arrangement can be easily converted.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect that bit arrangement conversion can be easily performed simply by selecting a control pattern.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a bit arrangement converter according to the present invention. FIG. 2 is a diagram showing an embodiment of a 4-bit layout converter. FIG. 3fa) is a diagram illustrating a barrel shifter, and FIG. 3(b) shows a case where the present invention is applied to a barrel shifter. FIG. 4 tal is a diagram for explaining bit conversion, and [b] shows a case where the present invention is applied to bit conversion. Figure 5 (al is a diagram explaining enlargement, (bl is a diagram showing the case in which the present invention is applied to enlargement). Figure 6 (al is a diagram explaining reduction, [b] is a diagram in which the present invention is applied to reduction) Figure 7 fat is a diagram explaining OR, (bl is a diagram explaining the present invention
The case where it is applied to R is shown. In the figure, MEM is switch specification memory, SMX is switch matrix, IN is input data launch, OUT is output data launch, S11 to 344, S31 to S34, S2
1 to S24, Sll-514 are switch gates, 0
1 to G4 are OR gates, and PA is a control pattern address launch. Mu 1 Mekaya 2 Tsurikaya 3 Close (cL') (b)♀ 4-
Flash Cafu (
bnotnt bttr2 1C: Otsu r4 Cku) (b) *7 Figure

Claims (1)

[Claims] In an image processing device, a first register consisting of a plurality of n bits stores image data, and the output of the first register is
A second register consisting of the same bits as the first register is connected via n switch matrices, a plurality of types of control patterns of the switch matrix are stored in a memory device, and the control pattern is externally selected. A bit arrangement converter characterized in that the switch matrix is controlled by the selected control pattern of the memory device output, and the output is stored in a second register.