JPH04288695A - Synchronous counter - Google Patents

Abstract

PURPOSE:To reduce time and labor and to shorten a time required for test work with compact constitution by providing a counter block control part, and enabling an arbitrary counter block to be skipped. CONSTITUTION:The counter block control circuit 15 is comprised of a count control register 16 and a combination circuit. The count control register 16 is comprised of three bits, and the bits A-C are conformed to the counter blocks 11-13. For example, when the bit A shows '1', an input signal 102 to the enable input terminal Enable of the counter block 11 is inputted to the enable input terminal Enable of a high-order counter block 12. In other words, the counter block 11 can be skipped. Thereby, since a low-order counter block can be skipped, a test on respective counter block can be easily performed. Also, the number of test patterns can be reduced.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous counter, and more particularly to a variable-base synchronous counter that facilitates circuit verification.

0003

2. Description of the Related Art Conventionally, as shown in FIG. 6, a counter block 601 with a count period N1, a counter block 602 with a count period N2, and a counter block 603 with a count period N3 are used to configure a counter with a count period N3. Period N (=N1×N2×N3
) There is a method of configuring the counter 600.

[0004] Hereinafter, a 128-decimal counter has a counter period N.
An example configured with counter blocks of 1=32, N2=2, and N3=2 will be described.

[0005] The 32-decimal counter 601 has a reset terminal R.
When the reset signal 611 input to eset becomes active, zero reset (synchronous reset) is performed at the next clock, the reset signal 611 is disabled, and the count enable signal 610 input to the enable input terminal Enable becomes active. This is a synchronous counter with a synchronous reset that starts counting up in synchronization with the clock 612 (hereinafter referred to as being enabled) when the clock 612 is reached. Carry signal 613 of 32-decimal counter 601
(hereinafter referred to as carry) is the carry output terminal Carr
This signal is output from the enable input terminal Enab as the count enable signal 614 of the next-stage upper counter block (binary counter) 602.
input to le.

Furthermore, the carry 615 of the counter block 602 is input to an enable input terminal Enable as a count enable signal 616 of a binary counter 603 which is an upper counter block. Note that the counter blocks 602 and 603 are also synchronous counters with synchronous reset.

The operations of these counter blocks will be explained using FIG.

When the counter block 601 is enabled, the counter block 601 starts counting in synchronization with the clock 612. And the count value is (3
2-1), the carry 613 becomes active. This carry 613 is the count enable signal 61
4 is input to the enable input terminal Enable of the counter block 602 in the next stage, and the counter block 60
2 is enabled only during the next clock period. That is,
Each time the counter block 601 outputs a carry, the counter block 602 is counted up.

Counter block 602 counts up to (2-1), and counter block 601 counts up to (2-1).
32-1), the counter block 602 outputs a carry and enables the counter block 603 to count up.

Through these operations, the entire counter circuit outputs the counter block 603 every (32×2×2) count.
A carry signal 617 is output as the output of the circuit. That is, it functions as a counter with a count period of (32×2×2).

To test such a counter, use the method shown in FIG.
Counter blocks 601, 602 and 60 as shown in
A method has been adopted in which the carry outputs of each of the three types are connected to the selector 604, and the selector output 618 is switched by the select signals S0 to S2 to perform the test. According to this test method, the carry output 613 of the counter block 601 is verified by 32 clocks, the carry output 615 of the counter block 602 is verified by 32×2 clocks, and the carry output 617 of the counter block 603 is verified by 32×2 clocks. At least 2×2 clocks worth of test data is required. Therefore, the total number of clocks required to test this counter 600 is (32+32×2+32
×2×2=)224 clocks are required.

0012

As described above, in the conventional synchronous counter, as the value of the count period N increases, the test data corresponding to the count period required to verify it also increases. Therefore, a huge amount of test data is required to verify an LSI incorporating a counter with a long counting period, and furthermore, there is a drawback that verification work by simulation using the data is time consuming.

[0013] The present invention solves the above problems.
The purpose is to provide a synchronous counter that has a more compact configuration and can reduce the effort and time required for test work.

[Configuration of the invention]

[0015]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is characterized in that, as shown in FIG. It is constructed by cascading n (n: positive integer) counter blocks each having a carry output terminal that outputs a carry signal when the value is a carry, and the count period is equal to the count of each of the n counter blocks. In a synchronous counter given by the product of periods, the carry signal output from the i-1th counter block or the carry signal from the 1st to i- The counter block control unit 15 is provided to control which of the count enable signals to be input to the first counter block.

[0016]

[Operation] In the synchronous counter of the present invention, the counter block control unit 15 inputs the carry signal output from the i-1th counter block to the enable input terminal Enable of the i-th (1<i≦n) counter block. , or the count enable signal input to any one of the counter blocks from the 1st to the i-1th counter block. It is possible to skip the lower counter blocks by inputting the input to the enable input terminal Enable of the block.Especially in the case of a circuit on an LSI, testing of each counter block becomes easier and fewer test patterns are required. The effort and time required for verification will be significantly reduced.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 shows a synchronous counter according to an embodiment of the present invention. In the figure, the synchronous counter has a count period N (=N1×N2× N3) is configured as a counter.

Below, as a specific design example of the maximum 128-decimal counter, counter period N1=16, N2=4, N3=
An example configured with two counter blocks will be explained.

Each counter block performs a count-up operation in synchronization with the clock 103 when enabled. The carry of each counter block is the carry output terminal Ca.
The carry is output from the rry Output and the carry is sent to the enable input terminal Enable of the upper counter block.
e. Note that the reset by the reset signal 101 is performed by the clock 10.
It is carried out in synchronization with 3.

FIG. 2 shows an example of the configuration of the counter block. Here, a hexadecimal counter (counter block 11) is shown as an example. In the figure, the counter block 11 includes four binary counters 21, 22, 23 and 24.
It consists of When the reset signal 101 is active (“0”), all F
/F is reset to zero. Count enable signal 1
02 is active and the reset signal 101 is disabled, a counting operation is performed in synchronization with the clock 103. Every time each binary counter 21, 22, and 23 is carried up, carry signals 201, 201, and 203 are transmitted sequentially from each binary counter 21, 22, and 23, and finally the count value becomes (16 -1), the carry output 105 of the binary counter 204 is output as the carry of the counter block 11.

The counter control circuit section 15 is composed of a count control register 16 and a combinational circuit. The count control register 16 has a 3-bit configuration, and each bit corresponds to each counter block. That is, bit A
corresponds to counter block 11, bit B corresponds to counter block 12, bit C corresponds to counter block 13, and the counter block corresponding to the bit set to "1" is skipped. Taking the counter block 11 as an example, bit A of the count control register 16 is “1”.
”, the enable input terminal E of the counter block 11
The input signal 102 to nable is input to the enable input terminal Enable of the upper counter block 12. In other words, the counter block 11 is skipped.

Next, the operation of this embodiment will be explained using FIGS. 3 and 4.

FIG. 3 is a time chart showing the timing when the counter block 11 is skipped. When the contents of bits A, B, and C of the count control register 16 are "1, 0, 0" respectively, the count enable signal 102 of the counter block 11 is passed through the combinational circuit to the enable input terminal Enable of the counter block 12.
A common count enable signal is input to counter blocks 11 and 12. Therefore, since counter block 12 is also enabled at the same time that counter block 11 is enabled, both counter blocks 11 and 12 start counting operations. Therefore, the counter block 12 uses the clock 103
It counts up in synchronization with , and the count value is (4-1)
When this happens, carry 108 is output. This carry 10
8 is the counter block 13 enable input terminal Enab
le, and the counter block 13 counts up accordingly. In other words, the operation of counter block 11 does not affect upper counter blocks 12 and 13, and counter block 11 is skipped. As a result, the count period N of the entire counter is (4×2)
becomes.

FIG. 4 is a time chart showing the timing when the counter block 12 is skipped. When the value of the counter block 11 becomes (16-1), a carry 105 is output.
and the enable input terminal Enable of the counter block 13. The carry output 108 from the counter block 12 is also connected to the enable input terminal Enable of the counter block 13.
However, when a carry is output from the counter block 12, the carry is always received from the counter block 11, so when the carry 105 is not output from the counter block 11, the counter block 13 does not operate. do not. In other words,
It may be considered that the counter block 13 receives the carry 105 from the counter block 11 and performs a counting operation independently of the counter block 12. Therefore, the count period N of the entire counter in this case is (16×2).

Although a time chart showing the timing when the counter block 13 is skipped is omitted, in this case, the enable input terminal En of the counter block 13 is
The input to ABLE becomes the output of the entire counter as it is, and the count period N becomes (16×4).

Next, the verification method of this embodiment will be explained using FIG.

The figure conceptually represents the counter block skip operation by the counter block control section described above using changeover switches SW0, SW1, and SW2. First, when testing the counter block 11, switch SW2 is set to b side, switches SW1 and SW0 are
is set to the a side and the counter blocks 12 and 13 are skipped. This causes the counter to operate at 16 clock cycles,
Therefore, the number of test clocks is at least 16 cycles.

Similarly, when testing the counter block 12, only the switch SW1 is set to the b side, and the switch SW1 is set to the b side.
With W0 and SW2 on the a side, counter blocks 11 and 1
3 and when testing the counter block 13, set only the switch SW0 to the b side and switch S
With W1 and SW2 on side a, counter blocks 11 and 1
By skipping 2, the number of clocks required to test each counter block can be at least 4 cycles, or 2 cycles.

When testing the conventional synchronous counter shown in FIG. 6, a test pattern corresponding to 224 (=128+64+32) cycles was required, but in the case of this embodiment, a test pattern corresponding to 22 (=16+4+2) cycles was required. It can be seen that a corresponding test pattern is sufficient and the time required for testing is reduced to one-tenth.

Furthermore, the count period that can be realized in this embodiment is 1, 1, or 1, depending on the value of the count control register 16
16, 4, 2, 16×4 (=64), 4×2 (=8),
It can be set in eight ways: 16×2 (=32) and 16×4×2 (=128).

As shown in FIG. 8, the carries of all the binary counters constituting the conventional example are controlled by a selector 801 (8 to 1 controlled by a 3-bit select signal).
Even if you configure it to select and output from
Same as this example, the count period is 1, 2, 4, 8, 16.
, 32, 64, and 128, but the circuit for selection control is much more complex than in this embodiment. Furthermore, the number of test clocks is 255 (=1+2+4+8+1
6+32+64+128) clocks are required, increasing the time required for testing.

Furthermore, in this embodiment, since the circuit has a configuration of three counter blocks, there are 23 combinations of count periods, but with a configuration of m counter blocks, a maximum of 2m combinations are possible. Become.

Furthermore, in this embodiment, the count period N1=
16, N2=4, and N3=2, but it goes without saying that the gist of the present invention is not limited to this.

[0035]

As described above, according to the present invention, it is possible to skip any count block by the count block control section, so in the case of a circuit on an LSI, it becomes easy to test each counter block. Since fewer test patterns are required, it is possible to provide a synchronous counter that can significantly reduce the effort and time required to verify a counter circuit.

Furthermore, since the count period can be set in many combinations without a parallel load function and the circuit is compact, a variable base counter can be realized with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a synchronous counter according to an embodiment of the present invention.

[Figure 2] An example of a circuit diagram of a counter block

[Figure 3] Time chart showing the timing when skipping a counter block

[Figure 4] Time chart showing the timing when skipping a counter block

FIG. 5 is a diagram illustrating a method for verifying a synchronous counter according to an embodiment of the present invention.

[Figure 6] Circuit diagram of a conventional synchronous counter

[Figure 7] Time chart showing the timing of a conventional synchronous counter

FIG. 8 is a circuit diagram when setting many types of count synchronization in a conventional example.

[Explanation of symbols]

11-13, 601-603 Counter block 15
Counter block control section 16 Count control registers 21 to 24 Binary counters 101, 611 Reset signals 102, 106, 109, 610, 614, 616
Count enable signal 103 of each counter block,
612 Clock signals 105, 108, 111, 613, 615, 617
Carry for each counter block

Claims (1)

[Claims] [Claim 1] As a synchronous counter, n pieces (n: positive integer) each have an enable input terminal that inputs a count enable signal to advance the count, and a carry output terminal that outputs a carry signal when the count value is a carry. In the synchronous counter, which is constructed by cascade-connecting n counter blocks, and whose count period is given by the product of the count periods of each of the n counter blocks, the i-th (1
<i≦n) A carry signal output from the i-1th counter block to the enable input terminal of the counter block, or a count enable signal input to any of the i-1th counter blocks from the 1st to the i-1th counter block, 1. A synchronous counter comprising a counter block control section that controls which of the following is input.