JPH06310996A - Sequence signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a desired sequence signal in a simple circuit scale by blocking the circuit constitution of a sequence signal generating circuit, and selecting an optimal circuit according to the generated sequence signal. CONSTITUTION:A counter circuit 1 inputs a first clock signal a1, first initial value signal b1, and reset signal (c), and outputs a count signal F based on the signal a1. A random pattern generating circuit 2 turns a random pattern output signal (g) into a first state only when the signal F indicates state otherwise. Then, the state of a toggle pattern signal (h) is changed in response to either case when the signal (g) is changed from the first state to the second state, the signal (g) is changed from the second state to the first state, or the state of the signal (g) is changed, and the signal (h) is outputted as the sequence signal. Thus, the desired sequence signal can be obtained by combining the circuit which generates and outputs the signal different from the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly to an image processing LSI (large scale integrated circuit).
cuit: a large-scale integrated circuit) is used for a sequence signal generation circuit.

[0002]

2. Description of the Related Art A conventional sequence signal generation circuit is composed of an n-bit counter circuit which is controlled by a reset signal and is synchronized by a clock signal, and a ROM which stores w-bit 1-word data in 2 @ 2 power words. It The counter circuit outputs an n-bit count value signal. Further, the ROM inputs this n-bit count value signal as an address and outputs a w-bit sequence signal corresponding to this address. Note that n and w are positive integers.

After receiving the reset signal, the counter circuit counts up by 1 at the rising timing of the clock signal and outputs a count value signal. The ROM inputs the count value signal as an address signal and outputs a sequence signal composed of a binary signal according to the ROM data corresponding to the address signal. For example, ROM
Data is a binary signal when the address signal is specific
The data is stored such that the binary signal is "1" and the binary signal is "0" in the other periods.

[0004]

However, the sequence signal generation circuit having the above configuration has the following inconveniences.

(1) Since the ROM is a constituent element, the circuit scale becomes large.

(2) All redundant data such as "0" or "1" continuing in time series (that is, counting up the address value f) must be written in the ROM as data.

An object of the present invention is to provide a sequence signal generation circuit which can easily generate several kinds of sequence signals without the need to write redundant data and which can be configured with a circuit scale smaller than the conventional one. To do.

[0008]

In order to solve the above problems, the present invention provides a counter which outputs a count value signal based on a clock signal, and a random pattern output only when the count value signal shows a specific value. A random pattern generation circuit that puts the signal in the first state and otherwise puts the random pattern output signal in the second state;
This random pattern output signal changes from the first state to the second state.
The state of the toggle pattern signal in response to any one of a change from the second state to the first state or a change in the state of the random pattern output signal. Provided is a sequence signal generation circuit having a toggle pattern generation circuit for changing the toggle pattern signal and outputting the toggle pattern signal as a sequence signal.

Here, in place of the toggle pattern generation circuit, a shift pattern generation for inputting an input signal and a control signal and generating and outputting a shift pattern signal having the same state as the input signal based on the control signal. A circuit can also be used.

Further, a toggle pattern signal, a shift pattern signal or / and a random pattern output signal are input, these input signals are logically operated, and the signal after the operation is output as a pattern synthesis signal. A pattern synthesis circuit may be added.

Further, a toggle pattern signal, a shift
A pattern selection circuit for inputting a control signal such as a pattern signal, a pattern synthesis signal, a random pattern output signal, etc., and selecting one of the input signals in response to the control signal may be further added.

[0012]

The counter circuit generates a signal representing the count value from the clock signal. The random pattern generation circuit, the toggle pattern signal, the shift pattern generation circuit, the pattern synthesis circuit, and the pattern selection circuit are control signals from the input signals, for example, signals representing count values and signals generated / output by other circuits. A signal different from the input signal is generated / output based on the above. By combining these circuits, a sequence signal generation circuit that generates a desired sequence signal can be formed.

[0013]

1 is a block diagram showing a sequence signal generation circuit according to a first embodiment of the present invention. The configuration of the sequence signal generation circuit according to the first embodiment will be described below with reference to this figure. The first embodiment is a sequence signal generation circuit that generates a sequence signal in which "1" or "0" continues for a certain period.

The sequence signal generation circuit of the first embodiment comprises a counter circuit 1, a random pattern generation circuit 2 and a toggle pattern generation circuit 3. The counter circuit 1 has a first clock signal a1 and a first m1 bit signal.
The initial value signal b1 and the reset signal c are input signals. The counter circuit 1 counts up the first initial value signal b1 as 1 as an initial count value at the time of reset after the reset signal c is released, and outputs it as an n-bit count value output signal f. Is.

The random pattern generation circuit 2 is connected to the output of the counter circuit 1, decodes the n-bit count value output signal f, and outputs "1" only when the count value is arbitrarily set, and "0" otherwise. "," Or vice versa, outputs "0" only when the count value is arbitrarily set, and otherwise outputs "1" as the p-bit random pattern output signal g.

The toggle pattern generation circuit 3 is a random
Connected to the output of the pattern generation circuit 2, a point at which the p-bit random pattern output signal g of the random pattern generation circuit 2 changes from "0" to "1" (hereinafter referred to as a rising point), "1" Change from "0" to "0" (hereinafter,
Either the "falling point" or both the rising and falling points are used as a trigger, and a "0" or "1" is alternately inverted by this trigger to output a q-bit toggle pattern signal h. . In this embodiment, the toggle pattern generation circuit 3 is supplied with a reset signal c, a random pattern output signal g and a m2-bit second initial value signal b2. Toggle pattern generation circuit 3
Outputs a q-bit toggle pattern signal h in which the peaks of the random pattern output signal g of "1" are connected by the signal of "1".

FIGS. 21 and 22 are timing charts showing the operation of the circuit shown in FIG. 1. The operation of the sequence signal generating circuit of the first embodiment will be described below with reference to FIGS. 21 and 22. To do. In the sequence signal generation circuit of the first embodiment, m1 = 5, m2 = 2, n = 5, p = 1, q = 1
Is.

First, the operation of the counter circuit 1 of FIG. 1 will be described with reference to the timing chart of FIG. This timing diagram shows a binary signal (f <4>, f) indicating a 5-bit count value by the first clock signal a1 and the reset signal c.
<3>, f <2>, f <1>, f <0>) are output. f <4>, f <3>, f <2
>, F <1>, f <0> are f <4 ... 0> in the following description.
Where f <4> is the most significant bit and f <0> is the least significant bit. 5-bit count output value f <
4. ． 0> can represent 2 to the 5th power, that is, 32 count values. The initial value of f <4 ... 0> is the value of the first initial value signal b1. Like the first clock signal a1, the first initial value signal b1 is a 5-bit binary signal b1 <
4>, b1 <3>, b1 <2>, b1 <1>, b1 <0
>, Which are also represented as b1 <4 ... 0>. In the first embodiment, b1 <4 ... 0>
= “00000”.

The counter circuit 1 has a first clock signal a1.
When the reset signal c is "1", the count value output signal f is set to the first initial value signal b1, and when the reset signal is "0", the count signal output is detected. Increment the signal f by one.

The counter circuit 1 may be an asynchronous counter using a T-type flip-flop or a synchronous counter combining a D-type flip-flop and a half adder. In this embodiment, a counter circuit as shown in FIG. 32 is used.

FIG. 32 is a circuit diagram of the counter circuit used in this embodiment. The counter circuit 1 has five synchronous types 1.
A 5-bit counter circuit composed of bit counters 101 to 109. Each synchronous 1-bit counter 101
To 109 input terminals D are binary signals b1 <0>, b1 <1>, b1 <2>, b which constitute the first initial value signal b1.
1 <3> and b1 <4> are input respectively, and output terminal Q
Are binary signals f <0>, f <1>,
f <2>, f <3>, and f <4> are output respectively.
Further, the first clock signal a1 is commonly used for the clock input terminals CLK of the respective synchronous 1-bit counters 101 to 109.
Is input, and the reset signal c is commonly input to the reset input terminal L. A signal fixed at "1" is input to the carry input terminal CI of the synchronous 1-bit counter 101. The carry output terminal CO of the synchronous 1-bit counter 101 is connected to the carry input terminal CI of the synchronous 1-bit counter 103. Similarly, the carry output terminal CO of the previous stage is connected to the carry input terminal CI of the next stage. The carry output terminal CO of the synchronous 1-bit counter 109 at the final stage is in an open state.

FIG. 33 shows the synchronous 1-bit counter 1 described above.
It is a circuit diagram which shows each circuit structure of 01-109. The synchronous 1-bit counter 200 includes a selector 201,
It is composed of a D flip-flop 203, an exclusive OR (hereinafter referred to as XOR) circuit 205, and an AND circuit 207.

The selector 201 has a first input A and a second input A.
The two input signals input to the input B are selected by the signal applied to the control terminal x, and the selected signal is output from the output S. The first input A is connected to the output of the XOR circuit 205, and the second input B is connected to the input terminal D of the synchronous 1-bit counter 200 to which the binary signal forming the initial value signal b1 is input. The control terminal X is connected to the reset input L of the synchronous 1-bit counter 200 to which the reset signal c is input. The input D of the D flip-flop 203 is the output S of the selector 201, the clock input C is the clock input terminal CLK of the synchronous 1-bit counter 200, and the output Q.
Is connected to the output terminal Q of the synchronous 1-bit counter.
The first input of the XOR circuit 205 is connected to the carry input terminal CI of the synchronous 1-bit counter 200, and the second input is connected to the output Q of the D flip-flop 203. XOR circuit 2
The output of 05 is connected to the first input A of the selector 201. The first input of the AND circuit 207 is a carry input terminal CI of the synchronous 1-bit counter 200, and the second input is D.
It is connected to the output Q of the flip-flop 203. AND
The output of the circuit 207 is connected to the carry output terminal CO of the synchronous 1-bit counter 200.

Next, the operation of the synchronous 1-bit counter 200 will be described. When a "0" signal is input to the reset input terminal L of the synchronous 1-bit counter 200, the counting operation is performed. In addition, the reset input terminal L
When the 1 "signal is input, the data of the input terminal D is taken into the D flip-flop 203 at the rising timing of the clock signal input to the clock input terminal CLK and is output from the output terminal Q. Carry input terminal CI If a signal of "1" is input to, the current output data (the signal of the output terminal Q) is inverted (obtained by taking the exclusive OR with the signal "1" by the XOR circuit 205). The inverted data is output from the output terminal Q at the timing of the rising edge of the clock signal of 1. The carry signal to the next stage (the signal on the carry output terminal CO)
Is obtained by taking the logical product of the carry signal of the preceding stage (the signal on the carry input terminal CI) and the current output data.

Now, returning to the operation of the sequence signal generation circuit of FIG. 1, description will be given with reference to the timing chart of FIG.
The count output value f <4. ． 0> is input to the random pattern generation circuit 2. In the random pattern generation circuit 2, the count output value f <4. ． A random signal is generated according to 0>. The circuit configuration of the random pattern generation circuit 2 of this embodiment is shown in the circuit diagram of FIG.

The random pattern generation circuit 2 outputs the count output value f <4. ． 0> for inputting signal lines 351 to 359
And this count output value f <4. ． 0> to inverter 30
Signal lines 361 to 369 inverted and transmitted at 1 to 309 are used as input signal lines. Random pattern generation circuit 2
Are further provided with first to fourth 5-input AND circuits 311 to 311.
17 and first and second 2-input OR circuits 319 and 3
21 and 21. The inputs of the first 5-input AND circuit 311 are signal lines 361, 353, 365, 367 and 3
It is connected to 69. Therefore, the first 5-input AND circuit 311 outputs the count output value f <4. ． 0> = “0001
The output signal becomes "1" only when it is "0" (when the count value is # 2). Similarly, the second 5-input AND circuit 31
The inputs of 3 are connected to signal lines 361, 363, 355, 357 and 369. Therefore, the second 5-input AN
The D circuit 313 outputs the count output value f <4. ． 0> = "01
The output signal becomes "1" only when it is 100 "(when the count value is # 12).

First and second 5-input AND circuits 31
The outputs of 1, 313 are connected to the inputs of the first 2-input OR circuit 319. Therefore, the output of the first 2-input OR circuit 319 is, as shown in the timing chart of FIG. 22, the count output value f <4. ． 0> = “00010” (when the count value is # 2) and the count output value f <4. ． 0>
== "01100" (when the count value is # 12)
Then, the output signal g <0> becomes "1".

Similar to the above description, the third five-input AND
The input of the circuit 315 is signal lines 361, 363, 355, 3
67 and 369. Therefore, the first 5
The input AND circuit 311 outputs the count output value f <4. ． 0>
The output signal becomes "1" only when "=" 00100 "(when the count value is # 4). The inputs of the fourth 5-input AND circuit 317 are signal lines 361, 363, 365, and 35.
7 and 369. Therefore, the second 5-input AND circuit 313 outputs the count output value f <4. ． 0>
The output signal is "1" only when "= 01000" (when the count value is # 8).

Third and fourth 5-input AND circuits 31
The outputs of 5, 317 are connected to the inputs of the second 2-input OR circuit 321. Therefore, the output of the second 2-input OR circuit 321 is, as shown in the timing chart of FIG. 22, the count output value f <4. ． 0> = “00100” (when the count value is # 4) and the count output value f <4. ． 0>
When = "01000" (when the count value is # 8), the output signal g <1> becomes "1".

Although the random pattern generation circuit 2 shown in FIG. 46 has two output terminals (outputs of the first and second 2-input OR circuits 319 and 321), it is shown in FIG. In the sequence signal generation circuit of the first embodiment, the output of the second 2-input OR circuit 321 is used in the open state. Therefore, the random pattern generation circuit 2 outputs only the signal g <0>.

Returning to FIG. 1, the description will be continued. The random pattern output signal g <0> generated by the random pattern generation circuit 2 is input to the toggle pattern generation circuit 3. In the toggle pattern generation circuit 3, the random pattern is generated within one count cycle (count value is between # 0 and # 31).
The random pattern output signal g <0> generated by the pattern generation circuit 2 functions to connect two pulses of "1".

FIG. 35 is a circuit diagram showing the toggle pattern generation circuit 3 of the first embodiment. The toggle pattern generation circuit 3 includes a D flip-flop 401 with reset and an XO.
And an R circuit 403. D flip-flop 4
A reset signal c common to the counter circuit 1 is input to the reset input R of 01, and a random signal is input to the clock input C.
The random pattern output signal g <0> generated by the pattern generation circuit 2 is input. First of XOR circuit 403
The input is connected to the output Q of the D flip-flop 401,
The second input is supplied with the second initial value signal b2. Second
Initial value signal b2 of m2 is the same as that of the first initial value signal b1.
Bit binary signals b2 <0>, b2 <1>, ... b2
Although it may be configured by <m>, it is configured by only the 1-bit binary signal b2 <0> in the first embodiment. The signal output from the output of the XOR circuit 403 is the output signal h of the toggle pattern generation circuit 3 (the output signal h is composed of q bits, but in this embodiment, it is a 1-bit binary signal h <0>. ). The output of the XOR circuit 403 is also connected to the input D of the D flip-flop 401.

At the time of reset (when the reset signal c is "1"), the output of the D flip-flop 401 is "0". Since the second initial value signal b2 <0> is "0", the inputs of the XOR circuit 403 are "0" and "0", and the output thereof is the output signal h of the toggle pattern generation circuit 400. <0> also becomes “0”.

After the reset, the reset signal c becomes "0". Even if the reset signal c becomes “0”, the output of the D flip-flop 401 remains “0”. Count value #
2, the random pattern output signal g <0> generated by the random pattern generation circuit 2 is from "0"
1 ”. In response to this, the D flip-flop 401
Output changes from "0" to "1". Second initial value signal b
Since 2 <0> is “0”, the inputs of the XOR circuit 403 are “0” and “1”, and the output signal h <0> of the toggle pattern generation circuit 3 which is the output thereof is “1”. Become.

At the count value # 12, the signal g <0> generated by the random pattern generation circuit 2 is again "0".
To "1". In response to this, the output of the D flip-flop 401 changes from "1" to "0". Since the second initial value signal b2 <0> is “0”, the XOR circuit 403
Input is "0" and "0", and the output signal h <0> of the toggle pattern generation circuit 3, which is the output, also returns to "0".

The sequence signal generation circuit of the first embodiment outputs the output signal h of the toggle pattern generation circuit 3 as a sequence signal. Therefore, h <0> in FIG. 22 is the first
3 is a sequence signal of the sequence signal generation circuit of the embodiment.

FIG. 2 is a block diagram showing a sequence signal generating circuit according to the second embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the second embodiment will be described with reference to FIG.

The sequence signal generation circuit of the second embodiment comprises a counter circuit 1, a random pattern generation circuit 2, a toggle pattern generation circuit 13 and a pattern selection circuit 7. The random pattern generation circuit 2 is connected to the output of the counter circuit 1, the toggle pattern generation circuit 13 is connected to the output of the random pattern generation circuit 2, and the pattern selection circuit 7 is connected to the toggle pattern generation circuit 1.
3 output. Since the counter circuit 1 is the same as that of the first embodiment, the description of its configuration and operation will be omitted. Although the circuit configuration of the random pattern generation circuit 2 is also the same as that of the first embodiment, the second output signal g <1> of the random pattern generation circuit 2 is also used in the second embodiment. The output of the OR circuit 321 is connected to the toggle pattern generation circuit 13. The circuit configuration of the toggle pattern generation circuit 13 is shown in FIG. The toggle pattern generation circuit 13 includes D flip-flops 401 and 405 with reset, XOR circuits 403 and 407, and an inverter 9. D flip-flop 4
01 and the XOR circuit 403 are the same as those described above, and the description thereof will be omitted. The reset signal c common to the counter circuit 1 is input to the reset input R of the D flip-flop 405, and the random pattern output signal g <1> generated by the random pattern generation circuit 2 is input to the clock input C.
Is entered. The first input of the XOR circuit 407 is connected to the output Q of the D flip-flop 405, and the second input is supplied with the second initial value signal b2 <1>. XOR circuit 4
The output of 07 is connected to the input of Invar et al. 409 and the input D of D flip-flop 405. Inverter 40
The signal output from the output of 9 becomes the output signal h <1> of the toggle pattern generation circuit 13. The toggle pattern generation circuit 13 outputs the output signals g <0> and g <1> of the random pattern generation circuit 12 and the second initial value signal b2 <0.
>, B2 <1>, output signals h <0>, h <1> are generated.

21 and 22 are timing charts showing the operation of the sequence signal generating circuit shown in FIG. 2. The operation of the sequence signal generating circuit of the second embodiment will be described below with reference to FIGS. 21 and 22. It demonstrates using. In the sequence signal generation circuit of the second embodiment, m1 = 5, m2 = 2, n =
5, p = 2, q = 2, u = 1.

Output signal f <4 ... 0> of counter circuit 1
And the output signal g <0 of the random pattern generation circuit 2
>, G <1> and the first output signal h <0> of the toggle pattern generation circuit 13 are the same as in the first embodiment,
The description thereof will be omitted, and the toggle pattern generation circuit 1 will be described below.
The third output signal h <1> of No. 3 will be described.

At reset (when the reset signal c is "1"), the output signal h <0> of the toggle pattern generation circuit 3
The second output signal h <
1> is “1”. After resetting, the signal g generated by the random pattern generation circuit 2 at the count value # 4
<1> changes from “0” to “1”. In response to this, the second output signal h <1> of the toggle pattern generation circuit 13 is "
Further, the signal g <1> generated by the random pattern generation circuit 2 at the count value # 8 changes from “0” to “1” again. In response to this, the toggle pattern generation circuit 13 Second output signal h <1> also returns to “1.” (See h <1> in FIG. 22) The first and second output signals h <0> and h <1> of the toggle pattern generation circuit 13.
Is input to the pattern selection circuit 7.

FIG. 37 is a circuit diagram of the pattern selection circuit 7 of the sequence signal generation circuit of the second embodiment. The pattern selection circuit 7 is composed of a selector 501. The toggle pattern generation circuit 1 is connected to the first input A of the selector 501.
3 of the first output signal h <0> is toggled to the second input B.
The second output signal h <1> of the pattern generation circuit 13 is input. The mode signal d is input to the control terminal X of the selector 501. The sequence signal 1 is output from the output S of the selector 501.

In the selector 501, when the signal (mode signal d) input to the control terminal X is "0", the signal input to the input A (first output signal h <0> of the toggle pattern generation circuit 13). When the signal (mode signal d) input to the control terminal X is “1”, the signal input to the input B (the second output signal h <1> of the toggle pattern generation circuit 13) is output. ) Is output from the output S.

Now, returning to FIG. 22, the description of the operation of the sequence signal generation circuit of the second embodiment will be continued. First counting cycle (count values # 1 to # 31 on the left side of FIG. 22)
Up to), the mode signal d is "0", so that the pattern selection circuit 7 is the first of the toggle pattern generation circuit 3.
Select the output signal h <0> and set it as the sequence signal l
Output as. Next, the second count cycle (see FIG. 22)
Count value # 1 to # 14 on the right of; count value # 1
5 to # 31 are omitted), the mode signal d is "1".
Therefore, the pattern selection circuit 7 selects the second output signal h <1> of the toggle pattern generation circuit 13 and outputs it as the sequence signal l.

The sequence signal generation circuit of the second embodiment is characterized in that the waveform of the sequence signal can be modified by the mode signal in addition to the features of the sequence signal generation circuit of the first embodiment.

FIG. 3 is a block diagram showing a sequence signal generation circuit according to a third embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the third embodiment will be described with reference to FIG.

The sequence signal generation circuit of the third embodiment comprises a counter circuit 1, a random pattern generation circuit 2, a toggle pattern generation circuit 3 and a pattern synthesis circuit 6. Since the counter circuit 1 and the random pattern generation circuit 2 are the same as those in the second embodiment, the description of their configuration and operation will be omitted. However, in the third embodiment, the output signals of the random pattern generation circuit 2 are used as different signals, so that the indications are the first output signal g1 and the second output signal g2. The toggle pattern generation circuit 3 has a second pattern of the random pattern generation circuit 2.
Output signal g2 is input. The first output signal g1 of the random pattern generation circuit 2 and the output signal h of the toggle pattern generation circuit 3 are input to the pattern synthesis circuit 6. The pattern synthesizing circuit 6 outputs a logical sum signal k of the input signals, which becomes the sequence signal of the sequence signal generating circuit of the third embodiment.

FIG. 23 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 3. The operation of the sequence signal generating circuit of the third embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the third embodiment, m1 = 5, m2 = 1, n = 5, p1 = 1, p2 = 1,
q = 1 and t = 1.

Output signal f <4 ... 0> of counter circuit 1
Since it is the same as that of the first embodiment, its explanation is omitted. The first output signal g1 and the second output signal g2 of the random pattern generation circuit 2 are the same as the output signals g <0> and g <1> in the second embodiment. The second output signal g2 of the random pattern generation circuit 2 is input to the toggle pattern generation circuit 3. The toggle pattern generation circuit 3 is a signal that the second output signal h <1> of the toggle pattern generation circuit 13 shown in FIG. 36 is output without passing through the inverter 409. For this reason, the output signal h of the toggle pattern generation circuit 3 is equal to the “2” of the second output signal h <1> of the toggle pattern generation circuit 3 in the second embodiment.
It has a waveform in which 0 "and" 1 "are inverted. The pattern synthesis circuit 6 receives the first output signal g1 of the random pattern generation circuit 2 and the output signal h of the toggle pattern generation circuit 23.

FIG. 38 is a circuit diagram showing the pattern synthesizing circuit 6 of the sequence signal generating circuit of the third embodiment. The pattern synthesis circuit 6 is composed of a 2-input OR circuit 601. The first input signal of the random pattern generation circuit 2 is applied to the first input of the 2-input OR circuit 601, and the output signal h of the toggle pattern generation circuit 3 is applied to the second input. From the output of the 2-input OR circuit 601, a signal (the second output signal of the pattern synthesizing circuit 6) k <1> obtained by ORing the two input signals is output. The first output of the pattern synthesizing circuit 6 is connected to the first input of the 2-input OR circuit 601, and the first output signal k <0> of the pattern synthesizing circuit 6 is the first output of the random pattern generating circuit 2. It is the same as the output signal g1. In the third embodiment, the first output of the pattern synthesizing circuit 6 is open.

Returning to FIG. 23 and continuing the description, the pattern synthesis circuit 6 of the third embodiment divides the first output signal g1 of the random pattern generation circuit 2 and the output signal h of the toggle pattern generation circuit 3. The signal k <of FIG. 23 which is a logical sum signal
1> is output as the sequence signal k.

The sequence signal generation circuit of the third embodiment is characterized in that it can generate a sequence signal in which a specific value continues for a certain period and both of the specific values are scattered.

FIG. 4 is a block diagram showing a sequence signal generation circuit according to the fourth embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the fourth embodiment will be described with reference to FIG.

The sequence signal generation circuit of the fourth embodiment comprises a counter circuit 1, a random pattern generation circuit 2, a toggle pattern generation circuit 3, a pattern synthesis circuit 6 and a pattern selection circuit 7. Counter circuit 1,
The random pattern generation circuit 2 and the toggle pattern generation circuit 3 are the same as those in the third embodiment, and the pattern selection circuit 7 is the same as that in the second embodiment. . Since the pattern synthesizing circuit 6 of the fourth embodiment also uses the first output of the pattern synthesizing circuit 6 of the third embodiment, in the fourth embodiment, the first output and the second output of the pattern synthesizing circuit 6 are patterned. Connect to the input of the selection circuit 7. The output signal u of the pattern selection circuit 7 becomes the sequence signal of the sequence signal generation circuit of the fourth embodiment.

FIG. 23 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 4, and the operation of the sequence signal generating circuit of the fourth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the fourth embodiment, m1 = 5, m2 = 1, n = 5, p1 = 1, p2 = 1,
q = 1, t = 2, u = 1.

Output signals f of the counter circuit 1, the random pattern generation circuit 2 and the toggle pattern generation circuit 3
<4 ... 0>, g1, g2, and h are the same as those in the third embodiment, and the description thereof is omitted. The pattern synthesis circuit 6 outputs the first output signal g1 of the random pattern generation circuit 2 as it is from the first output as the first output signal k <0>, and also outputs the first output signal of the random pattern generation circuit 2. The second output signal k <1>, which is the logical sum signal of the signal g1 and the output signal h of the toggle pattern generation circuit 3, is
Output from the output of. First count cycle (FIG. 23)
Mode signal d is “0”, the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 6,
It is output as a sequence signal l. Next, the second count cycle (count values # 1 to # 1 on the right side of FIG. 23)
4; the count value # 15 to # 31 is omitted), the mode signal d becomes "1", so the pattern selection circuit 7 selects the second output signal k <1> of the pattern synthesis circuit 6 and Is output as a sequence signal l. Therefore, the sequence signal 1 has a waveform as shown by 1 in FIG.

The sequence signal generation circuit of the fourth embodiment is characterized in that, in addition to the features of the circuit of the third embodiment, the waveform of the sequence signal can be modified by the mode signal.

FIG. 5 is a block diagram showing a sequence signal generation circuit according to a fifth embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the fifth embodiment will be described with reference to FIG.

The sequence signal generation circuit of the fifth embodiment comprises a counter circuit 1, a random pattern generation circuit 12 and a shift pattern generation circuit 4. Fifth
The sequence signal generation circuit of the second embodiment is a random pattern generation circuit 2 of the sequence signal generation circuit of the first embodiment.
To a random pattern generation circuit 12,
Moreover, since the toggle pattern generation circuit 3 is replaced with the shift pattern generation circuit 4, the counter circuit 1
The description of the configuration, operation, etc. will be omitted.

The random pattern generation circuit 12 in the sequence signal generation circuit of the fifth embodiment outputs a 1-bit output signal g. The output signal g is a signal which becomes "1" only when the count value is # 2, which is different from the first embodiment. Therefore, the random pattern generation circuit 12 of the fifth embodiment has the configuration shown in FIG. That is, the random pattern generation circuit 12 of the fifth embodiment has the count output value f <4. ． 0> input signal line 351
.About.359 and the count output value f <4. ． 0> is inverted by inverters 301 to 309 and transmitted.
It has a 69 and a 5-input AND circuit 311. The inputs of the 5-input AND circuit 311 are signal lines 361, 353, and 36.
5, 367 and 369.

The circuit configuration of the shift pattern generation circuit 4 of the sequence signal generation circuit of the fifth embodiment is shown in the circuit diagram of FIG. The shift pattern generation circuit 4 is the first
And a shift register having second D flip-flops 701 and 703. First and second D
The second clock signal a2 is commonly applied to the clock inputs C of the flip-flops 701 and 703. The second clock signal a2 is a clock signal having a frequency different from that of the first clock signal a1. In this embodiment, the frequency of the second clock signal a2 is 1/4 of the frequency of the first clock signal a1. The output signal g of the random pattern generation circuit 12 is applied to the input D of the first D flip-flop 701. An output signal i <0> is output from the output Q of the first D flip-flop 701, and this output Q is connected to the input D of the second D flip-flop 703. The output signal i <1> is output from the output Q of the second D flip-flop 703.

The sequence signal generation circuit of the fifth embodiment outputs the above-mentioned signals i <0> and i <1> as sequence signals.

FIG. 24 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG. 5. The operation of the sequence signal generation circuit of the fifth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the fifth embodiment, m1 = 5, n = 5, p = 1, r = 2.

Output signal f <4 ... 0> of counter circuit 1
Is the same as that of the first embodiment, the description thereof will be omitted.
The output signal g of the random pattern generation circuit 12 is a signal that becomes "1" only when the count value is # 2, as described above. The output signal g of the random pattern generation circuit 2 is input to the shift pattern generation circuit 4.

In the first D flip-flop 701 of the shift pattern generation circuit 4, the signal g of "1" is input to the input D at the count value # 2. Next, between the count value # 2 and the count value # 3, the clock input C
The second clock signal a2 input to the signal rises from "0" to "1". At this time, the first D flip-flop 701 takes in the signal g of "1" and outputs it as the output signal i <0>. Next, count values # 6 and # 7
And the second clock signal a2 rises from "0" to "1" again, the first D flip-flop 7
01 takes in the signal g of "0" and outputs it as the output signal i <
Output as 0>. On the other hand, the second D flip-flop 703 takes in the signal i <0> of "1" and outputs it as the output signal i <1>. In the second D flip-flop 703, the second clock signal a2 is between "0" and "1" between the count value # 10 and the count value # 11.
When it rises, the output signal i <1> falls from "1" to "0".

In the sequence signal generation circuit of the fifth embodiment, the basic waveform is the first stage (first D flip-flop 7) of the shift pattern generation circuit 4 (shift register).
01) and shifts it by the period of the second clock signal a2 (2 bits in the fifth embodiment).
It has a feature that can generate the sequence signal of. Also, the fifth
The sequence signal generation circuit of this embodiment is characterized in that the amount of hardware per sequence signal can be handled by one flip-flop.

FIG. 6 is a block diagram showing a sequence signal generation circuit according to a sixth embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the sixth embodiment will be described with reference to FIG.

The sequence signal generation circuit of the sixth embodiment comprises a counter circuit 1, a random pattern generation circuit 12, a shift pattern generation circuit 4 and a pattern selection circuit 7. The sequence signal generation circuit of the sixth embodiment is obtained by adding a pattern selection circuit 7 to the sequence signal generation circuit of the fifth embodiment. Therefore, description of the configurations, operations, etc. of the counter circuit 1, the random pattern generation circuit 12, and the shift pattern generation circuit 4 will be omitted. In the sequence signal generation circuit of the sixth embodiment, the output signals i <0> and i <1> of the shift pattern generation circuit 4 are output.
Is selected by the same pattern selection circuit 7 as the pattern selection circuit 7 of the sequence signal generation circuit of the second embodiment, and the selected signal is output as the sequence signal l.

FIG. 24 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 6. The operation of the sequence signal generating circuit of the sixth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the sixth embodiment, m1 = 5, n = 5, p = 1, r = 2, u = 1.

Output signal f of counter circuit 1, random pattern generation circuit 2 and shift pattern generation circuit 4
<4 ... 0>, g, i <0>, and i <1> are the same as those in the fifth embodiment, and the description thereof will be omitted. In the first count cycle (count values # 1 to # 31 on the left side of FIG. 24), the mode signal d is “0”, so the pattern selection circuit 7 outputs the first output signal i of the shift pattern generation circuit 4. Select <0> and output it as a sequence signal l. Next, the second count cycle (from count values # 1 to # 14 on the right side of FIG. 24; count value # 15)
To # 31 are omitted), the mode signal d becomes "1", and therefore the pattern selection circuit 7 selects the second output signal i <1> of the shift pattern generation circuit 4 and sets it as the sequence signal l. Output.

The sequence signal generation circuit of the sixth embodiment is characterized in that the waveform of the sequence signal can be modified by the mode signal in addition to the features of the circuit of the fifth embodiment.

FIG. 7 is a block diagram showing a sequence signal generation circuit according to a seventh embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the seventh embodiment will be described with reference to FIG.

The sequence signal generation circuit of the seventh embodiment comprises a counter circuit 1, a random pattern generation circuit 22, a shift pattern generation circuit 4 and a pattern synthesis circuit 6. Since the counter circuit 1 is the same as that of the first embodiment, the description of its configuration and operation will be omitted.

The circuit configuration of the random pattern generation circuit 22 of the seventh embodiment is shown in FIG. random·
The pattern generation circuit 22 outputs the count output value f <4. ． 0>
Input signal lines 351 to 359 and the count output value f <4. ． 0> is inverted by inverters 301 to 309 and transmitted, and signal lines 361 to 369 are used as input signal lines. The random pattern generation circuit 22 further includes first and second 5-input AND circuits 311 and 323. The input of the first 5-input AND circuit 311 is the signal line 36.
1, 353, 365, 367 and 369. Therefore, the first 5-input AND circuit 311 outputs the count output value f <4. ． Only when 0> = “00010” (when the count value is # 2), the output signal becomes “1”. Similarly, the input of the second 5-input AND circuit 323 is connected to the signal lines 361, 353, 365, 357 and 369. Therefore, the second 5-input AND circuit 313 outputs the count output value f <4. ． Only when 0> = “01010” (when the count value is # 10), the output signal is “
The random pattern generation circuit 22 outputs the output of the first 5-input AND circuit 311 to the second output and the second 5
The output of the input AND circuit 323 is used as the first output, and the respective output signals are the second and first output signals g2 and g1.
I am trying.

The second output signal g2 of the random pattern generation circuit 22 is input to the shift pattern generation circuit 4. The first output signal g1 of the random pattern generation circuit 22 and the output signal i of the shift pattern generation circuit 4
Is input to the pattern synthesis circuit 6. The pattern synthesizing circuit 6 outputs the first input signal as it is and a logical sum signal of the first and second input signals, which becomes the sequence signal k of the sequence signal generating circuit of the seventh embodiment.

FIG. 25 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 7. The operation of the sequence signal generating circuit of the seventh embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the seventh embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, r = 1, t
= 2.

Output signal f <4 ... 0> of counter circuit 1
Since it is the same as that of the first embodiment, its explanation is omitted. As described above, the first output signal g1 and the second output signal g2 of the random pattern generation circuit 22 are signals that become "1" at the count values # 10 and # 2, respectively. Since the second output signal g2 of the random pattern generation circuit 22 is input to the shift pattern generation circuit 4, its output signal i is the first output signal i of the shift pattern generation circuit 4 in the fifth embodiment. It is the same as <1>. Since the second output of the shift pattern generation circuit 4 (Q output of the D flip-flop 703 in FIG. 53) is in the open state, the output signal of the shift pattern generation circuit 4 is indicated by i. The first output signal g1 of the random pattern generation circuit 2 and the output signal i of the shift pattern generation circuit 4 are input to the pattern synthesis circuit 6.

Returning to FIG. 25 and continuing the description, the pattern synthesizing circuit 6 regards the same signal as the first output signal g1 of the random pattern generating circuit 2 as the first output signal k <0> and the random pattern. The logical sum signal of the first output signal g1 of the generation circuit 22 and the output signal i of the shift pattern generation circuit 4 is output as the second output signal k <1>. The first and second output signals k <0> and k <1> are the seventh
Sequence signal k of the sequence signal generation circuit of the embodiment
Is.

The sequence signal generation circuit of the seventh embodiment is characterized in that the plurality of shifted patterns can generate a sequence signal having a specific value at a common location.

FIG. 8 is a block diagram showing a sequence signal generation circuit according to an eighth embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the eighth embodiment will be described with reference to FIG.

The sequence signal generation circuit of the eighth embodiment comprises a counter circuit 1, a random pattern generation circuit 22, a shift pattern generation circuit 4, a pattern synthesis circuit 6 and a pattern selection circuit 7. The sequence signal generation circuit of the eighth embodiment has a configuration in which the pattern selection circuit 7 is connected to the output of the pattern synthesis circuit 6 of the sequence signal generation circuit of the seventh embodiment. Therefore, the counter circuit 1, the random pattern generation circuit 22, the shift pattern generation circuit 4, and the pattern synthesis circuit 6 are
Since it is the same as the embodiment described above, the description of its configuration and operation will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generating circuit according to the eighth embodiment has the first and second output signals k <0> and k <of the pattern synthesizing circuit 6.
1> by the pattern selection circuit 7 to select the sequence signal l
Output as.

FIG. 25 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 8. The operation of the sequence signal generating circuit of the eighth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the eighth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, r = 1, t
= 2 and u = 1.

Output signal f <4 ... 0 of counter circuit 1
>, The first output signal g1 and the second output signal g2 of the random pattern generation circuit 22, the output signal i of the shift pattern generation circuit, and the first and second output signals k <0> of the pattern synthesis circuit 6. , K <1> are the same as those in the seventh embodiment, the description thereof will be omitted and the pattern selection circuit 7 will be described.
The operation of the sequence signal generation circuit according to the eighth embodiment will be described with a focus on the operation of FIG.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 25), the mode signal d
Is "0", the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 6 and outputs it as the sequence signal l. Next, the second count cycle (from the count values # 1 to # 14 on the right side of FIG. 25);
In the count values # 15 to # 31), the mode signal d becomes “1”, so the pattern selection circuit 7 selects the second output signal k <1> of the pattern synthesis circuit 6 and outputs it as the sequence signal. Output as l. Therefore, the sequence signal l has a waveform as shown by l in FIG.

The sequence signal generation circuit of the eighth embodiment has the feature that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the seventh embodiment.

FIG. 9 is a block diagram showing a sequence signal generation circuit according to a ninth embodiment of the present invention. Less than,
The configuration of the sequence signal generation circuit according to the ninth embodiment will be described with reference to FIG.

The sequence signal generation circuit of the ninth embodiment comprises a counter circuit 1, a random pattern generation circuit 12, a shift pattern generation circuit 4 and a mask pattern generation circuit 5. The sequence signal generation circuit of the ninth embodiment has a configuration in which the mask pattern generation circuit 5 is connected to the output of the shift pattern generation circuit 4 of the sequence signal generation circuit of the fifth embodiment. Description of the configurations and operations of the pattern generation circuit 12 and the shift pattern generation circuit 4 will be omitted.

As described in the sequence signal generation circuit of the fifth embodiment, the shift pattern generation circuit outputs the four-wave first and second output signals i <0> and i <1>. The mask pattern generation circuit 5 outputs the signal i <0>,
i <1> and the mask signal e are input, and these signals are output as a sequence signal.

FIG. 42 is a circuit diagram of the mask pattern generation circuit 5. The mask / pattern generation circuit 5 is composed of first and second 2-input AND circuits 801 and 803. First and second 2-input AND circuits 801, 803
A mask signal e is commonly applied to the first input of the. First
Of the shift pattern generating circuit 4 is input to the second input of the shift pattern generating circuit 4 and the second input of the second 2-input AND circuit 803 is input to the second input of the shift pattern generating circuit 4. The second output signal i <1> is provided. FIG. 26
Is a timing chart showing the operation of the sequence signal generation circuit shown in FIG. 9, and the operation of the sequence signal generation circuit of the ninth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the ninth embodiment, m1 = 5, n =
5, p = 1, r = 2, s = 2.

Output signal f <4 ... 0 of counter circuit 1
>, The output signal g of the random pattern generation circuit 12 and the first output signal i <0 of the shift pattern generation circuit 4
> And the second output signal i <1> are the same as those in the fifth embodiment, the description thereof will be omitted. Therefore, the operation of the sequence signal generation circuit of the ninth embodiment will be described with reference to FIG. 42, focusing on the operation of the mask pattern generation circuit 5.

The mask signal e input to the mask pattern generation circuit 5 is at regular intervals as shown by e in FIG. 26 (in the ninth embodiment, once every four count values,
That is, it is a signal that becomes “0” at the count values # 2, # 6, # 10, ... The first 2-input AND circuit 801 outputs the output signal j <0> of "1" only when both the first output signal i <0> of the shift pattern generation circuit 4 and the mask signal e are "1". . Therefore, the first output signal j <0> of the mask pattern generation circuit 5 becomes a signal which becomes "1" during the period of the count values # 3 to # 5.
The second 2-input AND circuit 803 outputs the output signal j <1> of "2" only when the second output signal i <1> of the shift pattern generating circuit 4 and the mask signal e are "1".
1 ". Therefore, the mask pattern generation circuit 5
The second output signal j <1> becomes a signal that becomes “1” during the period of the count values # 7 to # 9.

The sequence signal j of the sequence signal generation circuit of the ninth embodiment is the first signal of the mask pattern generation circuit 5.
Output signal j <0> and a second output signal j <1>. The sequence output signals j <0> and j <shown in FIG.
If 1> is to be generated only by the sequence signal generation circuit of the fifth embodiment, four shift registers driven by the same clock signal a1 as the counter circuit 1 are required, and the amount of hardware (circuit configuration) increases. . The sequence signal generation circuit of the ninth embodiment is characterized in that the above-mentioned functions can be formed with a small circuit configuration.

FIG. 10 is a block diagram showing a sequence signal generation circuit according to the tenth embodiment of the present invention. The configuration of the sequence signal generation circuit according to the tenth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the tenth embodiment is the counter circuit 1, the random pattern generation circuit 12,
It is composed of a shift pattern generation circuit 4, a mask pattern generation circuit 5 and a pattern selection circuit 7. First
The sequence signal generation circuit of the No. 0 embodiment is the mask pattern generation circuit 5 of the sequence signal generation circuit of the ninth embodiment.
The pattern selection circuit 7 is connected to the output of the. Therefore, since the counter circuit 1, the random pattern generation circuit 12, the shift pattern generation circuit 4, and the mask pattern generation circuit 5 are the same as those in the ninth embodiment, the description of the configuration and operation thereof will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generation circuit of the tenth embodiment selects the first and second output signals j <0> and j <1> of the mask pattern generation circuit 5 by the pattern selection circuit 7 and outputs them as the sequence signal l. . FIG. 26 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG. 10. The operation of the sequence signal generation circuit of the tenth embodiment will be described below with reference to FIG. In the sequence signal generation circuit of the tenth embodiment, m1 = 5, n = 5, p = 1, r = 1, s = 2, u = 1.

Output signal f <4 ... 0 of counter circuit 1
>, The output signal g of the random pattern generation circuit 12, the output signals i <0>, i <1> of the shift pattern generation circuit
Since the first and second output signals j <0> and j <1> of the mask / pattern generation circuit 5 are the same as those in the ninth embodiment, the description thereof will be omitted and the operation of the pattern selection circuit 7 will be mainly described. The operation of the sequence signal generation circuit of the tenth embodiment will be described below.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 26), the mode signal d
Is "0", the pattern selection circuit 7 selects the first output signal j <0> of the mask pattern generation circuit 5 and outputs it as the sequence signal l. Second
26 (count values # 1 to # 14 on the right side of FIG. 26; count values # 15 to # 31 are omitted), the mode signal d becomes “1”, and therefore the pattern selection circuit 7 generates the mask pattern. Select the second output signal j <1> of the circuit 5 and output it as the sequence signal l. Therefore, the sequence signal 1 has a waveform as shown by 1 in FIG.

The sequence signal generation circuit of the tenth embodiment has the feature that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the ninth embodiment.

FIG. 11 is a block diagram showing a sequence signal generation circuit according to an eleventh embodiment of the present invention. The configuration of the sequence signal generation circuit according to the eleventh embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the eleventh embodiment is a counter circuit 1, a random pattern generation circuit 22,
It is composed of a shift pattern generation circuit 4, a mask pattern generation circuit 5 and a pattern synthesis circuit 6. Since the counter circuit 1, the random pattern generation circuit 22, and the shift pattern generation circuit 4 are the same as those in the seventh embodiment, the description of the configuration and operation thereof will be omitted.

In the sequence signal generation circuit of the eleventh embodiment, the mask pattern generation circuit 5 is connected to the output of the shift pattern generation circuit 4, and the output of this mask pattern generation circuit 5 and the random pattern generation circuit 22. The first output is connected to the pattern synthesis circuit 6.

The mask pattern generation circuit 5
The output signal i of the pattern generation circuit 4 is input. The first output signal g1 of the random pattern generation circuit 2 and the output signal j of the mask pattern generation circuit 5 are input to the pattern synthesis circuit 6. The pattern synthesizing circuit 6 outputs a logical sum signal of the input signals, which becomes the sequence signal k of the sequence signal generating circuit of the eleventh embodiment.

FIG. 27 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG.
The operation of the sequence signal generation circuit of the first embodiment will be described with reference to FIG. In the sequence signal generation circuit of the eleventh embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, r =
1, s = 1, t = 2.

Output signal f <4 ... 0 of counter circuit 1
>, First output signal g1 and second output signal g2 of random pattern generation circuit 22, output signal i of shift pattern generation circuit 4, mask signal e, clock signal a2
Since it is the same as that of the seventh embodiment, its explanation is omitted. The output signal i of the shift pattern generation circuit 4 is input to the mask pattern generation circuit 5. In the mask pattern generation circuit 5, only when both the output signal i of the shift pattern generation circuit 4 and the mask signal e are "1" (the period of the count values # 3 to # 5), the output signal j is set to "1". To do. The first output signal g1 of the random pattern generation circuit 2 and the output signal j of the mask pattern generation circuit 5 are input to the pattern synthesis circuit 6. The pattern synthesis circuit 6 sets the same signal as the first output signal g1 of the random pattern generation circuit 2 as the first output signal k <0> and masks the first output signal g1 of the random pattern generation circuit 22 with the mask signal. The logical sum signal with the output signal j of the pattern generation circuit 5 is output as the second output signal k <1>. The first and second output signals k <0> and k <1> are the sequence signal k of the sequence signal generation circuit of the eleventh embodiment.

The sequence signal generation circuit of the eleventh embodiment can generate a sequence signal in which a specific value exists at a common place in a plurality of patterns which are shifted and whose unnecessary portions are masked by the mask / pattern synthesis circuit. There are features.

FIG. 12 is a block diagram showing a sequence signal generation circuit according to a twelfth embodiment of the present invention. The configuration of the sequence signal generation circuit according to the twelfth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the twelfth embodiment is a counter circuit 1, a random pattern generation circuit 22,
It is composed of a shift pattern generation circuit 4, a mask pattern generation circuit 5, a pattern synthesis circuit 6 and a pattern selection circuit 7. The sequence signal generation circuit of the twelfth embodiment has a configuration in which a pattern selection circuit 7 is connected to the output of the pattern synthesis circuit 6 of the sequence signal generation circuit of the eleventh embodiment. Therefore, the counter circuit 1, the random pattern generating circuit 22, the shift pattern generating circuit 4, the mask pattern generating circuit 5 and the pattern synthesizing circuit 6 are the same as those in the eleventh embodiment.
The description of the operation is omitted. Also, the pattern selection circuit 7
Since it is the same as the second embodiment, the description of its configuration, operation, etc. will be omitted. The sequence signal generation circuit of the twelfth embodiment selects the first and second output signals k <0> and k <1> of the pattern synthesis circuit 6 by the pattern selection circuit 7 and outputs them as the sequence signal l.

FIG. 27 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG.
The operation of the sequence signal generation circuit of the second embodiment will be described with reference to FIG. In the sequence signal generation circuit of the twelfth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, r =
1, s = 1, t = 2, u = 1.

Output signal f <4 ... 0 of counter circuit 1
>, The first output signal g1 and the second output signal g2 of the random pattern generation circuit 22, the output signal i of the shift pattern generation circuit, the output signal j of the mask pattern generation circuit 5, and the first output signal of the pattern synthesis circuit 6. Since the second output signals k <0> and k <1> are the same as those in the eleventh embodiment, a description thereof will be omitted and the sequence signal generation in the twelfth embodiment will be focused on the operation of the pattern selection circuit 7. The operation of the circuit will be described.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 27), the mode signal d
Is "0", the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 6 and outputs it as the sequence signal l. Next, the second count cycle (from the count values # 1 to # 14 on the right side of FIG. 27);
In the count values # 15 to # 31), the mode signal d becomes “1”, so the pattern selection circuit 7 selects the second output signal k <1> of the pattern synthesis circuit 6 and outputs it as the sequence signal. Output as l. Therefore, the sequence signal 1 has a waveform as shown by 1 in FIG.

The sequence signal generation circuit of the twelfth embodiment has the feature that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the eleventh embodiment.

FIG. 13 is a block diagram showing a sequence signal generation circuit according to a thirteenth embodiment of the present invention. The configuration of the sequence signal generation circuit according to the thirteenth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the thirteenth embodiment is the counter circuit 1, the random pattern generation circuit 32,
It is composed of a shift pattern generation circuit 14, a mask pattern generation circuit 15, and a pattern synthesis circuit 16. Since the counter circuit 1 is the same as that of the eleventh embodiment, the description of its configuration and operation will be omitted.

As shown in FIG. 43, the random pattern generation circuit 32 of the thirteenth embodiment has a count output value f <
4. ． 0> for inputting the signal lines 351 to 359 and the count output value f <4. ． 0> to inverters 301-309
The signal lines 361 to 369 which are inverted and transmitted at are used as input signal lines. The random pattern generation circuit 32 further includes a first 5-input AND circuit 3 which is the same as the 5-input AND circuit 311 of the random pattern generation circuit 22 shown in FIG.
11 and a second 5-input AND circuit 325. A description of the connection relationship of the first 5-input AND circuit 311 will be omitted because it is redundant. First 5-input AND circuit 31
From 1 outputs the second output signal g2. As described in the description of FIG. 54, the second output signal g2 has the count output value f <4. ． Only when 0> = “00010” (when the count value is # 2), the output signal becomes “1”. Inputs of the 5-input AND circuit 325 are signal lines 351, 363, and 36.
5, 357 and 369. Therefore, the first output signal g1 output from the first 5-input AND circuit 311 is the count output value f <4. ． 0> = “0100
The output signal becomes "1" only when it is 1 "(when the count value is # 9). The first output signal g1 generated by the random pattern generation circuit 32 is the pattern synthesis circuit 16
In addition, the second output signal g2 is the shift pattern generation circuit 1
4 is input.

FIG. 44 is a circuit diagram showing the circuit configuration of the shift pattern generation circuit 14. The shift pattern generation circuit 14 is the shift pattern generation circuit 4 of FIG. 40 having a 3-bit configuration. Specifically, the shift pattern generation circuit 14 is composed of a shift register having first, second and third D flip-flops 701, 703 and 705. The second clock signal a2 is commonly applied to the clock inputs C of the first, second and third D flip-flops 701, 703 and 705. The second clock signal a2 is a clock signal having a frequency different from that of the first clock signal a1. In this embodiment, the frequency of the second clock signal a2 is 1/4 of the frequency of the first clock signal a1. The input D of the first D flip-flop 701 is supplied with the second output signal g2 of the random pattern generation circuit 32. First D flip-flop 701
The output signal i <0> is output from the output Q of
This output Q is the input D of the second D flip-flop 703.
Connected to. An output signal i <1> is output from the output Q of the second D flip-flop 703, and this output Q is connected to the input D of the third D flip-flop 705. The output signal i <2> is output from the output Q of the third D flip-flop 705. In this embodiment, the output signal i <0> is also used as the first signal i1 and the output signals i <0>, i <1> and i <2> are also used as the second signal i2. Therefore, the output Q of the first D flip-flop 701 is supplied to the mask pattern generation circuit 15 and the pattern synthesis circuit 16 and the second D flip-flop 70.
The output Q of 3 is connected to the mask pattern generation circuit 15, and the output Q of the third D flip-flop 705 is connected to the mask pattern generation circuit 15.

FIG. 45 is a circuit diagram of the mask pattern generation circuit 15. The mask pattern generation circuit 15 is shown in FIG.
The mask pattern generation circuit 5 of FIG. 3 has a 3-bit configuration, and the first, second and third 2-input AND circuits 80
1, 803, 805. The mask signal e is commonly applied to the first inputs of the first, second and third 2-input AND circuits 801, 803 and 805. First two
The output signal i <0> of the shift pattern generation circuit 14 is supplied to the second input of the input AND circuit 801 as the second 2-input AN.
The output signal i <1> of the shift pattern generation circuit 14 is applied to the second input of the D circuit 803, and the third 2-input AND circuit 8
The output signal i <2> of the shift pattern generation circuit 14 is applied to the second input of 05. The output signal j <0> is output from the output of the first AND circuit 801 of the mask pattern generation circuit 15, the output signal j <1> is output from the output of the second AND circuit 803, and the output signal j <1> of the third AND circuit 805 is output. An output signal j <2> is output from the output. Since the output signal j <2> is used as the output signal j in this embodiment, the third signal
The output of the AND circuit 805 is connected to the pattern synthesizing circuit 16, and the first and second AND circuits 801 and 80
The output of 3 is opened.

FIG. 46 is a circuit diagram showing the circuit configuration of the pattern synthesis circuit 16. The pattern synthesis circuit 16 is composed of first and second OR circuits 603 and 605. First
The output signal j of the mask pattern generation circuit 5 is applied to the first input of the OR circuit 603. First OR circuit 603
The first output signal g1 of the random pattern generation circuit 32 is commonly applied to the second input of the above and the first input of the second OR circuit 605. The first signal i1 of the shift pattern generation circuit 14 is supplied to the second input of the second OR circuit 605. The output of the second OR circuit 605 outputs the first output signal k <0>, and the output of the first OR circuit 603 outputs the second output signal k <1>. FIG. 28 shows FIG.
FIG. 32 is a timing chart showing an operation of the sequence signal generation circuit shown in FIG. 28, and the operation of the sequence signal generation circuit of the thirteenth embodiment will be described below with reference to FIG. 28. In the sequence signal generation circuit of the 13th embodiment, m1 = 5, n = 5
p1 = 1, p2 = 1, r1 = 1, r2 = 3, s = 1, t
= 2.

Output signal f of counter circuit 1 f <4 ... 0
>, The mask signal e, and the clock signal a2 are the same as those in the eleventh embodiment, and the description thereof will be omitted. As described above, the first output signal g1 of the random pattern generation circuit 32 is the count output value f <4. ． 0> = “01001”
Only (when the count value is # 9), the output signal becomes "1", and the second output signal g2 has the count output value f <4. ． Only when 0> = “00010” (when the count value is # 2), the output signal becomes “1”. Output signals i <0>, i <1> of the shift pattern generation circuit 14
Is the same as that of the ninth embodiment, and its explanation is omitted. The output signal i <2> of the shift pattern generation circuit 14 is a signal further delayed from the output signal i <1>, and as shown in FIG.
1 "signal. Mask pattern generation circuit 15
Then, the output signal i <0 of the shift pattern generation circuit 14
>, I <1>, i <2> and the mask signal e are “1” respectively, the output signals j <0>, j <1>, j
<2> is set to “1”. The pattern synthesis circuit 16 outputs the first output signal g1 of the random pattern generation circuit 32 and the output signals i <0>, (i of the shift pattern generation circuit 14).
The logical sum signal of 1) is used as the first output signal k <0>,
First output signal g1 of the random pattern generation circuit 32
And a logical sum signal of the output signal j of the mask pattern generation circuit 15 is output as a second output signal k <1>. The first and second output signals k <0> and k <1> are the thirteenth
Sequence signal k of the sequence signal generation circuit of the embodiment
Is.

The sequence signal generating circuit of the thirteenth embodiment has a pattern in which a specific value exists in the shifted pattern, or a plurality of patterns in which unnecessary portions that have been shifted are masked by a mask / pattern synthesizing circuit. , There is a feature that a sequence signal having a specific value in a common place can be generated.

FIG. 14 is a block diagram showing a sequence signal generating circuit according to the 14th embodiment of the present invention. The configuration of the sequence signal generation circuit according to the 14th embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the fourteenth embodiment is the counter circuit 1, the random pattern generation circuit 32,
It is composed of a shift pattern generation circuit 14, a mask pattern generation circuit 15, a pattern synthesis circuit 16 and a pattern selection circuit 7. The sequence signal generation circuit of the fourteenth embodiment has a configuration in which the pattern selection circuit 7 is connected to the pattern synthesis circuit 16 of the sequence signal generation circuit of the thirteenth embodiment. Therefore, the counter circuit 1, the random pattern generation circuit 32, the shift pattern generation circuit 14, of the sequence signal generation circuit of the fourteenth embodiment,
Since the mask / pattern generation circuit 15 and the pattern synthesis circuit 16 are the same as those in the thirteenth embodiment, the description of the configuration and operation thereof will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generation circuit of the fourteenth embodiment selects the first and second output signals k <0> and k <1> of the pattern synthesis circuit 16 by the pattern selection circuit 7 and outputs them as the sequence signal l.

FIG. 28 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG.
The operation of the sequence signal generation circuit of the fourth embodiment will be described with reference to FIG. In the sequence signal generation circuit of the fourteenth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, r1
= 1, r2 = 3, s = 1, t = 2, u = 1.

Output signal f of counter circuit 1 f <4 ... 0
>, First output signal g1 and second output signal g2 of random pattern generation circuit 32, output signals i1 and i2 of shift pattern generation circuit 14, output signal j of mask pattern generation circuit 15 and pattern synthesis circuit The sixteenth first and second output signals k <0> and k <1> are the same as those in the thirteenth embodiment, and therefore a description thereof will be omitted. The operation of the pattern selection circuit 7 will be mainly described in the fourteenth embodiment. The operation of the sequence signal generation circuit will be described.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 28), the mode signal d
Is "0", the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 16 and outputs it as the sequence signal l. Next, in the second count cycle (count values # 1 to # 14 on the right side in FIG. 28; count values # 15 to # 31 are omitted), the mode signal d becomes “1”, so the pattern selection circuit 7 The second output signal k <1> of the pattern synthesis circuit 16 is selected and output as the sequence signal l. Therefore, the sequence signal 1 has a waveform as shown in 1 of FIG.

The sequence signal generation circuit of the fourteenth embodiment has a feature that the sequence signal can be selected by a mode signal in addition to the features of the circuit of the thirteenth embodiment.
FIG. 15 is a block diagram showing a sequence signal generation circuit according to a fifteenth embodiment of the present invention. The configuration of the sequence signal generation circuit according to the fifteenth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the fifteenth embodiment is the counter circuit 1, the random pattern generation circuit 42,
It is composed of a toggle pattern generation circuit 3, a shift pattern generation circuit 4, and a pattern synthesis circuit 26. Since the counter circuit 1 is the same as that of the first embodiment, the description of its configuration and operation will be omitted.

The random pattern generation circuit 42 of the fifteenth embodiment has a count output value f <
4. ． 0> for inputting the signal lines 351 to 359 and the count output value f <4. ． 0> to inverters 301-309
The signal lines 361 to 369 which are inverted and transmitted at are used as input signal lines. The random pattern generation circuit 42 is shown in FIG.
The first and second 5-input AND circuits 311, 313 and 2-input OR of the random pattern generation circuit 2 shown in FIG.
It has a circuit 319. The 2-input OR circuit 319 outputs the first output signal g1. As described in the description of FIG. 46, the first output signal g1 has the count output value f <
4. ． When 0> = “00010” (count value is # 2
, And the count output value f <4. ． 0> = "01
The output signal becomes "1" only when it is 100 "(when the count value is # 12). The random pattern generation circuit 42 further includes the third and fourth 5-input AND circuits 32.
7 and 329. Third 5-input AND circuit 32
7 inputs are connected to signal lines 361, 363, 365, 357 and 359. Therefore, the third 5-input AN
The second output signal g2 output from the D circuit 327 is the count output value f <4. ． The output signal becomes "1" only when 0> = "11000" (when the count value is # 24). The input of the fourth 5-input AND circuit 329 is the signal line 3
61, 363, 355, 357 and 369. Therefore, the third output signal g3 output from the fourth 5-input AND circuit 329 is the count output value f <
4. ． When 0> = "01100" (the count value is # 1
Only when (2), the output signal becomes "1". The first output signal g generated by the random pattern generation circuit 42
1 is the toggle pattern synthesis circuit 3 and the second output signal g
2 is input to the pattern synthesis circuit 26, and the third output signal g3 is input to the shift pattern generation circuit 4.

The toggle pattern synthesizing circuit 3 is the same as that in the first embodiment, and the input signal g1 and the output signal h are also the same as those in the first embodiment, so that the description thereof will be omitted. The output signal h of the toggle pattern synthesis circuit 3 is input to the pattern synthesis circuit 16.

Since the shift pattern generating circuit 4 has the same circuit configuration as that of the fifth embodiment, its explanation is omitted. The input / output signals of the shift pattern generation circuit 4 of this embodiment are different from those of the shift pattern generation circuit 4 of the fifth embodiment, which will be described in the description of the operation. Shift pattern generation circuit 4
Output signals i <0> and i <1> of the pattern synthesis circuit 26
Entered in.

FIG. 48 is a circuit diagram showing a circuit configuration of the pattern synthesis circuit 26. The pattern synthesis circuit 26 has 3 inputs O
It is composed of an R circuit 607 and a 2-input OR circuit 609. The second output signal g2 generated by the random pattern generation circuit 42 is applied to the first input of the 3-input OR circuit 607. The first output signal i <0> of the shift pattern generation circuit 4 is applied to the second input of the 3-input OR circuit 607. Third input of 3-input OR circuit 607 and 2-input O
The output signal h of the toggle pattern synthesis circuit 3 is commonly supplied to the first input of the R circuit 609. The second output signal i <1> of the shift pattern generation circuit 4 is applied to the second input of the 2-input OR circuit 609. 3-input OR circuit 6
From the output of 07, the first output signal k <0>
A second output signal k <1> is output from the output of the R circuit 609.

FIG. 29 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG.
The operation of the sequence signal generation circuit of the fifth embodiment will be described with reference to FIG. In the sequence signal generation circuit of the fifteenth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r = 2, t = 2.

Output signal f <4 ... 0 of counter circuit 1
>, The clock signal a2 is the same as that of the eleventh embodiment, and therefore its explanation is omitted. As mentioned above, random
The first output signal g1 of the pattern generation circuit 42 is the count output value f <4. ． 0> = “00010” (when the count value is # 2) and the count output value f <4. ． 0
> = “01100” (when the count value is # 12), the output signal becomes “1”, and the second output signal g2 has the count output value f <4. ． 0> = “11000”
Only (when the count value is # 24), the output signal becomes "1", and the third output signal g3 has the count output value f <4. ． The output signal is "1" only when 0> = "01100" (when the count value is # 12).

The toggle pattern synthesizing circuit 3 is the same as that of the first embodiment, and the output signal h is also the same as that of the first embodiment (the signal of the period "1" between the count values # 2 and # 11). Therefore, the description thereof is omitted.

Next, the operation of the shift pattern generating circuit 4 will be described with reference to FIG. A signal g3 of "1" is input to the input D of the count value # 12 of the first D flip-flop 701 of the shift pattern generation circuit 4. Next, count value # 12 and count value # 1
Second input to clock input C between
Of the clock signal a2 rises from "0" to "1".
At this time, the first D flip-flop 701 takes in the signal g3 of "1" and outputs it as the output signal i <0>. Next, when the second clock signal a2 rises again from "0" to "1" between the count values # 16 and # 17, the first D flip-flop 701 takes in the signal g3 of "0", Is output as an output signal i <0>. On the other hand, in the second D flip-flop 703, “
1 "signal i <0> is taken in and output as output signal i <1
Output as>. The second D flip-flop 703 changes the output signal i <1> from “1” to “1” when the second clock signal a2 rises from “0” to “1” between the count value # 20 and the count value # 21. Fall to 0 ".

The pattern synthesizing circuit 26 ORs the second output signal g2 of the random pattern generating circuit 42, the output signal i <0> of the shift pattern generating circuit 4 and the output signal h of the toggle pattern synthesizing circuit 3. The output signal i <1> of the shift pattern generation circuit 4 and the output signal h of the toggle pattern synthesis circuit 3 are used as the first output signal k <0>.
And a logical sum signal of and is output as a second output signal k <1>. The first and second output signals k <0>, k <1>
Is the sequence signal k of the sequence signal generation circuit of the fifteenth embodiment.

The sequence signal generation circuit of the fifteenth embodiment is characterized in that it can generate a sequence signal by combining the signals generated by the random pattern generation circuit, the toggle pattern generation circuit, and the shift pattern generation circuit.

FIG. 16 is a block diagram showing a sequence signal generation circuit according to the 16th embodiment of the present invention. The configuration of the sequence signal generation circuit according to the 16th embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the sixteenth embodiment is the counter circuit 1, the random pattern generation circuit 42,
Toggle pattern generation circuit 3, shift pattern generation circuit 4, pattern synthesis circuit 26 and pattern selection circuit 7
Composed of and. The sequence signal generation circuit of the 16th embodiment has a configuration in which the pattern selection circuit 7 is connected to the pattern synthesis circuit 26 of the sequence signal generation circuit of the 15th embodiment. Therefore, the counter circuit 1, the random pattern generation circuit 42, the toggle pattern generation circuit 3, the shift pattern generation circuit 4 and the pattern synthesis circuit 26 of the sequence signal generation circuit of the 16th embodiment are the same as those of the 15th embodiment. Therefore, the description of the configuration and the operation thereof will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generation circuit of the sixteenth embodiment has the first and second output signals k <0 of the pattern synthesis circuit 26.
>, K <1> are selected by the pattern selection circuit 7 and output as the sequence signal l.

FIG. 29 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG.
The operation of the sequence signal generation circuit of the sixth embodiment will be described with reference to FIG. In the sequence signal generation circuit of the 16th embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r = 2, t = 2, u = 1.

Output signal f of counter circuit 1 f <4 ... 0
>, The first, second and third output signals g1, g2, g3 of the random pattern generation circuit 42, the output signal h of the toggle pattern generation circuit 3, the shift pattern generation circuit 4
Output signals i <0>, i <1> and the first and second output signals k <0>, k <1> of the pattern synthesizing circuit 26 are the same as those in the fifteenth embodiment, and the description thereof will be omitted. Then, the operation of the sequence signal generation circuit of the sixteenth embodiment will be described focusing on the operation of the pattern selection circuit 7.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 29), the mode signal d
Is “0”, the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 26 and outputs it as the sequence signal l. Next, in the second count cycle (count values # 1 to # 14 on the right side in FIG. 29; count values # 15 to # 31 are omitted), the mode signal d becomes “1”, so the pattern selection circuit 7 The second output signal k <1> of the pattern synthesis circuit 26 is selected and output as the sequence signal l. Therefore, the sequence signal l has a waveform as shown by l in FIG.

The sequence signal generation circuit of the 16th embodiment is characterized in that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the 15th embodiment.
FIG. 17 is a block diagram showing a sequence signal generation circuit according to a 17th embodiment of the present invention. The configuration of the sequence signal generation circuit according to the 17th embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the seventeenth embodiment is the counter circuit 1, the random pattern generation circuit 42,
It is composed of a toggle pattern generation circuit 3, a shift pattern generation circuit 4, a mask pattern generation circuit 5 and a pattern synthesis circuit 16. The counter circuit 1, the random pattern generation circuit 42, the toggle pattern generation circuit 3, and the shift pattern generation circuit 4 are the same as those in the fifteenth embodiment, and therefore the description of the configuration, operation, etc. will be omitted.

In the seventeenth embodiment, the second output of the shift pattern generation circuit 4 is input to the mask pattern generation circuit 5. In addition, the first of the shift pattern generation circuit 4
The output is floating. The output of the mask pattern generation circuit 5 is the output of the toggle pattern generation circuit 3 and the random pattern generation circuit 4
It is input to the pattern synthesis circuit 16 together with the second output of No. 2.

The mask / pattern generating circuit 5 and the pattern synthesizing circuit 16 have the same circuit configurations as those of the ninth and thirteenth embodiments, respectively, and therefore their explanations are omitted.

FIG. 30 is a timing chart showing the operation of the sequence signal generation circuit shown in FIG.
The operation of the sequence signal generation circuit of the seventh embodiment will be described with reference to FIG. In the sequence signal generation circuit of the 17th embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r = 1, s = 1, t = 2.

As described in the fifteenth embodiment, the second output signal g2 of the random pattern generation circuit 32 is the count output value f <4. ． The output signal becomes "1" only when 0> = "11000" (when the count value is # 24). The output signal h of the toggle pattern synthesis circuit 3 becomes a signal of "1" during the period of the count value # 2 to # 11. The output signal i <0> of the shift pattern generation circuit 4 is a signal of “1” during the period of count values # 13 to # 15, and the output signal i <1> is the period of the count value # 17 to # 20 ”.
1 "signal.

The mask pattern generation circuit 5 has the circuit configuration shown in FIG. 42. In this embodiment, the AND circuit 8 is used.
01 is used, and the AND circuit 803 is not used. That is, the mask signal e is applied to the first input of the AND circuit 801.
The output signal i of the shift pattern generation circuit 4 is input to the second input.
<1> is given. The mask signal e and the output signal i of the shift pattern generation circuit 4 are output from the output of the AND circuit 801.
An output signal j that is a logical product signal of <1> is output.

The pattern synthesis circuit 16 has the circuit configuration shown in FIG. 46, but the input / output signals are different. In the pattern synthesizing circuit 16 of this embodiment, the logical sum signal of the second output signal g2 of the random pattern generating circuit 42 and the output signal h of the toggle pattern synthesizing circuit 3 is converted into the first output signal k <0.
>, A logical sum signal of the output signal h of the toggle pattern synthesis circuit 3 and the output signal j of the mask pattern generation circuit 5 is output as a second output signal k <1>. This first
The second output signals k <0> and k <1> are the sequence signal k of the sequence signal generation circuit of the seventeenth embodiment.

The sequence signal generation circuit of the seventeenth embodiment is characterized in that it can generate a sequence signal by combining the signals generated by the random pattern generation circuit, the toggle pattern generation circuit, and the mask pattern generation circuit.

FIG. 18 is a block diagram showing a sequence signal generation circuit according to the 18th embodiment of the present invention. The configuration of the sequence signal generation circuit according to the 18th embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the eighteenth embodiment is the counter circuit 1, the random pattern generation circuit 42,
It includes a toggle pattern generation circuit 3, a shift pattern generation circuit 4, a mask pattern generation circuit 5, a pattern synthesis circuit 16 and a pattern selection circuit 7. First
The sequence signal generation circuit of the eighth embodiment has a configuration in which the pattern selection circuit 7 is connected to the pattern synthesis circuit 16 of the sequence signal generation circuit of the seventeenth embodiment. Therefore, the counter circuit 1, the random pattern generation circuit 42, the toggle pattern generation circuit 3, the shift pattern generation circuit 4, of the sequence signal generation circuit of the eighteenth embodiment,
Mask / pattern generation circuit 5 and pattern synthesis circuit 1
Since No. 6 is the same as that of the seventeenth embodiment, the description of its configuration and operation will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generation circuit of the eighteenth embodiment is the first and second output signals k of the pattern synthesis circuit 16.
<0> and k <1> are selected by the pattern selection circuit 7 and output as the sequence signal l.

FIG. 30 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG.
The operation of the sequence signal generation circuit of the eighth embodiment will be described with reference to FIG. In the sequence signal generation circuit of the eighteenth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r = 1, s = 1, t = 2, u = 1.

Output signal f <4 ... 0 of counter circuit 1
>, The first, second and third output signals g1, g2, g3 of the random pattern generation circuit 42, the output signal h of the toggle pattern generation circuit 3, the shift pattern generation circuit 4
Output signals i <0>, i <1>, a mask signal e, an output signal j of the mask / pattern generation circuit 5 and first and second output signals k <0>, k <1 of the pattern synthesis circuit 16.
Since> is the same as that of the 17th embodiment, its description is omitted, and the operation of the sequence signal generation circuit of the 18th embodiment will be described focusing on the operation of the pattern selection circuit 7.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 30), the mode signal d
Is "0", the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 16 and outputs it as the sequence signal l. Next, in the second count cycle (count values # 1 to # 14 on the right side of FIG. 30; count values # 15 to # 31 are omitted), the mode signal d becomes “1”, so the pattern selection circuit 7 The second output signal k <1> of the pattern synthesis circuit 16 is selected and output as the sequence signal l. Therefore, the sequence signal l has a waveform as shown by l in FIG.

The sequence signal generation circuit of the eighteenth embodiment is characterized in that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the seventeenth embodiment.
FIG. 19 is a block diagram showing a sequence signal generation circuit according to the 19th embodiment of the present invention. The configuration of the sequence signal generation circuit according to the nineteenth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the nineteenth embodiment is the counter circuit 1, the random pattern generation circuit 42,
It is composed of a toggle pattern generation circuit 3, a shift pattern generation circuit 4, a mask pattern generation circuit 5 and a pattern synthesis circuit 26. The counter circuit 1, the random pattern generation circuit 42, the toggle pattern generation circuit 3, the shift pattern generation circuit 4, and the mask pattern generation circuit 5 are the same as those in the seventeenth embodiment, and therefore the description of the configuration, operation, etc. will be given. Is omitted.

In the nineteenth embodiment, the first output of the shift pattern generation circuit 4 is input to the pattern synthesis circuit 26. The second output of the shift pattern generation circuit 4 is connected to the mask pattern generation circuit 5 as in the seventeenth embodiment. Therefore, the output of the toggle pattern generation circuit 3, the second output of the random pattern generation circuit 42, the first output of the shift pattern generation circuit 4, and the output of the mask pattern generation circuit 5 are connected to the pattern synthesis circuit 26. ing.

The pattern synthesis circuit 26 has the same circuit configuration as that of the fifteenth embodiment, but the connection is different. 19th
The pattern synthesizing circuit 26 of this embodiment has two OR circuits 607 and 609 as in FIG. The input of the OR circuit 607 is the output of the toggle pattern generation circuit 3, the random
The second output of the pattern generation circuit 42 and the first output of the shift pattern generation circuit 4 are connected (similar to FIG. 48). The OR circuit 609 includes a toggle pattern generation circuit 3
And the output of the mask pattern generation circuit 5 are connected.

FIG. 31 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG.
The operation of the sequence signal generation circuit of the ninth embodiment will be described with reference to FIG. In the sequence signal generation circuit of the 17th embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r1 = 1, r2 = 1, s = 1, t = 2.

As described in the seventeenth embodiment, the second output signal g2 of the random pattern generation circuit 32 has the count output value f <4. ． The output signal becomes "1" only when 0> = "11000" (when the count value is # 24). The output signal h of the toggle pattern synthesis circuit 3 becomes a signal of "1" during the period of the count value # 2 to # 11. Further, the output signal i <0> of the shift pattern generation circuit 4
(I1) is a signal of "1" during the period of count values # 13 to # 15, and the output signal i <1> (i2) is a signal of "1" during the period of count values # 17 to # 20.

An output signal j, which is a logical product signal of the mask signal e and the output signal i <0> of the shift pattern generation circuit 4, is output from the output of the mask pattern generation circuit 5.

The pattern synthesizing circuit 26 ORs the second output signal g2 of the random pattern generating circuit 42, the output signal i <0> of the shift pattern generating circuit 4 and the output signal h of the toggle pattern synthesizing circuit 3. The signal is the first output signal k <0>, and the logical sum signal of the output signal h of the toggle pattern synthesis circuit 3 and the output signal j of the mask pattern generation circuit 5 is the second output signal k <1>. Output. The first and second output signals k <0>, k <1>
Is the sequence signal k of the sequence signal generation circuit of the 19th embodiment.

The sequence signal generation circuit of the nineteenth embodiment generates a sequence signal by combining the signals generated by the random pattern generation circuit, the toggle pattern generation circuit, the shift pattern generation circuit and the mask pattern generation circuit. There is a feature that can be done.

FIG. 20 is a block diagram showing a sequence signal generation circuit according to the twentieth embodiment of the present invention. The configuration of the sequence signal generation circuit according to the twentieth embodiment will be described below with reference to FIG.

The sequence signal generation circuit of the twentieth embodiment is the counter circuit 1, the random pattern generation circuit 42,
It comprises a toggle pattern generation circuit 3, a shift pattern generation circuit 4, a mask pattern generation circuit 5, a pattern synthesis circuit 26 and a pattern selection circuit 7. Second
The sequence signal generation circuit of the 0th embodiment has a configuration in which the pattern selection circuit 7 is connected to the pattern synthesis circuit 26 of the sequence signal generation circuit of the 19th embodiment. Therefore, the counter circuit 1, the random pattern generation circuit 42, the toggle pattern generation circuit 3, the shift pattern generation circuit 4, of the sequence signal generation circuit of the twentieth embodiment,
Mask / pattern generation circuit 5 and pattern synthesis circuit 2
Since No. 6 is the same as that of the nineteenth embodiment, the description of its configuration and operation will be omitted. Further, since the pattern selection circuit 7 is the same as that of the second embodiment, the description of its configuration and operation will be omitted. The sequence signal generation circuit of the twentieth embodiment is the first and second output signals k of the pattern synthesis circuit 26.
<0> and k <1> are selected by the pattern selection circuit 7 and output as the sequence signal l.

FIG. 31 is a timing chart showing the operation of the sequence signal generating circuit shown in FIG. 20.
The operation of the sequence signal generation circuit of the No. 0 embodiment will be described with reference to FIG. In the sequence signal generation circuit of the twentieth embodiment, m1 = 5, n = 5, p1 = 1, p2 = 1, p3
= 1, q = 1, r1 = 1, r2 = 1, s = 1, t = 2
u = 1.

Output signal f <4 ... 0 of counter circuit 1
>, The first, second and third output signals g1, g2, g3 of the random pattern generation circuit 42, the output signal h of the toggle pattern generation circuit 3, the shift pattern generation circuit 4
Output signals i <0> (i1), i <1> (i2), the mask signal e, the output signal j of the mask / pattern generation circuit 5 and the first and second output signals k <0 of the pattern synthesis circuit 26. > And k <1> are the same as those in the nineteenth embodiment, the description thereof will be omitted, and the operation of the sequence signal generation circuit of the twentieth embodiment will be described focusing on the operation of the pattern selection circuit 7.

In the first count cycle (count values # 1 to # 31 on the left side of FIG. 31), the mode signal d
Is “0”, the pattern selection circuit 7 selects the first output signal k <0> of the pattern synthesis circuit 26 and outputs it as the sequence signal l. Next, in the second count cycle (count values # 1 to # 14 on the right side of FIG. 31; count values # 15 to # 31 are omitted), the mode signal d becomes “1”, so that the pattern selection circuit 7 The second output signal k <1> of the pattern synthesis circuit 16 is selected and output as the sequence signal l. Therefore, the sequence signal l has a waveform as shown by l in FIG.

The sequence signal generation circuit of the twentieth embodiment has the feature that the sequence signal can be selected by the mode signal in addition to the features of the circuit of the nineteenth embodiment.

[0170]

As described in detail above, according to the sequence signal generating circuit of the present invention, a desired sequence signal can be obtained only by selecting an optimum circuit configuration in accordance with a sequence signal generated by dividing the circuit configuration into blocks. Is obtained.

Further, according to the sequence signal generation circuit of the present invention, since the initial value signal can be set from the outside, a flexible sequence signal can be generated.

Further, according to the sequence signal generation circuit of the present invention, it is possible to select the sequence signal by setting the mode signal from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a block diagram of a second embodiment.

FIG. 3 is a block diagram of a third embodiment.

FIG. 4 is a block diagram of a fourth embodiment.

FIG. 5 is a block diagram of a fifth embodiment.

FIG. 6 is a block diagram of a sixth embodiment.

FIG. 7 is a block diagram of a seventh embodiment.

FIG. 8 is a block diagram of an eighth embodiment.

FIG. 9 is a block diagram of a ninth embodiment.

FIG. 10 is a block diagram of a tenth embodiment.

FIG. 11 is a block diagram of an eleventh embodiment.

FIG. 12 is a block diagram of a twelfth embodiment.

FIG. 13 is a block diagram of a thirteenth embodiment.

FIG. 14 is a block diagram of a fourteenth embodiment.

FIG. 15 is a block diagram of a fifteenth embodiment.

FIG. 16 is a block diagram of a sixteenth embodiment.

FIG. 17 is a block diagram of a seventeenth embodiment.

FIG. 18 is a block diagram of an eighteenth embodiment.

FIG. 19 is a block diagram of a nineteenth embodiment.

FIG. 20 is a block diagram of a twentieth embodiment.

FIG. 21 is a timing diagram showing the operation of the circuits of FIGS. 1 and 2.

FIG. 22 is a timing diagram showing the operation of the circuits of FIGS. 1 and 2.

FIG. 23 is a timing diagram showing the operation of the circuits of FIGS. 3 and 4.

FIG. 24 is a timing diagram showing the operation of the circuits of FIGS. 5 and 6;

FIG. 25 is a timing diagram showing the operation of the circuits of FIGS. 7 and 8.

FIG. 26 is a timing diagram illustrating the operation of the circuits of FIGS. 9 and 10.

FIG. 27 is a timing diagram showing the operation of the circuits of FIGS. 11 and 12.

FIG. 28 is a timing diagram showing the operation of the circuits of FIGS. 13 and 14.

FIG. 29 is a timing diagram showing the operation of the circuits of FIGS. 15 and 16.

FIG. 30 is a timing diagram showing the operation of the circuits of FIGS. 17 and 18.

FIG. 31 is a timing diagram showing the operation of the circuits of FIGS. 19 and 20.

FIG. 32 is a circuit diagram of a counter circuit.

FIG. 33 is a circuit diagram of a synchronous 1-bit counter.

FIG. 34 is a circuit diagram of a first random pattern generation circuit.

FIG. 35 is a circuit diagram of a toggle pattern generation circuit.

FIG. 36 is a circuit diagram of another toggle pattern generation circuit.

FIG. 37 is a circuit diagram of a pattern selection circuit.

FIG. 38 is a circuit diagram of a pattern synthesis circuit.

FIG. 39 is a circuit diagram of a second random pattern generation circuit.

FIG. 40 is a circuit diagram of a shift pattern generation circuit.

FIG. 41 is a circuit diagram of a third random pattern generation circuit.

FIG. 42 is a circuit diagram of a mask pattern generation circuit.

FIG. 43 is a circuit diagram of a fourth random pattern generation circuit.

FIG. 44 is a circuit diagram of another shift pattern generation circuit.

FIG. 45 is a circuit diagram of another mask pattern generation circuit.

FIG. 46 is a circuit diagram of another pattern synthesis circuit.

FIG. 47 is a circuit diagram of a fifth random pattern generation circuit.

FIG. 48 is a circuit diagram of still another pattern synthesis circuit.

[Description of Reference Signs] 1 counter circuit 2 random pattern generation circuit 3 toggle pattern generation circuit 4 shift pattern generation circuit 5 mask pattern generation circuit 6 pattern synthesis circuit 7 pattern selection circuit a1 first clock signal a2 second Clock signal b1 First initial value signal b2 Second initial value signal c Reset signal d Mode signal f Output signal of counter circuit g Output signal of random pattern generation circuit g1 First output signal of random pattern generation circuit g2 Second output signal of random pattern generation circuit g3 Third output signal of random pattern generation circuit h Output signal of toggle pattern generation circuit i Output signal of shift pattern generation circuit i1 First of shift pattern generation circuit Output signal of the second output of the shift pattern generation circuit i2 No. j Output signal of mask / pattern generating circuit k Output signal of pattern synthesizing circuit l Output signal of pattern selecting circuit m1 Signal b1 bit length m2 Signal b2 bit length n Signal f bit length p Signal g bit length p1 signal g1 bit length p2 signal g2 bit length p3 signal g3 bit length q signal h bit length r signal i bit length r1 signal i1 bit length r2 signal i2 bit length s signal j bit length r signal k Bit length u Bit length of signal l v Bit length of signal d

[Procedure amendment]

[Submission date] April 15, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

The counter circuit generates a signal representing the count value from the clock signal. Random pattern generation circuit, toggle pattern generation circuit, shift pattern generation circuit,
The pattern synthesis circuit and the pattern selection circuit generate / receive an input signal, for example, a signal representing a count value or another circuit.
A signal different from the input signal is generated / outputted from the output signal or the like based on the control signal or the like. By combining these circuits, a sequence signal generation circuit that generates a desired sequence signal can be formed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

Returning to FIG. 1, the description will be continued. The random pattern output signal g <0> generated by the random pattern generation circuit 2 is input to the toggle pattern generation circuit 3. In the toggle pattern generation circuit 3, the random pattern is generated within one count cycle (count value is between # 0 and # 31).
The random pattern output signal g <0> generated by the pattern generation circuit 2 functions to connect the two rising edges of the pulse of "1".

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

FIG. 35 is a circuit diagram showing the toggle pattern generation circuit 3 of the first embodiment. The toggle pattern generation circuit 3 includes D flip-flops with reset 401, XO
It is composed of an R circuit 403 and an inverter 404. The reset signal c common to the counter circuit 1 is input to the reset input R of the D flip-flop 401, and the random pattern output signal g <0> generated by the random pattern generation circuit 2 is input to the clock input C. It The first input of the XOR circuit 403 is connected to the output Q of the D flip-flop 401, and the second input is supplied with the second initial value signal b2. Similarly to the first initial value signal b1, the second initial value signal b2 is an m2-bit binary signal b2 <0.
, B2 <1>, ..., B2 <m>, but in the first embodiment, only the 1-bit binary signal b2 <0> is used. The signal output from the output of the XOR circuit 403 is the output signal h of the toggle pattern generation circuit 3 (the output signal h is composed of q bits, but in this embodiment, 1).
It is a binary signal h <0> of bits). The output Q of the D flip-flop 401 is connected to the input D via the inverter 404.

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At the time of reset (when the reset signal c is "1"), the output of the D flip-flop 401 is "0". Since the second initial value signal b2 <0> is “0”, the inputs of the XOR circuit 403 are “0” and “0”, and the output thereof is the output signal h of the toggle pattern generation circuit 3. <0> also becomes “0”.

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The sequence signal generation circuit of the second embodiment comprises a counter circuit 1, a random pattern generation circuit 2, a toggle pattern generation circuit 13 and a pattern selection circuit 7. The random pattern generation circuit 2 is connected to the output of the counter circuit 1, the toggle pattern generation circuit 13 is connected to the output of the random pattern generation circuit 2, and the pattern selection circuit 7 is connected to the toggle pattern generation circuit 1.
3 output. Since the counter circuit 1 is the same as that of the first embodiment, the description of its configuration and operation will be omitted. Although the circuit configuration of the random pattern generation circuit 2 is the same as that of the first embodiment, the second output signal g <1> of the random pattern generation circuit 2 is also used in the second embodiment. The output of the OR circuit 321 is connected to the toggle pattern generation circuit 13. The circuit configuration of the toggle pattern generation circuit 13 is shown in FIG. The toggle pattern generation circuit 13 includes D flip-flops with reset 401, 405, XOR circuits 403, 407, and inverters 404, 408, 409.
Since the D flip-flop 401, the XOR circuit 403, and the inverter 404 are the same as those described above, their description will be omitted. The reset input c of the counter circuit 1 is input to the reset input R of the D flip-flop 405, and the random pattern output signal g <1> generated by the random pattern generation circuit 2 is input to the clock input C. It The first input of the XOR circuit 407 is connected to the output Q of the D flip-flop 405, and the second input is supplied with the second initial value signal b2 <1>. The output of the XOR circuit 407 is connected to the input of the inverter 409. Inverter 4
The signal output from the output of 09 becomes the output signal h <1> of the toggle pattern generation circuit 13. The output Q of the D flip-flop is connected to the input D via the inverter 408. The toggle pattern generation circuit 13 outputs the output signals g <0> and g <1> of the random pattern generation circuit 12.
And output signals h <0> and h <1> from the second initial value signals b2 <0> and b2 <1>.

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[Figure 8]

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FIG. 34

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FIG. 35

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FIG. 36

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masato Yamazaki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (20)

[Claims] 1. A counter which inputs a clock signal and outputs a count value signal based on this clock signal, and a first state and a second state which inputs the count value signal and based on this count value signal A circuit for generating and outputting a random pattern output signal having any of the above, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and the random pattern output signal is otherwise set to the first state. A random pattern generation circuit that puts the pattern output signal in a second state; and a random pattern output signal that is input to the first state and the second state based on the random pattern output signal.
A circuit for generating and outputting a sequence signal having any one of the above states, wherein the random pattern output signal is the first
Of the sequence in response to any one of a change of the state of the random pattern output signal from the second state, a change from the second state to the first state, or a change of the state of the random pattern output signal. And a toggle pattern generation circuit that changes the state of a signal. 2. A counter that inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter that inputs the count value signal of a plurality of bits and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting a multi-bit random pattern output signal having any one of the above states, and setting the random pattern output signal to the first state only when the count value signal shows a specific value, and otherwise If the random pattern output signal is in the second state,
A pattern generation circuit, and a multi-bit toggle pattern which receives the multi-bit random pattern output signal and has one of a first state and a second state based on the multi-bit random pattern output signal A circuit for generating and outputting an output signal, wherein the random pattern output signal changes from a first state to a second state, changes from a second state to a first state, or the random pattern output. A toggle pattern generation circuit that changes the state of the toggle pattern output signal in response to any one change when the state of the signal changes, and the toggle pattern output signal and the control signal of the plurality of bits are input. , In response to the control signal, one of the toggle pattern output signals of the plurality of bits of the toggle pattern output signal, Sequence signal generating circuit, characterized in that it comprises a pattern selection circuit-option and outputs it as a sequence signal. 3. A counter which inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter which inputs the count value signal of a plurality of bits, and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting first and second random pattern output signals each having one of the states
A random pattern generation circuit that puts the random pattern output signal into a first state only when the count value signal shows a specific value, and otherwise puts the random pattern output signal into a second state; A circuit for inputting a first random pattern output signal, and generating and outputting a toggle pattern output signal having either a first state or a second state based on the first random pattern output signal. , When the first random pattern output signal changes from the first state to the second state, when changing from the second state to the first state, or the state of the first random pattern output signal A toggle pattern generation circuit that changes the state of the toggle pattern output signal in response to any one of the changes, and the second lander. A sequence signal having a pattern output signal and the toggle pattern output signal, logically operating these input signals, and outputting the signal after the operation as a sequence signal Generation circuit. 4. A counter which inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter which inputs the count value signal of a plurality of bits and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting a plurality of bits of first and second random pattern output signals, each of which has one of the above states, and outputs the random pattern output signal to the first and second random pattern output signals only when the count value signal shows a specific value. A random pattern generation circuit which sets the random pattern output signal to the first state and otherwise sets the random pattern output signal to the second state; and inputs the plurality of bits of the first random pattern output signal, A circuit for generating and outputting a multi-bit toggle pattern output signal having one of a first state and a second state based on one random pattern output signal, wherein the first random pattern output signal is When changing from the first state to the second state,
Changing the state of the toggle pattern output signal in response to any one of a change from a second state to a first state or a change in the state of the first random pattern output signal. A toggle pattern generation circuit, the plurality of bits of the second random pattern output signal and the plurality of bits of the toggle pattern output signal are input, the input signals are logically calculated, and the signal after the calculation is output. A pattern synthesizing circuit for outputting as a pattern synthesizing signal and the pattern synthesizing signal of a plurality of bits and a control signal are inputted, and in response to the control signal, one pattern synthesizing signal is selected from the plurality of bit pattern synthesizing signals. And a pattern selection circuit for outputting it as a sequence signal. 5. A counter that inputs a clock signal and outputs a count value signal based on this clock signal, and a first state and a second state that inputs the count value signal and based on this count value signal A circuit for generating and outputting a random pattern output signal having any of the above, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and the random pattern output signal is otherwise set to the first state. A random pattern generation circuit that puts a pattern output signal in a second state, and a sequence signal that has the same state as the random pattern output signal based on the control signal, to which the random pattern output signal and the control signal are input. And a shift pattern generating circuit for generating and outputting the sequence signal generating circuit. 6. A counter that inputs a clock signal and outputs a count value signal based on this clock signal, and a first state and a second state that inputs the count value signal and based on this count value signal A circuit for generating and outputting a random pattern output signal having any of the above, the random pattern output signal being in the first state only when the count value signal shows a specific value, and the random pattern output signal otherwise being the random state. A random pattern generation circuit that puts the pattern output signal in the second state, and the random pattern output signal and the first control signal as input, and the random pattern output signal based on the first control signal A shift pattern signal having a plurality of bits having the same state and different delay times is generated and output in response to the change of the first control signal. A shift pattern generating circuit for inputting the shift pattern signal of a plurality of bits and a second control signal, and shifting one of the shift pattern signals of a plurality of bits in response to the second control signal. A sequence signal generation circuit having a pattern selection circuit that selects a pattern signal and outputs it as a sequence signal. 7. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal, and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting first and second random pattern output signals each having one of the states
A random pattern generation circuit that puts the random pattern output signal into a first state only when the count value signal shows a specific value, and otherwise puts the random pattern output signal into a second state; A shift pattern generation circuit for inputting a first random pattern output signal and a control signal, and for generating and outputting a shift pattern signal having the same state as that of the first random pattern output signal based on the control signal; A pattern synthesizing circuit for inputting the second random pattern output signal and the shift pattern signal, logically calculating the input signals, and outputting the calculated signal as a sequence signal. A characteristic sequence signal generation circuit. 8. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal; and a counter for inputting the count value signal of a plurality of bits, and based on the count value signal of the plurality of bits. First state and second
A circuit for generating and outputting a plurality of bits of the first and second random pattern output signals, each of which has one of the above states, and the random pattern output signal A random pattern generation circuit that puts the random pattern output signal into the state 1 and otherwise puts the random pattern output signal into the second state; and inputs the random pattern output signal of the plurality of bits and the first control signal, Generating and outputting a shift pattern signal having a plurality of bits having the same state as that of the random pattern output signal of a plurality of bits based on one control signal and having a different delay time in response to a change of the first control signal. A shift pattern generating circuit, a plurality of bits of the second random pattern output signal, and the plurality of bits of the shift pattern generating circuit. Enter the over tone signal,
A pattern synthesizing circuit for logically operating each of these input signals and outputting a plurality of bit signals after the operation as a pattern synthesizing signal, and inputting the plurality of bit pattern synthesizing signals and a second control signal, A sequence signal generation circuit, comprising: a pattern selection circuit that selects one pattern synthesis signal from the plurality of bits of the pattern synthesis signal and outputs it as a sequence signal in response to a second control signal. . 9. A counter that inputs a clock signal and outputs a count value signal based on this clock signal, and a first state and a second state that inputs the count value signal and based on this count value signal A circuit for generating and outputting a random pattern output signal having any of the above, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and the random pattern output signal is otherwise set to the first state. A random pattern generation circuit that puts the pattern output signal in the second state, and the random pattern output signal and the first control signal are input, and the same as the random pattern output signal based on the first control signal. A shift pattern generation circuit for generating and outputting a shift pattern signal having a state, and the shift pattern signal and First state and second
A second control signal having any one of the two states is input, and when the second control signal is in the first state, the same signal as the shift pattern signal and the second control signal are in the second state. And a mask pattern generation circuit that outputs a signal fixed to either the first state or the second state as a sequence signal in the state of 1). 10. A counter which inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter which inputs the count value signal of a plurality of bits and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting a multi-bit random pattern output signal having any one of the above states, and setting the random pattern output signal to the first state only when the count value signal shows a specific value, and otherwise If the random pattern output signal is in the second state,
A pattern generation circuit, which inputs the random pattern output signal of a plurality of bits and a first control signal, and has the same state as the random pattern output signal of a plurality of bits based on the first control signal; A shift pattern generation circuit for generating and outputting a shift pattern signal of a plurality of bits having different delay times in response to a change of a first control signal, the shift pattern signal of the plurality of bits, a first state and a second state A second control signal having any one of the states described above is input, and when the second control signal is in the first state, the same multi-bit signal as the multi-bit shift pattern signal is applied to the second control signal. And a mask pattern generation circuit for outputting a signal fixed to either the first state or the second state as a mask pattern signal when the control signal of is in the second state. The mask pattern signal of a plurality of bits and a third control signal are input, and one mask pattern signal of the mask pattern signals of a plurality of bits is selected in response to the third control signal. And a pattern selection circuit for outputting as a sequence signal. 11. A counter which inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter which inputs the count value signal of a plurality of bits and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting first and second random pattern output signals each having one of the states
A random pattern generation circuit that puts the random pattern output signal into a first state only when the count value signal shows a specific value, and otherwise puts the random pattern output signal into a second state; A first random pattern output signal and a first control signal are input, and a shift pattern signal having the same state as the first random pattern output signal is generated and output based on the first control signal. A shift pattern generation circuit, the shift pattern signal, a first state and a second state
A second control signal having any one of the two states is input, and when the second control signal is in the first state, the same signal as the shift pattern signal and the second control signal are in the second state. In this state, a mask that outputs a signal fixed to either the first state or the second state as a mask pattern signal.
A pattern generation circuit, a pattern synthesis circuit for inputting the second random pattern output signal and the mask pattern signal, logically calculating the input signals, and outputting the signal after the calculation as a sequence signal A sequence signal generation circuit having: 12. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal, and a counter for inputting a count value signal of the plurality of bits, and based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting a plurality of bits of first and second random pattern output signals, each of which has one of the above states, and outputs the random pattern output signal to the first and second random pattern output signals only when the count value signal shows a specific value. A random pattern generating circuit that sets the state to 1 and otherwise sets the random pattern output signal to the second state; and inputs the plurality of bits of the first random pattern output signal and the first control signal. A multi-bit shift signal having the same state as the multi-bit first random pattern output signal based on the first control signal and having different delay times in response to a change in the first control signal. A shift pattern generation circuit for generating and outputting a pattern signal, the shift pattern signal of a plurality of bits, and a first state and a second state When a second control signal having any one of them is input and the second control signal is in the first state, the second control signal is the same as the plurality of bits of the shift pattern signal. A mask pattern generation circuit that outputs a multi-bit signal fixed to either the first state or the second state as a multi-bit mask pattern signal when the signal is in the second state; The second random pattern output signal and the plurality of bits of the mask pattern signal are input,
A pattern synthesizing circuit that logically operates these input signals and outputs the resulting multi-bit signal as a multi-bit pattern synthesizing signal, and inputs the multi-bit pattern synthesizing signal and the third control signal , A pattern selection circuit which, in response to the third control signal, selects one pattern composite signal from the plurality of bit pattern composite signals and outputs it as a sequence signal. Generation circuit. 13. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal, and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting first and second random pattern output signals each having one of the states
A random pattern generation circuit that puts the random pattern output signal into a first state only when the count value signal shows a specific value, and otherwise puts the random pattern output signal into a second state; A first random pattern output signal and a first control signal are input, and the first random pattern output signal has the same state as the first random pattern output signal based on the first control signal. A shift pattern generation circuit that generates and outputs first and second shift pattern signals having different delay times in response to a change; and a first shift pattern signal, a first state, and a second state. When a second control signal having any of the above is input and the second control signal is in the first state, the same signal as the first shift pattern signal is input to the second control signal. A second state, a mask pattern generation circuit for outputting a signal fixed to either the first state or the second state as a mask pattern signal; the second random pattern output signal; A pattern synthesizing circuit for inputting the second shift pattern signal and the mask pattern signal, logically calculating at least two signals of these input signals, and outputting the calculated signal as a sequence signal. A sequence signal generation circuit having. 14. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal, and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits First state and second
A circuit for generating and outputting first and second random pattern output signals each having one of the states
A random pattern generation circuit that puts the random pattern output signal into a first state only when the count value signal shows a specific value, and otherwise puts the random pattern output signal into a second state; A first random pattern output signal and a first control signal are input, and the first random pattern output signal has the same state as the first random pattern output signal based on the first control signal. A shift pattern generation circuit that generates and outputs first and second shift pattern signals having different delay times in response to a change; and a first shift pattern signal, a first state, and a second state. When a second control signal having any of the above is input and the second control signal is in the first state, the same signal as the first shift pattern signal is input to the second control signal. A second state, a mask pattern generation circuit for outputting a signal fixed to either the first state or the second state as a mask pattern signal; the second random pattern output signal; A second shift pattern signal and the mask pattern signal are input, a plurality of sets of at least two signals of these input signals are logically operated, and a plurality of bit signals after the operation are combined into a pattern of a plurality of bits. A pattern synthesizing circuit for outputting as a signal, and the pattern synthesizing signal of the plurality of bits and a third control signal are input, and in response to the third control signal, one of the pattern synthesizing signals of the plurality of bits is synthesized. And a pattern selection circuit for selecting a signal and outputting it as a sequence signal. 15. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal; and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits. First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed and the second random pattern output signal and the control signal are input, and a shift pattern signal having the same state as the second random pattern output signal is input based on the control signal. A shift pattern generation circuit for generating and outputting, the third random pattern output signal, the toggle
A pattern synthesizing circuit for inputting a pattern output signal and the shift pattern signal, logically operating at least two signals of these input signals, and outputting the signal after the operation as a sequence signal. Sequence signal generation circuit. 16. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal; and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits. First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed, the second random pattern output signal and the first control signal are input, and the same state as the second random pattern output signal is set based on the first control signal. A shift pattern generation circuit for generating and outputting a shift pattern signal having the third random pattern output signal, the toggle
A pattern output signal and the shift pattern signal are input, a plurality of sets of at least two signals among these input signals are logically operated, and the operated multi-bit signal is output as a multi-bit pattern composite signal. A pattern synthesizing circuit, and the plurality of bits of the pattern synthesizing signal and a second control signal are input, and in response to the second control signal, one of the plurality of bits of the pattern synthesizing signal is selected. And a pattern selection circuit for outputting it as a sequence signal. 17. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal; and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits. First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed, the second random pattern output signal and the first control signal are input, and the same state as the second random pattern output signal is set based on the first control signal. A shift pattern generating circuit for generating and outputting a shift pattern signal having the shift pattern signal, the first state and the second state
A second control signal having any one of the two states is input, and when the second control signal is in the first state, the same signal as the shift pattern signal and the second control signal are in the second state. In this state, a mask that outputs a signal fixed to either the first state or the second state as a mask pattern signal.
A pattern generation circuit, the third random pattern output signal, the toggle
A pattern synthesizing circuit for inputting a pattern output signal and the mask / pattern signal, logically operating at least two signals of these input signals, and outputting the signal after the operation as a sequence signal. Sequence signal generation circuit. 18. A counter that inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal; and a counter that inputs the count value signal of a plurality of bits and outputs the count value signal of the plurality of bits based on the count value signal. First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed, the second random pattern output signal and the first control signal are input, and the same state as the second random pattern output signal is set based on the first control signal. A shift pattern generating circuit for generating and outputting a shift pattern signal having the shift pattern signal, the first state and the second state
The second control signal is input to the second control signal and the second control signal is the second signal when the second control signal is in the first state. In this state, a mask that outputs a signal fixed to either the first state or the second state as a mask pattern signal.
A pattern generation circuit, the third random pattern output signal, the toggle
A pattern output signal and the mask pattern signal are input, a plurality of sets of at least two signals of these input signals are logically operated, and the operated multi-bit signal is output as a multi-bit pattern composite signal. A pattern synthesizing circuit, the pattern synthesizing signal of a plurality of bits and a third control signal are input, and in response to the third control signal, one pattern synthesizing signal of the pattern synthesizing signals of a plurality of bits is selected. And a pattern selection circuit for outputting it as a sequence signal. 19. A counter which inputs a clock signal and outputs a count value signal of a plurality of bits based on the clock signal, and a counter which inputs the count value signal of a plurality of bits, and based on the count value signal of the plurality of bits First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed, the second random pattern output signal and the first control signal are input, and the same state as the first random pattern output signal is set based on the first control signal. A shift pattern generation circuit that has and that generates and outputs first and second shift pattern signals having different delay times in response to a change in the first control signal; and the first shift pattern signal and A second control signal having one of a first state and a second state is input, and when the second control signal is in the first state, the same signal as the first shift pattern signal is input. A mask pattern generation circuit for outputting a signal fixed to either the first state or the second state as a mask pattern signal when the second control signal is in the second state; La Dam pattern output signal, said toggle
A pattern output signal, the second shift pattern signal, and the mask pattern signal are input, at least two signals of these input signals are logically calculated, and the signal after the calculation is output as a sequence signal. A sequence signal generation circuit having a pattern synthesis circuit. 20. A counter for inputting a clock signal and outputting a count value signal of a plurality of bits based on the clock signal; and a counter for inputting the count value signal of a plurality of bits, based on the count value signal of the plurality of bits. First state and second
First, second and third, each having one of the states
Of the circuit for generating and outputting the random pattern output signal, the random pattern output signal is set to the first state only when the count value signal shows a specific value, and otherwise the random pattern output signal is set to the first state. A random pattern generation circuit in a second state and the first random pattern output signal are input, and either the first state or the second state is input based on the first random pattern output signal. A circuit for generating and outputting a toggle pattern output signal having the following: when the first random pattern output signal changes from a first state to a second state, the second state changes to a first state. Or the state of the first random pattern output signal changes, the state of the toggle pattern output signal is changed in response to any one of the changes. A toggle pattern generation circuit to be changed, the second random pattern output signal and the first control signal are input, and the same state as the first random pattern output signal is set based on the first control signal. A shift pattern generation circuit that has and that generates and outputs first and second shift pattern signals having different delay times in response to a change in the first control signal; and the first shift pattern signal and A second control signal having one of a first state and a second state is input, and when the second control signal is in the first state, the same signal as the first shift pattern signal is input. A mask pattern generation circuit for outputting a signal fixed to either the first state or the second state as a mask pattern signal when the second control signal is in the second state; La Dam pattern output signal, said toggle
A pattern output signal, the second shift pattern signal, and the mask pattern signal are input, a plurality of sets of at least two signals among these input signals are logically operated, and a signal of a plurality of bits after the operation is input. A pattern synthesizing circuit for outputting a pattern synthesizing signal of a plurality of bits, and a pattern synthesizing signal of a plurality of bits and a third control signal are inputted, and in response to the third control signal, A sequence signal generation circuit, comprising: a pattern selection circuit that selects one of the pattern combination signals and outputs it as a sequence signal.