JP2003330704A - Pseudo-random number pattern generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pseudo-random number pattern generating circuit capable of realizing a high speed operation even when output bit width is increased and easily being designed even when the output bit width is changed. <P>SOLUTION: The pseudo-random number pattern generating circuit is formed in an integrated circuit, and generates binary sequence pattern data of 2<SP>7</SP>-1 pseudo-random numbers having a plurality of output bit widths by using not an exclusive-OR gate but shift resistors 20 interconnected like a ring. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a pseudo random number pattern generation circuit,
For example, it is used for a data transfer test between a transmitter and a receiver for high speed data communication.

[0002]

2. Description of the Related Art Generally, a 2 ⁷ -1 pseudo random number pattern generation circuit used when repeatedly generating 2 ⁷ -1 bit pseudo random number binary sequence pattern data is a 1 bit output type or a multiple bit simultaneous output type. There is one.

FIG. 6 shows a conventional example of a 1-bit output 2 ⁷ -1 pseudo random number pattern generation circuit.

In the figure, seven registers Q0 to Q6 each operate in synchronization with a clock to form a shift register as a whole.

Each of the registers Q0 to Q6 can be set to an initial state, and a flip-flop circuit with a set terminal S / reset terminal R terminal is used, for example. Then, as an initial state, the register Q0 is set by applying the initialization pulse to the set terminal S, and the registers Q1 to Q6 are reset by applying the initialization pulse to the reset terminal R, respectively. Therefore, the initial value of the shift register 60 is Q [6: 0] = 000001.

The outputs of the registers Q0 to Q5 at the preceding stage are input to the registers Q1 to Q6, respectively, and the registers Q5 and Q6 are input.
The output of the register is processed by the exclusive OR gate EOR
You are entering in Q0.

Therefore, if the outputs of the registers Q5 and Q6 in a certain clock cycle are represented by Q5 (n) and Q6 (n), the output of the register Q0 will be Q1 (n + 1) = in the next clock cycle.
EOR (Q5 (n), Q6 (n)), and the output of the shift register is Q [6:
It is represented by 0] (n + 1) = {Q [5: 1] (n), EOR (Q5 (n), Q6 (n))}.

FIG. 7 shows pseudo random number binary sequence pattern data of 2 ⁷ -1 (= 127) bits which are sequentially output when the circuit shown in FIG. 6 is operated, and this sequence pattern data is It will be output repeatedly.

When outputting 8-bit width data using the circuit shown in FIG. 6, it is possible to continue outputting 1 bit in one cycle and output 8-bit width in the eighth cycle. , 8-bit width output cannot be output in one cycle.

FIG. 8 shows a conventional example of a 2 ⁷ -1 pseudo-random number pattern generating circuit with 8-bit output.

In the figure, seven registers Q0 to Q6 operate in synchronization with a clock, and seven exclusive OR gates EOR0 to EOR6 are connected between the registers and one exclusive OR gate EOR0 to EOR6. The OR gate EOR7 is for taking out the output OUTPUT [7].

In this circuit, values obtained by operating the circuit shown in FIG. 6 for 9 cycles are input to registers Q0 to Q6. As a result, the output OUTPUT [7: 0] having an 8-bit width can be generated in one cycle.

FIG. 9 shows a conventional example of a 2 ⁷ -1 pseudo random number pattern generating circuit which outputs 16 bits.

In the figure, seven registers Q0 to Q6 operate in synchronization with a clock, seven exclusive OR gates EOR0 to EOR6 are connected between the registers, and nine exclusive OR gates. The OR gates EOR7 to EOR15 are for taking out the outputs OUTPUT [7:15].

In this circuit, values obtained by operating the circuit shown in FIG. 6 for 17 cycles are input to registers Q0 to Q6. As a result, 16-bit wide output OUTPUT [15:
0] can be generated.

However, in the circuits of FIGS. 8 and 9 described above, when the output bit width is increased, the number of exclusive OR gates EOR0 to EOR6 existing between registers and exclusive OR gates EOR7 to EOR15 for output extraction are increased. Therefore, high speed operation becomes difficult.

Therefore, for example, in a data transfer test between a transmitter and a receiver for high-speed data communication in the vicinity of 2 GHz, the transmitter generates 2 ⁷ -1 pseudo-random binary sequence pattern data and transfers it to the receiver. This is an obstacle in achieving high-speed operation.

[0018]

As described above, the conventional 2 ⁷ -1 pseudo-random number pattern generation circuit has a problem that high-speed operation becomes difficult when the output bit width is increased.

The present invention has been made to solve the above problems, and can realize high-speed operation even when the output bit width of the pseudo random number pattern generation circuit is increased, and easily when changing the output bit width. An object is to provide a pseudo random number pattern generation circuit that can be designed.

[0020]

The first pseudo random number pattern generation circuit of the present invention operates in synchronization with each clock, and is connected in a ring shape as a whole to form a shift register, and an initial value can be set. And 127 wirings for extracting 2 ⁷ -1 bit pseudo-random number binary sequence pattern data in m bit width from m (positive integer) registers selected intermittently among the shift registers. It is characterized by including.

The second pseudo random number pattern generating circuit of the present invention operates in synchronization with each clock, and is connected in a ring shape as a whole to form a shift register, and 127 registers capable of setting initial values are provided. , M (a positive integer) or n, which are intermittently selected among the shift registers
And a selector circuit for selectively taking out 2 ⁷ −1 bit pseudo random binary sequence pattern data from the (positive integer) number of registers in the m-bit width or the n-bit width.

The third pseudo random number pattern generation circuit of the present invention operates in synchronization with each clock, and is connected in a ring shape as a whole to form a shift register, and an initial value can be set to 2 ⁿ -1 ( n is a positive integer) and m (a positive integer smaller than n) registers that are intermittently selected from the shift registers to generate 2 ⁿ -1 bit pseudo random binary sequence pattern data. It is characterized in that it is provided with a wiring taken out with a width of m bits.

The fourth pseudo random number pattern generation circuit of the present invention operates in synchronization with each clock, and is connected in a ring shape as a whole to form a shift register, and an initial value can be set to 2 ⁿ -1 ( n is a positive integer) and 2 ⁿ -1 from the shift register by the mode selection signal.
And a selection circuit for switching the output bit width m (a positive integer smaller than n) of the pseudo random binary sequence pattern data of bits to a plurality of types for selection.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The pseudo random number pattern generation circuit of the present invention is formed in an integrated circuit, and by using a shift register, pseudo random number binary sequence pattern data is generated at high speed without using an exclusive OR gate. The feature is that it is made to do.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
3 shows a 2 ⁿ -1 pseudo random number pattern generation circuit for generating a 2 ⁿ -1 (n is a positive integer) bit pseudo random number binary sequence pattern formed in the integrated circuit according to the embodiment of FIG.

In this pseudo random number pattern generation circuit, 2 ⁿ -1 registers each operating in synchronization with a clock are connected in a ring shape to form a 2 ⁿ -1 bit shift register 10, and this shift register 10 A predetermined initial value is set for each step of, and m (<n) is selected from a plurality of steps that are intermittently selected.
The wiring 11 is formed so as to take out the bit width output. A specific example having such a configuration will be described below.

(First Embodiment) FIG. 2 shows an 8 bit wide output 2 ⁷ -1 pseudo random number pattern generating circuit according to the first embodiment of the present invention.

In this pseudo random number pattern generation circuit,
The 127 registers Q0 to Q126 are connected in a ring shape as a whole to form the shift register 20, each of which can be set to an initial state, and each of them is, for example, a flip-flop circuit with a set terminal S / reset terminal R. Is used.

Of the shift registers, eight registers (15, 31, 47, 63, 79, 95, 11) which are intermittently selected are used.
Outputs are taken out from the (1,127th stage register) by the wiring 21, that is, 8-bit width outputs OUT [7] to OU
T [0] is generated.

Each stage register Q0 to Q1 of the shift register
26 is set by applying an initialization pulse to the set terminal S and is reset by applying an initialization pulse to the reset terminal R to set a predetermined initial value.

In this case, each stage register of the shift register
The initial values of Q0 to Q126 are set so that the pseudo random number binary sequence pattern data of 2 ⁷ -1 (= 127) bits shown in FIG. 7 can be output in units of continuous 8 bits in each cycle. .

That is, the 8th bit to the 1st bit of the pattern data shown in FIG. 7 are set corresponding to the 8 registers of the 15, 31, 47, 63, 79, 95, 111, 127 stages, and , 3
8 bits of 16th bit to 9th bit of the pattern data shown in FIG. 7 are set corresponding to 8 registers of 0, 46, 62, 78, 94, 110, 126 stages. The same procedure is followed, except for the 12th pattern data shown in Fig. 7 corresponding to the 7th register of the 16, 32, 48, 64, 80, 96, 112th stage.
Seven bits from the 7th bit to the 121st bit are set.

Therefore, the pseudo random number pattern generation circuit of FIG. 1 can be performed every 8 cycles with the conventional 1-bit output 2 ⁷ -1 pseudo random number pattern generation circuit shown in FIG.
An output equivalent to the bit width output OUTPUT [7: 0], that is, an 8-bit width output that is output every cycle by the conventional ^7- bit output 2 ⁷ -1 pseudo-random number pattern generation circuit shown in FIG. It operates so that equivalent outputs OUT [7] to OUT [0] are obtained every cycle.

In this case, the data transfer for each cycle is a high-speed transfer between the adjacent stages of the shift register or a high-speed transfer on a wiring for feedback connection in a ring shape, which exists between the registers as in the conventional example. Since the exclusive OR gate that does not use is not used, the delay associated with the processing does not occur, and high-speed operation becomes possible.

It is desirable to devise the pattern layout so that the distance of the feedback connection wiring between the registers is shortened. For example, as shown in the figure, each stage register Q0 to Q126 of the shift register is divided into a plurality of blocks, and The stage registers Q0 to Q126 may be arranged in a matrix as a whole.

(Second Embodiment) FIG. 3 shows a 16-bit wide output 2 ⁷ -1 pseudo random number pattern generating circuit according to a second embodiment of the present invention.

This pseudo random number pattern generation circuit is different from the pseudo random number pattern generation circuit described above with reference to FIG.
127 registers Q0 to Q1 forming the shift register 30
16 registers (7,1) selected intermittently out of 26
5,23,31,39,47,55,63,71,79,87,95,103,111,119,127th stage registers) outputs are respectively taken out by the wiring 31, that is, 16-bit width outputs OUT [15] to OUT [ 0]
Is generated.

In this case, the 16-bit width output OUTPUT [15: 0] which becomes possible for each cycle using the conventional 16-bit output 27 −1 pseudo random number pattern generating circuit shown in FIG.
The initial value is set so that an output equivalent to is obtained every cycle.

That is, each stage register Q0-
Q126 is a 2 ⁷ -1 (= 127) bit pseudo-random number 2 shown in FIG.
The initial value is set so that the base sequence pattern data can be output in units of continuous 16 bits for each cycle.

Therefore, the pseudo random number pattern generating circuit of FIG. 2 has a 16-bit output of 2 ⁷ -1 of the conventional example shown in FIG.
Outputs every cycle by the pseudo random number pattern generation circuit 1
It operates so that outputs OUT [15] to OUT [0] equivalent to 6-bit width output are obtained for each cycle.

In this case, the data transfer for each cycle is a high-speed transfer between the adjacent stages of the shift register or a high-speed transfer on a wiring for feedback connection in a ring shape, which exists between the registers as in the conventional example. Since the exclusive OR gate that does not use is not used, the delay associated with the processing does not occur, and high-speed operation becomes possible.

In each of the above embodiments, the means for setting the initial value of the shift register is not limited to the above example, but the initial value setting register (not shown) or externally transfers the initial value data to the shift register. It is also possible to change so as to set.

FIGS. 4A to 4C are diagrams for explaining changes in the operating state of the pseudo random number pattern generation circuit shown in FIG.

In FIG. 4A, a 2 ⁿ -1 bit shift register 10 consisting of 2 ⁿ -1 registers is a register having a multiple of the output bit width m and a register having a multiple of m from 2 ⁿ -1. Can be represented by a register of a number p (a positive integer smaller than m).

After a predetermined initial value is set in a clock cycle in such a 2 ⁿ -1 bit shift register, the state of the shift register in the next clock cycle is expressed as shown in FIG. 4 (b). The state after several cycles is expressed as shown in FIG.

Further, in the 2 ⁷ -1 pseudo-random number pattern generating circuit according to the above-mentioned first or second embodiment, even when it is desired to change the output bit width, the register stage for extracting the output from the shift register may be changed. Design can be done easily.

Therefore, using the same basic configuration as the circuit shown in FIG. 2 or 3, another bit width, for example, 10 is used.
It can easily be modified to take out bit-width output.

<Second Embodiment> FIG. 5 shows a second embodiment of the present invention.
2 shows an example of a 2 ⁷ -1 pseudo random number pattern generation circuit capable of switching and selecting the output bit width m to a plurality of types according to the embodiment of FIG.

Here, an example will be described in which the output bit width of the shift register consisting of 127 registers Q0 to Q126 is switched and selected to 16, 10 or 8 bits.

This pseudo random number pattern generation circuit has a 2 ⁷ -1
2 ⁷ -1 bit shift register 50 consisting of 50 registers
And a selection circuit (selector) for switching and selecting the output bit width of the shift register to 16 bits, 10 bits or 8 bits by a mode selection signal, and the initial value of the shift register 52 corresponding to the selected output bit width. It is characterized in that the setting contents of are switched.

According to such a pseudo random number pattern generating circuit, a simpler structure is provided as compared with the case where three sets of pseudo random number pattern generating circuits as shown in FIGS. 2 and 3 are simply provided on the same chip. Three kinds of output bit widths can be selected. Moreover, since the exclusive OR gate is not used, no delay occurs due to the processing, and high speed operation becomes possible.

[0053]

As described above, according to the pseudo random number pattern generating circuit of the present invention, high-speed operation can be realized even when the output bit width is increased, and design can be easily performed even when the output bit width is changed. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a 2n −1 pseudo random number pattern generation circuit that generates a 2n −1 bit pseudo random number binary sequence pattern formed in an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an 8 bit width output 27 −1 pseudo random number pattern generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a 16-bit width output 27 −1 pseudo random number pattern generation circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining changes in the operating state of the pseudo random number pattern generation circuit shown in FIG.

FIG. 5 is an output bit width m according to the second embodiment of the present invention.
2 is a circuit diagram showing an example of a 2 ⁷ -1 pseudo-random number pattern generation circuit capable of switching and selecting a plurality of types.

FIG. 6 is a circuit diagram showing a conventional example of a 1-bit output 2 ⁷ −1 pseudo random number pattern generation circuit.

7 is a diagram showing 2 ⁷ -1 (= 127) -bit pseudo random binary sequence pattern data that is sequentially output when the circuit shown in FIG. 6 is operated.

FIG. 8 is a circuit diagram showing a conventional example of an 8-bit output 2 ⁷ −1 pseudo random number pattern generation circuit.

FIG. 9 is a circuit diagram showing a conventional example of a 2 ⁷ −1 pseudo random number pattern generation circuit with 16-bit output.

[Explanation of symbols]

Q0 to Q126 ... Registers, 20 ... shift register, 21 ... Wiring.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Naoki Nakagawa             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5J049 AA18 CA04 CA07                 5J104 AA18 NA23

Claims (5)

[Claims] 1. 127 registers each of which operates in synchronization with a clock and is connected in a ring shape as a whole to form a shift register, and an initial value can be set, and the shift register is intermittently selected. And a wiring for extracting 2 ⁷ -1 bit pseudo random number binary sequence pattern data in m bit width from m (positive integer) registers. 2. 127 registers each of which operates in synchronization with a clock and is connected in a ring shape as a whole to form a shift register, and an initial value can be set, and the shift register is intermittently selected. 2 ⁷ out of m (positive integer) or n (positive integer) registers
-1 bit of pseudo random binary sequence pattern data
The pseudo random number pattern generation circuit according to claim 1, further comprising a selection circuit that selectively extracts the bit width or the n bit width. 3. A number of 2 ⁿ -1 (n is a positive integer) registers each of which operates in synchronization with a clock, is connected in a ring shape as a whole to form a shift register, and can set an initial value, Among the shift registers, m (n
And a wiring for extracting 2 ⁿ -1 bit pseudo random binary sequence pattern data in m-bit width from a smaller number of positive integers) registers. 4. A total of 2 ⁿ -1 (n is a positive integer) registers each of which operates in synchronization with a clock, is connected in a ring shape as a whole to form a shift register, and can set an initial value, 2 ⁿ from the shift register according to the mode selection signal
A pseudo-random number pattern generation circuit, comprising: a selection circuit for switching and selecting an output bit width m (a positive integer smaller than n) of a 1-bit pseudo-random number binary sequence pattern data. 5. A flip-flop circuit having a set / reset terminal is used for each register, and an initial value is set by applying an initial setting pulse to the set terminal or the reset terminal. The pseudo random number pattern generation circuit according to claim 1.