CN106569776A - Tero random number generator - Google Patents
Tero random number generator Download PDFInfo
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- CN106569776A CN106569776A CN201610984973.2A CN201610984973A CN106569776A CN 106569776 A CN106569776 A CN 106569776A CN 201610984973 A CN201610984973 A CN 201610984973A CN 106569776 A CN106569776 A CN 106569776A
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- Prior art keywords
- tero
- path
- input
- inverter
- metastable state
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
Abstract
The present invention discloses a TERO random number generator. The TERO random number generator comprises a TERO metastable oscillator and a counter. An input end of the counter is connected to an output end of the TERO metastable oscillator. By making the number of inverters in two paths of the TERO metastable oscillator different, the delays of the two paths differ, so that the inverters in the TERO metastable oscillator have a unified size, the circuit structure is simplified, the design difficulty is reduced, and influence of process and environment thereon is decreased.
Description
Technical field
The present invention relates to a kind of true random number generator circuit, more particularly to a kind of TERO (transition effect ring oscillations
Device) randomizer.
Background technology
Randomizer plays very crucial effect in all kinds of crypto chips especially smart card, such as key
Generate, the mask of sensitive data and blind etc..Traditional real random number generator is all based on analog circuit to realize, general to have
Have that area is larger, power consumption is higher, speed is slower, it is vulnerable the features such as.By Varchola et al. propose based on TERO with
Machine number generator is realized by digital circuit, so as to overcome the various shortcoming of simulation real random number generator in the past.
Based on the randomizer of TERO, comprising, TERO metastable states agitator and coupled enumerator.Its core
The TERO metastable states agitator of the heart includes two paths, and inverter device of the every path comprising same number and a control are shaken
The NAND gate swung, as shown in Figure 1.When control signal VCTRFor low level when, TERO metastable states agitator keeps stable.Work as control
Signal VCTRWhen being changed into high level from low level, TERO metastable state agitators start metastable state vibration, and the number of times of metastable state vibration is
Can be used as the output of randomizer.In order to generating metastable vibrates, the time delay of path 1 and path 2 must be variant.Generally
In order to meet the requirement of delay difference, way is the size for changing each inverter device in path.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of TERO randomizers, can make TERO metastable states vibration knot
Inverter device size unification in structure, reduces the impact of technique and environment to which.
For solve above-mentioned technical problem, TERO randomizers of the present invention, including：One TERO metastable state agitators, one
Enumerator；The input of the enumerator is connected with the outfan of TERO metastable state agitators；
The TERO metastable states agitator includes two paths, the output V of the first pathOUT1For the input of alternate path,
The output V of alternate pathOUT2For the input of the first path；
First path includes the device with inverter functionality of multiple series connection, forms the first inverter device chain, remembers which
In the device number of effective inverter functionality be n, meet n for even number；First path also including one be used for control vibration with
Not gate, one input end are connected with the outfan of the first inverter device chain, and another input is input into oscillation control signal
VCTR；
The alternate path includes the device with inverter functionality of multiple series connection, forms the second inverter device chain, remembers which
In the device number of effective inverter functionality be m, meet m for even number and be not equal to n；The alternate path also is used to control including one
The NAND gate that damping is swung, one input end are connected with the outfan of the second inverter device chain, another input input vibration
Control signal VCTR；
Under nonoscillating state, by oscillation control signal VCTRRemain low level；As oscillation control signal VCTRFrom low level
When being changed into high level, TERO metastable state agitators start metastable state vibration, the number of times vibrated by counter records metastable state；Vibration
After the completion of, a bit or many bits of the metastable state number of oscillation can be used as the result output of randomizer.
Two input nand gates of the device with inverter functionality, including but not limited to phase inverter, a termination high level.
During MUX is added in first path and alternate path to path with effective inverter functionality
The number of device is selected, and as can configure the TERO randomizers of asymmetric time-delay access.
The beneficial effects of the present invention is：In due to two paths of TERO metastable state agitators with inverter functionality
Device number is unequal so that the time delay of two paths is variant so that in TERO metastable state agitators with anti-phase
The device size unification of function, simplifies circuit structure and design difficulty, and path time-delay characteristics and the vibration of TERO metastable states are by technique
It is little with environmental effect.
Further, the present invention can also be by adding MUX in the first path and alternate path so that first leads to
The time delay of road and alternate path can configure, and so as to obtain the TERO metastable state oscillating structures of more delay selections, and different prolong
When select to obtain the random sequences that different random sequences produce speed and different statistical result.
Description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is existing TERO metastable states oscillator structure figure；
Fig. 2 is the TERO metastable state agitator schematic diagrams of asymmetric time-delay access；
Fig. 3 is the TERO metastable state agitator schematic diagrams that can configure asymmetric time-delay access；
Fig. 4 is the TERO randomizer structure charts with asymmetric time-delay access.
Specific embodiment
The TERO randomizers of the present invention are the TERO randomizers of asymmetric time-delay access, with reference to Fig. 4 institutes
Show, which includes the TERO metastable states agitator and coupled enumerator of asymmetric time-delay access.
The TERO randomizers of asymmetric time-delay access are exactly by causing two of TERO metastable state oscillating structures
Inverter device number in path is unequal, so that the time delay of two paths produces difference.In order to generating metastable vibrates,
The time delay of first path and alternate path of TERO metastable state oscillating structures must be variant.When inverter device number is equal,
In order that the time delay of two paths produces difference, must just change the size of inverter device.Various sizes of device is in difference
Technique and environment under (such as temperature, voltage etc.), its time-delay characteristics has larger difference, cause metastable state vibrate characteristic
Difference is also larger.And adopt the device of same size, can just cause TERO metastable states oscillating structure by technique and environmental effect more
It is little.The TERO randomizers of asymmetric time-delay access produce the difference of path time delay by the number of change inverter device
It is different so that all inverter devices in time-delay access can use the device of same type same size such that it is able to reduce work
The impact that skill and environment are vibrated to metastable state.In addition, if anti-phase to realize using two input nand gates of a termination high level
Function, can cause all devices all same-type same sizes in TERO metastable state oscillating structures, so as to further reduce work
The impact that skill and environment are vibrated to metastable state.
Embodiment 1
Referring to Fig. 2 and Fig. 4, in the present embodiment, using the high electricity of a termination in the time-delay access of TERO metastable state agitators
Two flat input nand gates are realizing inverter functionality.
TERO metastable states agitator includes two time-delay access：The output V of the first pathOUT1For the input of alternate path,
The output V of alternate pathOUT2For the input of the first path.
Two input nand gates comprising 8 one termination high level in first path, 8 NAND gate are sequentially connected in series, are formed
NAND gate chain, and a NAND gate for being used to control vibration；For control vibration NAND gate, one input and with it is non-
The output of door chain is connected, another input and oscillation control signal VCTRIt is connected.
Two input nand gates comprising 10 one termination high level in alternate path, 10 NAND gate are sequentially connected in series, shape
Into NAND gate chain, and a NAND gate for being used to control vibration；For control vibration NAND gate, one input and with
The output of non-door chain is connected, another input and oscillation control signal VCTRIt is connected.
Under nonoscillating state, by VCTRRemain low level.As oscillation control signal VCTRWhen being changed into high level from low level,
The TERO metastable state agitators of asymmetric time-delay access start metastable state vibration, the number of times vibrated by counter records metastable state.
After the completion of vibration, a bit of the metastable state number of oscillation can be used as the result output of randomizer.
Embodiment 2
Referring to Fig. 3, the present embodiment is the TERO randomizers that can configure asymmetric time-delay access.Wherein, TERO is sub-
Steady oscillation device is the TERO metastable state agitators that can configure asymmetric time-delay access, using phase inverter realizing in time-delay access
Inverter functionality；Using MUX come the number of effective phase inverter in selection path in first path and alternate path.
The output V of the first path of TERO metastable state agitatorsOUT1For the input of alternate path, the output of alternate path
VOUT2For the input of the first path.
2N phase inverter is included in first path, be may be selected by selection input signal S1 of MUX effectively anti-phase
The number of device.When S1 is R11When, the number of effective phase inverter is 2；When S1 is R12When, the number of effective phase inverter is 4；With this
Analogize.Also comprising a NAND gate for being used to control vibration, the output phase of one input and chain of inverters in first path
Even, another input is input into oscillation control signal VCTR。
2N phase inverter is included in alternate path, be may be selected by selection input signal S2 of MUX effectively anti-phase
The number of device.When S2 is R21When, the number of effective phase inverter is 2；When S2 is R22When, the number of effective phase inverter is 4；With this
Analogize.Meet S2 and be not equal to S1.In alternate path also comprising one be used for control vibration NAND gate, one input with it is anti-
The output of phase device chain is connected, and another input is input into oscillation control signal VCTR.N is the integer more than or equal to 1.
Under nonoscillating state, by VCTRRemain low level.As oscillation control signal VCTRIt is changed into high level from low level
When, the TERO metastable state agitator structures that can configure asymmetric time-delay access start metastable state vibration, by counter records metastable state
The number of times of vibration.After the completion of vibration, a bit of the metastable state number of oscillation can be used as the result output of randomizer.
The present invention is described in detail above by specific embodiment, but these have not been constituted to the present invention's
Limit.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, these
Should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of TERO randomizers, including：One TERO metastable state agitators, an enumerator；The input of the enumerator
End is connected with the outfan of TERO metastable state agitators；
The TERO metastable states agitator includes two paths, and the first path is output as the input of alternate path, alternate path
It is output as the input of the first path；
First path includes the device with inverter functionality of multiple series connection, forms the first inverter device chain, and note wherein has
The device number of the inverter functionality of effect is n, meets n for even number；First path also is used to control the NAND gate of vibration including one,
One input end is connected with the outfan of the first inverter device chain, and another input is input into oscillation control signal；Its feature
It is：
The alternate path includes the device with inverter functionality of multiple series connection, forms the second inverter device chain, and note wherein has
The device number of the inverter functionality of effect is m, meets m for even number and is not equal to n；The alternate path also shakes for control including one
The NAND gate swung, one input end are connected with the outfan of the second inverter device chain, and another input is input into the vibration
Control signal；
Under nonoscillating state, oscillation control signal is remained into low level；When oscillation control signal is changed into high level from low level
When, TERO metastable state agitators start metastable state vibration, the number of times vibrated by counter records metastable state；It is after the completion of vibration, sub-
One bit or many bits of steady oscillation number of times can be used as the result output of randomizer.
2. TERO randomizers as claimed in claim 1, it is characterised in that：The device with inverter functionality, bag
Include phase inverter, two input nand gates of a termination high level.
3. TERO randomizers as claimed in claim 1, it is characterised in that：In first path and alternate path also
Including a MUX, the number for the effective inverter device in path is selected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984973.2A CN106569776A (en) | 2016-11-09 | 2016-11-09 | Tero random number generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984973.2A CN106569776A (en) | 2016-11-09 | 2016-11-09 | Tero random number generator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765479B (en) * | 2020-12-17 | 2022-05-21 | 國立中山大學 | Random number generator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521538A (en) * | 2011-12-07 | 2012-06-27 | 浙江大学 | Physical no-cloning function structure based on multi-frequency band |
| US8583711B2 (en) * | 2009-12-02 | 2013-11-12 | Seagate Technology Llc | Random number generation system with ring oscillators |
-
2016
- 2016-11-09 CN CN201610984973.2A patent/CN106569776A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8583711B2 (en) * | 2009-12-02 | 2013-11-12 | Seagate Technology Llc | Random number generation system with ring oscillators |
| CN102521538A (en) * | 2011-12-07 | 2012-06-27 | 浙江大学 | Physical no-cloning function structure based on multi-frequency band |
Non-Patent Citations (4)
| Title |
|---|
| MICHAL VARCHOLA ET AL.: "New High Entropy Element for FPGA based True Random Number Generators", 《INTERNATIONAL CONFERENCE ON CRYPTOGRAPHIC HARDWARE & EMBEDDED SYSTEMS》 * |
| PATRICK HADDAD ET AL.: "A Physical Approach for Stochastic Modeling of TERO-based TRNG", 《CRYTOGRAPHIC HARDWARE AND TMBEDDED SYSTEMS--CHES2015》 * |
| VIKTOR FISCHER,ET AL.: "ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED IN FPGA", 《2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS》 * |
| 吴新杰等: "《数字电子技术项目教程》", 31 January 2014, 北京航空航天大学出版社 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765479B (en) * | 2020-12-17 | 2022-05-21 | 國立中山大學 | Random number generator |
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