CN108768619B - Working method of strong PUF circuit based on ring oscillator - Google Patents
Working method of strong PUF circuit based on ring oscillator Download PDFInfo
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- CN108768619B CN108768619B CN201810586232.8A CN201810586232A CN108768619B CN 108768619 B CN108768619 B CN 108768619B CN 201810586232 A CN201810586232 A CN 201810586232A CN 108768619 B CN108768619 B CN 108768619B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention provides a strong PUF circuit based on a ring oscillator and a working method thereof, belonging to the technical field of information security and cryptography. The strong PUF circuit based on the ring oscillator comprises a ring oscillator array circuit, a data selection circuit, a first counter circuit, a second counter circuit, a data comparator circuit, a serial-parallel conversion circuit and an AES encryption circuit. The ring oscillator structure is combined with an AES encryption circuit, so that the characteristic requirement of a strong PUF is met. And the circuit structure is multiplexed to the greatest extent, the circuit overhead is greatly reduced, the structure is flexible and simple, the generated secret key is high in uniqueness and reliability, and the requirement that the strong PUF has massive excitation-response pairs can be met.
Description
Technical Field
The invention relates to the technical field of information security and cryptography, in particular to a strong PUF circuit based on a ring oscillator and a working method thereof.
Background
A ring oscillator is a closed loop formed by a string of an odd number of inverters connected in series with an oscillation period equal to the sum of all delays from the first to the last stage. Thus, the magnitude of the propagation delay of a digital signal is a function of the electrical parameters of the component that the signal encounters on the path. These device electronic parameters include MOSFET channel length, width, and threshold voltage, all of which are affected to varying degrees by uncontrollable variations in the manufacturing process. Therefore, the propagation delay of the digital signal will exhibit partial randomness, influenced by the specific physical entity, exhibiting a physical unclonable behavior at the time of measurement.
Until now, foreign markets have mature Physical Unclonable Function (PUF) products in commerce. The United states Intrinsic-ID company, as an industry leader, has applied its products to smart cards, automobiles, FPGAs, logistics and government fields in recent years, especially in deep cooperation with NXP and Altera. The company's solution not only eliminates the need for non-volatile storage for storage keys for next generation chips, but also applies to existing systems. With a PUF the key can be extracted from the hardware properties of the chip (like the biometric fingerprint of the chip) when needed. Since there is no key in the power-off state, a hacker cannot crack any information, and conventionally the key is permanently stored in non-volatile memory.
In the existing digital PUF technology, a ring oscillator structure, an arbiter structure, an SRAM memory structure, and the like are mainly used. Compared with the characteristic that a strong PUF has massive excitation-response pairs, the conventional PUF can only generate a small number of random bit sequences, and the performance cannot meet the requirement.
Disclosure of Invention
The invention aims to provide a strong PUF circuit based on a ring oscillator and a working method thereof, and aims to solve the problems that the existing PUF circuit is low in performance, and a generated key is not unique and poor in reliability.
In order to solve the technical problems, the invention provides a strong PUF circuit based on a ring oscillator and a working method thereof, wherein the strong PUF circuit based on the ring oscillator comprises a ring oscillator array circuit, a data selection circuit, a first counter circuit, a second counter circuit, a data comparator circuit, a serial-parallel conversion circuit and an AES encryption circuit;
the ring oscillator array circuit comprises N +1 paths of ring oscillator circuits, N is a natural number not less than 128, the output end of each path of ring oscillator circuit is connected with the data input end of the data selection circuit, and the input end of each path of ring oscillator circuit is connected with the same pulse signal;
a first output end of the data selection circuit is connected with an input end of the first counter circuit, and a second output end of the data selection circuit is connected with an input end of the second counter circuit;
the output end of the first counter circuit is connected with the first input end of the data comparator circuit, and the output end of the second counter circuit is connected with the second input end of the data comparator circuit;
the output end of the data comparator circuit is connected with the input end of the serial-parallel conversion circuit;
and the output end of the serial-parallel conversion circuit is connected with the key input end of the AES encryption circuit.
Optionally, each ring oscillator circuit includes 1 two-input nand gate and 2 × k +1 not gates connected in series in sequence, one input end of the two-input nand gate is connected to the pulse signal, and the other input end of the two-input nand gate is connected to an output end of the 2 × k not gate in the same ring oscillator circuit, where k is a natural number greater than 0.
Optionally, reset signal input ends of the first counter circuit and the second counter circuit are both connected to a reset signal.
Optionally, a selection signal input end of the data selection circuit is connected to a selection signal.
Optionally, the first counter circuit and the second counter circuit use an M-bit counter, and a value of M is set according to a frequency of the clock signal.
The invention also provides a working method of the strong PUF circuit based on the ring oscillator, which comprises the following steps:
step 3, the first counter circuit and the second counter circuit respectively count the clock signals input by the first counter circuit and the second counter circuit, and input two obtained count values into the data comparator circuit;
step 4, the data comparator circuit compares the count values input by the first counter circuit and the second counter circuit, and outputs a comparison result;
step 5, traversing the selection signals in sequence, and repeatedly executing the step 2 to the step 4 until the output of the comparison result corresponding to the last group of adjacent ring oscillator circuits is completed;
step 6, forming the output results into a group of character strings, selecting continuous 128 bits from the character strings, converting the character strings into parallel 128-bit-length data through a serial-parallel conversion circuit, and inputting the data serving as a key into an AES encryption circuit;
step 7, the AES encryption circuit obtains a corresponding 128-bit response aiming at any 128-bit excitation, thereby forming an excitation-response pair; due to the sufficient data bit width, a large number of stimulus-response pairs can be generated.
Optionally, step 4 specifically includes:
if the count value input by the first counter circuit is larger than the count value input by the second counter circuit, the data comparator circuit outputs 0; the data comparator circuit outputs a 1 when the count value input by the first counter circuit is less than the count value input by the second counter circuit;
if the count value input by the first counter circuit is larger than the count value input by the second counter circuit, the data comparator circuit outputs 1; then the data comparator circuit outputs 0 when the count value input by the first counter circuit is less than the count value input by the second counter circuit.
Optionally, the operation method of the ring oscillator-based strong PUF circuit further includes:
when the selection signal is changed, a reset signal is input to the first counter circuit and the second counter circuit to reset the count values thereof to 0.
Optionally, the key of the AES encryption circuit is 128 bits long, and the excitation-response pair is also 128 bits long.
The invention provides a strong PUF circuit based on a ring oscillator and a working method thereof. The ring oscillator structure is combined with an AES encryption circuit, so that the characteristic requirement of a strong PUF is met. And the circuit structure is multiplexed to the greatest extent, the circuit overhead is greatly reduced, the structure is flexible and simple, the generated secret key is high in uniqueness and reliability, and the requirement that the strong PUF has massive excitation-response pairs can be met.
Drawings
FIG. 1 is a schematic diagram of a strong PUF circuit based on a ring oscillator;
fig. 2 is a schematic diagram of a ring oscillator array circuit.
Detailed Description
The strong PUF circuit based on a ring oscillator and the operation method thereof proposed by the present invention are further described in detail with reference to the drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The first embodiment of the invention provides a strong PUF circuit based on a ring oscillator, as shown in fig. 1, to generate a large number of excitation-response pairs with high reliability. The ring oscillator-based strong PUF circuit includes a ring oscillator array circuit 10, a data selection circuit 11, a first counter circuit 12, a second counter circuit 13, a data comparator circuit 14, a serial-parallel conversion circuit 15, and an AES encryption circuit 16.
Specifically, the ring oscillator array circuit 10 includes at least 129 ring oscillator circuits 100, an output end of each ring oscillator circuit 100 is connected to a data input end of the data selection circuit 11, and input ends of each ring oscillator circuit 100 are connected to the same pulse signal. After the pulse signal arrives, each ring oscillator circuit 100 starts to oscillate to generate and output a clock signal. Because each route has different time delay, the route with prolonged time is caused, the oscillation frequency is low, the route with short time delay is caused, and the oscillation frequency is high. A first output end of the data selection circuit 11 is connected to an input end of the first counter circuit 12, a second output end of the data selection circuit 11 is connected to an input end of the second counter circuit 13, and a selection signal input end of the data selection circuit 11 is connected to a selection signal. An output end of the first counter circuit 12 is connected with a first input end of the data comparator circuit 14, and an output end of the second counter circuit 13 is connected with a second input end of the data comparator circuit 14; the reset signal input ends of the first counter circuit 12 and the second counter circuit 13 are both connected with a reset signal, so that when the selection signal changes, the count values in the first counter circuit 12 and the second counter circuit 13 are reset to 0. The output end of the data comparator circuit 14 is connected with the input end of the serial-parallel conversion circuit 15; the output end of the serial-parallel conversion circuit 15 is connected with the key input end of the AES encryption circuit 16. The serial-to-parallel conversion circuit 15 converts the 128-bit data generated serially by the data comparison circuit 14 into a parallel 128-bit key data output, and the AES encryption circuit 16 key adopts a 128-bit length, and the excitation and the response of the AES encryption circuit are respectively 128-bit length.
Specifically, in order to ensure that the first counter circuit 12 and the second counter circuit 13 can correctly count the clock signal, the first counter circuit 12 and the second counter circuit 13 use an M-bit counter, and in practical application, a value of M is set according to a frequency of the clock signal.
Fig. 2 is a schematic structural diagram of the ring oscillator array circuit 10. The ring oscillator array circuit 10 includes N +1 ring oscillator circuits 100. Each ring oscillator circuit 100 includes 1 two-input nand gate and 2 × k +1 not gates connected in series in sequence, one input end of the two-input nand gate is connected to a pulse signal, and the other input end is connected to an output end of the 2 × k not gate in the same ring oscillator circuit, where k is a natural number greater than 0, and can be flexibly configured according to actual needs and circuit conditions. When a 1-bit pulse signal is input, a clock signal of N +1 bits will be output.
In addition, in the actual circuit design, the layout and the wiring of each ring oscillator circuit 100 need to conform to the wiring rules of adjacent arrangement, symmetrical arrangement and internal wiring.
Example two
Based on the strong PUF circuit based on the ring oscillator provided in the first embodiment, a second embodiment of the present invention provides a working method of the strong PUF circuit based on the ring oscillator, where the ring oscillator array circuit 10 includes N +1 ring oscillator circuits 100, N is a natural number greater than 0, and the working method of the strong PUF circuit based on the ring oscillator includes the following steps:
the method comprises the following steps: inputting a pulse signal at an input terminal of the N + 1-path ring oscillator circuit 100, wherein the N + 1-path ring oscillator circuit 100 starts oscillating to generate N +1 clock signals with different frequencies;
step two: inputting a selection signal to a data selection circuit 11, wherein the data selection circuit 11 respectively inputs clock signals of two adjacent paths of ring oscillator circuits corresponding to the selection signal to a first counter circuit 12 and a second counter circuit 13; specifically, for convenience of description, the two adjacent ring oscillator circuits may be referred to as the ith ring oscillator circuit 100 and the (i + 1) th ring oscillator circuit 100, where i is a natural number greater than 0 and less than or equal to N. The data selection circuit 11 inputs the clock signal of the ith ring oscillator circuit 100 in the two adjacent ring oscillator circuits to the first counter circuit 12, and inputs the clock signal of the (i + 1) th ring oscillator circuit 100 in the two adjacent ring oscillator circuits to the second counter circuit 13;
step three: the first counter circuit 12 and the second counter circuit 13 respectively count respective input clock signals, and input two obtained count values to the data comparator circuit 14; correspondingly, the first counter circuit 12 counts the clock signal of the ith ring oscillator circuit 100, and inputs the obtained first count value to the first input end of the data comparator circuit 14; the second counter circuit 13 counts the clock signal of the (i + 1) th ring oscillator circuit 100, and inputs the obtained second count value to the second input terminal of the data comparator circuit 14. Specifically, the first count value and the second count value are both supplied to the data comparator circuit 14 in the form of circuit signals;
step four: the data comparator circuit 14 compares the count values input from the first counter circuit 12 and the second counter circuit 13, and outputs a comparison result. Specifically, if the first count value is greater than the second count value, the data comparator circuit 14 outputs 0, and if the first count value is less than the second count value, the data comparator circuit 14 outputs 1; if the data comparator circuit 14 outputs a 1 when the first count value is greater than the second count value, then the data comparator circuit 14 outputs a 0 when the first count value is less than the second count value.
Step five, traversing the selection signals in sequence through an external circuit, and repeatedly executing the step two to the step four until the output of the comparison result corresponding to the last group of adjacent ring oscillator circuits is completed; specifically, the selection signals sequentially include 0 to (N-1), when the traversed selection signal is j, the data selection circuit 11 selects the clock signals output by the jth ring oscillator circuit 100 and the jth +1 ring oscillator circuit 100, and j is a natural number greater than or equal to 0 and less than or equal to N-1;
in order to ensure the accuracy of counting the clock signals output by the two newly selected ring oscillator circuits 100 after the selection signal is changed, when the selection signal input to the data selection circuit 11 is changed, a reset signal is input into the first counter circuit 12 and the second counter circuit 13 to control the count value to be reset to 0;
and step six, finally obtaining a group of character strings consisting of N binary numerical values, namely the key root character strings. Selecting continuous 128 bits from the character string, converting the continuous 128 bits into parallel 128-bit-length data through a serial-parallel conversion circuit 15, and inputting the parallel 128-bit-length data into an AES encryption circuit 16 as a key;
and step seven, after the AES encryption circuit 16 obtains the key input, corresponding 128-bit response can be obtained for any 128-bit excitation, so that an excitation-response pair is formed. With sufficient data bit width, a large number of stimulus-response pairs can be generated.
Specifically, the length N of the key root string may be flexibly configured according to actual requirements and circuit conditions.
EXAMPLE III
In the third embodiment, the working process of the strong PUF circuit based on the ring oscillator under the coordination of the peripheral circuit is described by taking the length of the 1024-bit key root string as an example.
In the third embodiment, the ring oscillator array circuit 10 includes 1025 ring oscillator circuits 100, each ring oscillator circuit 100 is formed by connecting in series 1 two-input nand gate and 9 not gates, and two input terminals of the nand gate are respectively connected to the pulse signal and the feedback signal output by the 8 th not gate. The data selection circuit 11 selects 2 by 2015, both counters are 32 bits, and the data comparator circuit 14 has a data bit width of 32 bits, i.e., N =1024, M =32, and k =4 in the first and second embodiments.
With the circuit, the strong PUF circuit based on the ring oscillator has the following working steps:
after power-on initialization, the pulse signal is temporarily set to "1" and then to "0", the 2015-circuit ring oscillator array circuit 100 starts to oscillate to generate different frequency outputs, first, the data selection circuit 11 inputs the selection signal 10'd 0, and the data selection circuit 11 selects the output results of the 0 th and 1 st ring oscillator circuits 100 and transmits the results to the first counter 12 and the second counter 13, respectively. At this time, the values in the two counters are incremented rapidly, and assuming that the path delay of the 0 th ring oscillator circuit 100 is smaller than the path delay of the 1 st ring oscillator circuit 100, which means that the frequency of the 0 th ring oscillator is higher than the frequency of the 1 st ring oscillator, the value of the first counter 12 must be larger than the value of the second counter 13. Thus, the data comparator circuit 14 produces an output of "1".
Under the control of the peripheral circuit, after 1ms, the reset signal set to "1" resets the two counters and changes the selection signal to 10 d' 1 at the same time, and at this time, the data selection circuit 11 selects the output results of the 1 st and 2 nd ring oscillator circuits 100 and transfers them to the first counter 12 and the second counter 13, respectively. Assuming that the 1 st ring oscillator circuit 100 path delay is greater than the 2 nd ring oscillator circuit 100 path delay, meaning that the 1 st ring oscillation frequency is lower than the 2 nd ring oscillation, then the value of the first counter 12 must be less than the value of the second counter 13. Thus, data comparator circuit 14 produces an output of "0".
Repeating the above steps, after the selection signal traverses 10d '0 to 10 d' 1023, the circuit outputs to obtain a complete serial bit data stream containing 1024-bit key root character strings. Continuous 128 bits are arbitrarily selected from the key data, and after the serial-parallel conversion circuit 15 processes the key data, a 128-bit key is generated to be used as the key input of the AES encryption circuit 16. For any stimulus, the AES encryption circuit 16 may use key encryption to obtain a corresponding response, forming a stimulus-response pair. The whole process takes about 1 s.
In summary, by using a ring oscillator PUF-based circuit to generate an inter-chip unique key, an AES encryption circuit is enabled to generate an inter-chip unique response, constituting a strong PUF. And on the basis, the circuit structure is multiplexed to the greatest extent, the circuit overhead is greatly reduced, the structure is flexible and simple, the generated secret key is high in uniqueness and reliability, and the requirement that the strong PUF has massive excitation-response pairs can be met.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (3)
1. A working method of a strong PUF circuit based on a ring oscillator comprises a ring oscillator array circuit, a data selection circuit, a first counter circuit, a second counter circuit, a data comparator circuit, a serial-parallel conversion circuit and an AES encryption circuit; the ring oscillator array circuit comprises N +1 paths of ring oscillator circuits, N is a natural number not less than 128, the output end of each path of ring oscillator circuit is connected with the data input end of the data selection circuit, and the input end of each path of ring oscillator circuit is connected with the same pulse signal; a first output end of the data selection circuit is connected with an input end of the first counter circuit, and a second output end of the data selection circuit is connected with an input end of the second counter circuit; the output end of the first counter circuit is connected with the first input end of the data comparator circuit, and the output end of the second counter circuit is connected with the second input end of the data comparator circuit; the output end of the data comparator circuit is connected with the input end of the serial-parallel conversion circuit; the output end of the serial-parallel conversion circuit is connected with the key input end of the AES encryption circuit;
each ring oscillator circuit comprises 1 two-input NAND gate and 2 x k +1 NOT gates which are sequentially connected in series, wherein one input end of each two-input NAND gate is connected with a pulse signal, and the other input end of each two-input NAND gate is connected with the output end of the 2 x k NOT gate in the same ring oscillator circuit, wherein k is a natural number greater than 0;
reset signal input ends of the first counter circuit and the second counter circuit are both connected with reset signals;
the selection signal input end of the data selection circuit is connected with a selection signal;
the first counter circuit and the second counter circuit adopt M-bit counters, and the value of M is set according to the frequency of a clock signal;
the working method of the strong PUF circuit based on the ring oscillator is characterized by comprising the following steps of:
step 1, inputting a pulse signal to an input end of an N + 1-path ring oscillator circuit, and starting oscillation to generate N +1 clock signals with different frequencies;
step 2, the data selection circuit inputs a selection signal, and clock signals of two adjacent paths of ring oscillator circuits corresponding to the selection signal are respectively input to a first counter circuit and a second counter circuit;
step 3, the first counter circuit and the second counter circuit respectively count the clock signals input by the first counter circuit and the second counter circuit, and input two obtained count values into the data comparator circuit;
step 4, the data comparator circuit compares the count values input by the first counter circuit and the second counter circuit, and outputs a comparison result; if the count value input by the first counter circuit is greater than the count value input by the second counter circuit, the data comparator circuit outputs 0, and if the count value input by the first counter circuit is less than the count value input by the second counter circuit, the data comparator circuit outputs 1; if the count value input by the first counter circuit is greater than the count value input by the second counter circuit, the data comparator circuit outputs 1, and if the count value input by the first counter circuit is less than the count value input by the second counter circuit, the data comparator circuit outputs 0;
step 5, traversing the selection signals in sequence, and repeatedly executing the step 2 to the step 4 until the output of the comparison result corresponding to the last group of adjacent ring oscillator circuits is completed;
step 6, forming the output results into a group of character strings, selecting continuous 128 bits from the character strings, converting the character strings into parallel 128-bit-length data through a serial-parallel conversion circuit, and inputting the data serving as a key into an AES encryption circuit;
step 7, the AES encryption circuit obtains a corresponding 128-bit response aiming at any 128-bit excitation, thereby forming an excitation-response pair; due to the sufficient data bit width, a large number of stimulus-response pairs can be generated.
2. The method of claim 1, further comprising:
when the selection signal is changed, a reset signal is input to the first counter circuit and the second counter circuit to reset the count values thereof to 0.
3. The method of claim 1, wherein the key of the AES encryption circuit is 128 bits long and the stimulus-response pair is also 128 bits long.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106919764B (en) * | 2017-03-07 | 2020-03-17 | 合肥工业大学 | Reliability detection method for ring oscillator physical unclonable function based on FPGA |
| CN110545174A (en) * | 2019-08-16 | 2019-12-06 | 浙江大华技术股份有限公司 | circuit for generating secret key and information encryption and decryption method |
| CN110677255A (en) * | 2019-09-24 | 2020-01-10 | 中国电子科技集团公司第五十八研究所 | Strong PUF (physical unclonable function) working circuit and method based on SRAM (static random Access memory) |
| CN111082925B (en) * | 2019-10-23 | 2021-07-30 | 中山大学 | Embedded system encryption protection device and method based on AES algorithm and PUF technology |
| CN111355589B (en) * | 2020-01-16 | 2021-02-19 | 南京航空航天大学 | Reconfigurable ring oscillator physical unclonable function circuit and excitation generation method thereof |
| CN111865615B (en) * | 2020-07-30 | 2022-07-19 | 南京博芯电子技术有限公司 | APUF circuit with detectable reliability and working method |
| CN113507362B (en) * | 2021-07-08 | 2022-04-01 | 电子科技大学 | RO PUF secret key generation method based on quadruple comparison strategy |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521538A (en) * | 2011-12-07 | 2012-06-27 | 浙江大学 | Physical no-cloning function structure based on multi-frequency band |
| CN105743645A (en) * | 2016-01-25 | 2016-07-06 | 清华大学 | PUF (Physical Unclonable Function)-based stream key generation device and method and data encryption and decryption method |
| CN105811923A (en) * | 2016-02-29 | 2016-07-27 | 中国电子科技集团公司第五十八研究所 | Clock duty ratio adjusting circuit |
| CN107483180A (en) * | 2017-08-21 | 2017-12-15 | 湖南大学 | A kind of high stability physics unclonable function circuit and its response production method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011054410B4 (en) * | 2011-10-12 | 2014-09-25 | Infineon Technologies Ag | Device and method for generating a bit sequence |
| US20150188717A1 (en) * | 2013-12-26 | 2015-07-02 | Wei Wu | Physically unclonable function redundant bits |
| WO2015148659A1 (en) * | 2014-03-25 | 2015-10-01 | Mai Kenneth Wei-An | Methods for generating reliable responses in physical unclonable functions (pufs) and methods for designing strong pufs |
| US9787481B2 (en) * | 2014-08-28 | 2017-10-10 | The Regents Of The University Of Michigan | Physical unclonable function using augmented memory for challenge-response hashing |
| CN104579631A (en) * | 2014-12-15 | 2015-04-29 | 天津大学 | AES (Advanced Encryption Standard) secret key generation structure and method based on latch type voltage sensitive amplifier PUF (Physical Unclonable Function) |
| JP6587188B2 (en) * | 2015-06-18 | 2019-10-09 | パナソニックＩｐマネジメント株式会社 | Random number processing apparatus, integrated circuit card, and random number processing method |
-
2018
- 2018-06-08 CN CN201810586232.8A patent/CN108768619B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521538A (en) * | 2011-12-07 | 2012-06-27 | 浙江大学 | Physical no-cloning function structure based on multi-frequency band |
| CN105743645A (en) * | 2016-01-25 | 2016-07-06 | 清华大学 | PUF (Physical Unclonable Function)-based stream key generation device and method and data encryption and decryption method |
| CN105811923A (en) * | 2016-02-29 | 2016-07-27 | 中国电子科技集团公司第五十八研究所 | Clock duty ratio adjusting circuit |
| CN107483180A (en) * | 2017-08-21 | 2017-12-15 | 湖南大学 | A kind of high stability physics unclonable function circuit and its response production method |
Non-Patent Citations (1)
| Title |
|---|
| "基于CMOS环型振荡器０~100MHz高线性低功耗时钟发生器";刘心彤，李振荣，庄奕琪;《微电子学与计算机》;20180305 * |
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