CN114357539A - Frequency-controllable PUF circuit based on ring oscillator - Google Patents
Frequency-controllable PUF circuit based on ring oscillator Download PDFInfo
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Abstract
The invention provides a ring oscillator PUF circuit with a frequency controllable function, which comprises a ring oscillator array consisting of a plurality of ring oscillators, a path selection register, an iteration control register, two multiplexers, two counters and a comparator for comparing frequencies, wherein the ring oscillator included in the ring oscillator array comprises a plurality of path selection delay units and a two-input NAND gate which are connected in series, and the path selection delay units mainly comprise two parts: and the two multiplexers are connected with the input ends of the two counters after selecting the corresponding two ring oscillator frequencies, and the comparator for comparing the frequencies is connected to the output ends of the two counters and connects the response output end to the path selection register. The invention has the advantages of high safety, strong pressure resistance, high flexibility and the like.
Description
Technical Field
The invention relates to the technical field of integrated circuit anti-counterfeiting PUF circuits, in particular to a ring oscillator PUF circuit with a frequency controllable function.
Background
An emerging chip authentication technology, namely Physical Unclonable Function (PUF), is an anti-counterfeiting technology with randomness developed by the current anti-counterfeiting technology.
The technology can effectively utilize the randomness difference of various circuits in the chip caused by the deviation of the manufacturing process to generate the response signal according to the established principle. This response signal may be considered as a human fingerprint, and if the same stimulus is received, the response signal generated will be different for different chips.
Thus, the rise of PUF technology implies that circuit counterfeiting is increasingly difficult, which is the essence of physical unclonable technology. In addition, the PUF circuit generally has the advantages of small scale, light weight, low power consumption, small area and the like, and is now put into research and development in the production of large-scale mass-production chips, which has great research significance and application value in the field of electronic information.
Currently, PUFs are mainly non-electronic PUFs, analog PUFs and digital PUFs. The digital delay PUF is most widely used, and is mainly realized by utilizing the characteristic that propagation delays of signals in a circuit are different.
As shown in fig. 1, a typical representation of a digital delay PUF is a ring oscillator PUF. The scheme mainly utilizes the manufacturing process difference of two ring oscillator loops to extract different frequency values, if the oscillation frequency of the first ring oscillator loop is less than that of the second ring oscillator loop, the output immediately responds to 0, otherwise, the output immediately responds to 1. The loop delay of the ring oscillator depends on factors such as doping concentration, size and line width of a device, the loop delay of the ring oscillator cannot be completely the same for different PUF chips, and the digital delay PUF extracts the characteristic of the random delay.
However, the frequency of the ring oscillator realized by the scheme is a fixed value, and the fixed value can be easily cracked by the outside, for example, a large amount of response signal data is obtained through a large amount of input excitation, and the relative relation of the frequency magnitude between each two ring oscillators is obtained through modeling analysis. It follows that such PUF schemes that do not control the ring oscillator frequency do not have a high degree of security.
Disclosure of Invention
In order to solve the problem that a frequency-controllable ring oscillator PUF circuit is lacked at home and abroad at the present stage, the invention provides a ring oscillator PUF circuit capable of controlling the frequency of a ring oscillator.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a frequency-controllable PUF circuit based on a ring oscillator comprises a ring oscillator array (the number is more than or equal to 8) consisting of a plurality of ring oscillators, a path selection register, an iteration control register, a first multiplexer (the output end of each ring oscillator is connected to the first multiplexer), a second multiplexer (the output end of each ring oscillator is connected to the second multiplexer), a first counter (the output end of the first multiplexer is connected to the first counter), a second counter (the output end of the second multiplexer is connected to the second counter), and a comparator for comparing frequencies (the output ends of the first counter and the second counter are connected with the comparator, and the output end of the comparator is connected to the path selection register).
As a further improvement of the invention: the ring oscillator included in the ring oscillator array comprises a plurality of path selection delay units and a two-input NAND gate which are connected in series. The path selection delay unit mainly comprises an alternative selector and an inverter. The input end of the whole series-connected sub-circuit is connected with the output end of a two-input NAND gate, the input end of the ring oscillator is connected with one input end of the two-input NAND gate, and the two-input NAND gate plays a role in controlling the enabling of the circuit.
As a further improvement of the invention: the path selection delay unit mainly comprises two parts: an alternative selector and an inverter. The two input ends of the alternative selector are connected and connected with the inverter in series. The output end of each path selection delay unit and the input end of another path selection delay unit are connected end to form a loop. The selection enabling end of the alternative selector in each stage of path selection delay unit is connected with a certain bit of the path selection register in sequence.
As a further improvement of the invention: the input ends of the two multi-path selectors adopt the input ends with the same number as the ring oscillators, and the selection signal ends of the two multi-path selectors are all given by external excitation.
As a further improvement of the invention: the comparator for comparing the frequencies is used for connecting the response output end to the path selection register and increasing the randomness of the path selection of the alternative selector in the corresponding ring oscillator array.
As a further improvement of the invention: and the output end of the iteration control register is connected with the ring oscillator array, the multiplexer, the counter and the comparator, and controls the working state of the controllable ring oscillator PUF circuit.
The invention has the advantages that: on the one hand, the selection signal of the novel path selection delay unit provided by the invention can be maximally randomized under the influence of the output of a comparator, and the path selection of an alternative selector in the delay unit can generate infinite possibilities, so that the frequency of a classical ring oscillation PUF circuit is changed into an unpredictable value with extremely strong randomness, and compared with a classical delay unit, the invention only adopts one selector and one phase inverter, thereby greatly reducing the area and the power consumption of the PUF circuit and providing a powerful guarantee for the integration of the PUF circuit; on the other hand, the iteration control register is additionally added, so that a designer can design the randomization degree of the PUF circuit to the maximum extent, the more times of PUF operation, the more randomized response output signals, and the reasonable design of the value of the iteration control register can further guarantee the anti-cracking pressure resistance of the PUF circuit.
Drawings
Figure 1 is a schematic diagram of the structural principle of a classical ring oscillator PUF scheme.
Fig. 2 is a schematic diagram of the structural principle of the ring oscillator PUF circuit with frequency controllable function of the present invention.
Fig. 3 is a schematic circuit diagram of a ring oscillator and a corresponding path selection delay unit employed in an embodiment of the present invention.
Fig. 4 is a schematic diagram of an implementation process in a specific application example of the present invention.
Detailed Description
The invention is further illustrated in the following description with reference to the figures and the specific examples, without thereby limiting the scope of protection of the invention.
The ring oscillator is essentially composed of an odd number of non-logical series connections, and the number of stages is required to be greater than or equal to 1. During the initial power-up process, a certain value exists at a non-logic input end of the ring oscillator, and then the value at the input end becomes the opposite value after the path propagation through the ring oscillator, and the switching between high and low states is repeatedly carried out according to the process, so that the oscillation phenomenon with the periodic characteristic is formed.
As shown in fig. 2, the ring oscillator PUF circuit with frequency controllable function in this embodiment includes a ring oscillator array (16 in number) composed of a plurality of ring oscillators, a 16-bit path selection register, a 4-bit iteration control register, a first 16-to-1 multiplexer (each ring oscillator output is connected to a first multiplexer), a second 16-to-1 multiplexer (each ring oscillator output is connected to a second multiplexer), a first counter (the first multiplexer output is connected to a first counter), a second counter (the second multiplexer output is connected to a second counter), and a comparator for comparing frequencies (the first counter and the second counter have their outputs connected to the comparator, and the comparator has its output connected to the path selection register).
As shown in fig. 3, the ring oscillator array includes 16 path selection delay units connected in series and a two-input nand gate. The path selection delay unit mainly comprises an alternative selector and an inverter. The input end of the whole series-connected sub-circuit is connected with the output end of a two-input NAND gate, the input end of the ring oscillator is connected with one input end of the two-input NAND gate, and the two-input NAND gate plays a role in controlling the enabling of the circuit; the path selection delay unit mainly comprises two parts: an alternative selector and an inverter. The two input ends of the alternative selector are connected and connected with the inverter in series. The output end of each path selection delay unit and the input end of another path selection delay unit are connected end to form a loop. The selection enabling end of the alternative selector in each stage of path selection delay unit is connected with a certain bit of the path selection register in sequence.
The input ends of the two multi-path selectors adopt the input ends with the same number as the ring oscillators, and the selection signal ends of the two multi-path selectors are all given by external excitation; the comparator for comparing the frequencies is used for connecting the response output end to the path selection register and increasing the randomness of the path selection of the alternative selector in the corresponding ring oscillator array; and the output end of the iteration control register is connected with the ring oscillator array, the multiplexer, the counter and the comparator, and controls the working state of the controllable ring oscillator PUF circuit.
As shown in fig. 4, the implementation process of the present embodiment can be illustrated by the following steps:
firstly, initializing the whole PUF circuit, resetting a 16-bit path selection register to be 0 (indicating that an alternative selector in each ring oscillation will conduct a 0 end), and giving a reasonable value to an iteration control register;
next, the designer inputs 16-bit selection signal values from two 16-to-1 multiplexers to select which two ring oscillators in the 16 ring oscillator arrays to compare their frequencies, and repeats the process 16 times, and the designer can input 16 different selection stimulus values.
The previous step then has specified which two ring oscillators to choose for frequency comparison and gates the input of each of the two alternative selectors in the ring oscillator with the value of each bit in the 16-bit path select register. Both counters will count high pulses of the ring oscillator for a specified time. After the frequency values are calculated, the corresponding "0" or "1" response is obtained via the comparator. The 16 response outputs obtained in sequence can form a 16-bit long PUF response sequence with a randomized characteristic, the 16-bit PUF sequence is overwritten into the 16-bit path selection register to represent that the first iteration is completed, and the iteration control register is subtracted by 1.
At this time, the value in the 16-bit path selection register is updated to a new random PUF sequence, and then the designer can continue to input 16 selection signal values to 2 16-to-1 multiplexers in sequence, obtain a new 16-bit random PUF response sequence through the PUF circuit, and continue to subtract 1 from the iteration control register.
And finally, judging whether the stored value is 0 or not by the iteration control register. If the value at the moment is 0, controlling the whole PUF circuit to stop working; if the value at this time is not 0, the above steps are continued to repeat.
The response output by the controllable PUF circuit is a 16-bit response sequence stored in a 16-bit path selection register, and is highly related to an initial value in the 16-bit path selection register and 16 times of excitation given by a designer. If the external environment adopts an enumeration method to carry out forced cracking, the excitation information needing to be traversed is { iteration times x 216*(15*16)16And assuming that the iteration number is 1, the corresponding cracking excitation will have 8 x 1042Seed growing; if a PUF scheme with 16 ring oscillator arrays of fixed frequency is used, it can be easily broken by enumeration, and only 0.5 × 15 × 16 is traversed 120 times at most. Therefore, compared with a classical ring oscillator PUF scheme, the method not only reduces the area and power consumption of the PUF circuit, but also enables random response information of the PUF circuit to have higher safety and higher voltage resistance.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention, unless the contents of the technical solution of the present invention.
Claims (6)
1. A frequency-controllable PUF circuit based on a ring oscillator is characterized in that: the ring oscillator comprises a ring oscillator array consisting of a plurality of ring oscillators, a path selection register, an iteration control register, two multiplexers, two counters and a comparator for comparing frequencies, wherein the ring oscillator included in the ring oscillator array comprises a plurality of path selection delay units and a two-input NAND gate which are connected in series, and the path selection delay units mainly comprise two parts: and the two multiplexers are connected with the input ends of the two counters after selecting the corresponding two ring oscillator frequencies, and the comparator for comparing the frequencies is connected to the output ends of the two counters and connects the response output end to the path selection register.
2. A ring oscillator based frequency controllable PUF circuit according to claim 1, wherein: the ring oscillator included in the ring oscillator array comprises a plurality of path selection delay units and a two-input NAND gate which are connected in series. The path selection delay unit mainly comprises an alternative selector and an inverter. The input end of the whole series-connected sub-circuit is connected with the output end of a two-input NAND gate, the input end of the ring oscillator is connected with one input end of the two-input NAND gate, and the input NAND gate plays a role in controlling the enabling of the circuit.
3. A ring oscillator based frequency controllable PUF circuit according to claim 1, wherein: the input ends of the two multi-path selectors adopt the input ends with the same number as the ring oscillators, and the selection signal ends of the two multi-path selectors are all given by external excitation.
4. A ring oscillator based frequency controllable PUF circuit according to claim 1, wherein: the comparator for comparing the frequencies is used for connecting the response output end to the path selection register and increasing the randomness of the path selection of the alternative selector in the corresponding ring oscillator array.
5. A ring oscillator based frequency controllable PUF circuit according to claim 1, wherein: and the output end of the iteration control register is connected with the ring oscillator array, the multiplexer, the counter and the comparator, and controls the working state of the controllable ring oscillator PUF circuit.
6. A ring oscillator based frequency controllable PUF circuit according to claim 2, wherein: the path selection delay unit mainly comprises two parts: an alternative selector and an inverter. The two input ends of the alternative selector are connected and connected with the inverter in series. The output end of each path selection delay unit and the input end of another path selection delay unit are connected end to form a loop. The selection enabling end of the alternative selector in each stage of path selection delay unit is connected with a certain bit of the path selection register in sequence.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115459923A (en) * | 2022-08-30 | 2022-12-09 | 武汉科技大学 | Ring oscillator PUF circuit based on memristor and use method thereof |
| CN115632799A (en) * | 2022-12-23 | 2023-01-20 | 湖北工业大学 | Anti-modeling configurable dual-mode PUF structure and configuration method thereof |
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| CN106372539A (en) * | 2016-08-31 | 2017-02-01 | 电子科技大学 | Frequency-variable ring oscillator PUF (Physical Unclonable Function) circuit |
| CN113707201A (en) * | 2021-10-27 | 2021-11-26 | 南京航空航天大学 | Efficient reconfigurable ring oscillator PUF circuit based on RRAM |
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2022
- 2022-01-04 CN CN202210001050.6A patent/CN114357539A/en active Pending
Patent Citations (5)
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| CN103902930A (en) * | 2014-03-10 | 2014-07-02 | 杭州晟元芯片技术有限公司 | Physical unclonable function circuit structure based on ring oscillators |
| CN104200180A (en) * | 2014-07-17 | 2014-12-10 | 南京航空航天大学 | Physical unclonable function based on reconfigurable ring oscillators and generation method of physical unclonable function based on reconfigurable ring oscillators |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115459923A (en) * | 2022-08-30 | 2022-12-09 | 武汉科技大学 | Ring oscillator PUF circuit based on memristor and use method thereof |
| CN115459923B (en) * | 2022-08-30 | 2024-04-26 | 武汉科技大学 | Memristor-based ring oscillator PUF circuit and use method thereof |
| CN115632799A (en) * | 2022-12-23 | 2023-01-20 | 湖北工业大学 | Anti-modeling configurable dual-mode PUF structure and configuration method thereof |
| CN115632799B (en) * | 2022-12-23 | 2023-03-28 | 湖北工业大学 | Anti-modeling configurable dual-mode PUF structure and configuration method thereof |
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Application publication date: 20220415 |