CN115459923A - Ring oscillator PUF circuit based on memristor and use method thereof - Google Patents

Ring oscillator PUF circuit based on memristor and use method thereof Download PDF

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CN115459923A
CN115459923A CN202211057814.XA CN202211057814A CN115459923A CN 115459923 A CN115459923 A CN 115459923A CN 202211057814 A CN202211057814 A CN 202211057814A CN 115459923 A CN115459923 A CN 115459923A
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memristor
ring oscillator
module
oscillator circuit
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CN115459923B (en
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甘朝晖
李江南
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Wuhan University of Science and Engineering WUSE
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

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Abstract

The invention relates to a ring oscillator PUF circuit based on a memristor and a using method thereof. The technical scheme is as follows: the ring oscillator PUF circuit is composed of a random delay circuit (101), a 1 st ring oscillator circuit (102), a 2 nd ring oscillator circuit (106), a 1 st counter (103), a 2 nd counter (105) and a digital comparator (104). The square wave frequency produced by the two ring oscillator circuits depends on the resistance of the module memristors (404) in the memristor modules (304). The random frequency response method takes the randomness of high-resistance distribution of the memristors (404) in the memristor modules (304) as a main entropy source, selects the memristors (404) according to an input excitation voltage signal under the action of a random delay circuit (101), randomly reduces the resistance value of the selected memristors (404), and then compares the square wave frequencies generated by the two ring oscillator circuits to obtain the response. The invention has the characteristics of strong machine learning resistance, low hardware consumption and good core performance index.

Description

Ring oscillator PUF circuit based on memristor and use method thereof
Technical Field
The invention belongs to the technical field of PUF circuits. In particular to a ring oscillator PUF circuit based on a memristor and a use method thereof.
Background
Physically Unclonable Functions (PUFs) are widely regarded as a new hardware security protection scheme in the field of hardware security. The PUF is a concept created by researchers inspired by human fingerprints, and the fingerprints of each person are different, so the fingerprints can be used as unique identifiers of human bodies, the same batch of products produced by hardware devices in the same production process have slight differences in parameters, the differences are random and uncontrollable, and the PUF extracts the differences as the fingerprints of the hardware devices, namely, the unique identifiers of the hardware devices. A PUF has an input and an output signal, the input signal of which is called a stimulus (Challenge) and the output signal is called a Response (Response). Inputting any stimulus will produce a unique and unpredictable response, each with its unique corresponding response. One stimulus and its corresponding Response are called stimulus Response Pairs (CRPs). The PUF has the characteristics of uniqueness, randomness and the like, namely the PUF is unique once produced and cannot be copied by manufacturers, and by utilizing the characteristics, the PUF is mainly used in the field of hardware security and particularly has unique advantages in the security problems of hardware equipment identity authentication, anti-cloning and the like.
The PUF can be divided into a strong PUF and a weak PUF according to the number of CRPs, and the strong PUF has a large number of CRPs and is generally applied to identity authentication; weak PUFs typically have only a small number of CRPs and are used in key generation. A ring oscillator PUF (RO PUF) is a classical strong PUF. The RO PUF has high reliability and does not require strict symmetry in circuit structure, which reduces the difficulty of manufacturing, but the RO PUF needs to select different two ring oscillator circuits to compare each time it generates a different response, and thus has high hardware consumption and power consumption.
Whether a strong PUF or a weak PUF, once an adversary can predict their CRPs with high accuracy, they are no longer secure. Machine learning can realize cloning of PUF mathematical models, and CRPs of the PUF mathematical models can be predicted with high precision, and particularly, the effect of machine learning modeling attack is better when the circuit linear structure is stronger and the CRPs are used for most of more strong PUFs. Researchers find through experiments that the accuracy of machine learning modeling of the existing main strong PUFs such as the Arbiter PUF and the RO PUF can reach over 90%.
Loong J T H et al (Loong J T H, hashimNAN, hamid S, et al. Performance analysis of CMOS-memrisorhybriding amorphous functional (RO-PUF) [ C ]//2016IEEE International Conference on Semiconductor Electronics (ICSE), IEEE, 2016) propose a memristor-based RO PUF circuit. According to the design, a memristor is used for replacing a PMOS transistor of a CMOS inverter in a traditional RO PUF circuit, and the characteristic that the resistance value change of the memristor has nonlinearity is utilized, so that the oscillation frequency of an oscillator is more random, and the PUF circuit has better randomness. The PUF circuit still has the disadvantage that the conventional RO PUF circuit is difficult to resist machine learning modeling attacks.
The patent technology of 'strong PUF based on memristor' (CN 109495272A) utilizes 2T2R as a basic unit of a memristor array, generates a unique response value by comparing currents of two columns of paths in the memristor array, has the characteristics of high area utilization rate, configurability and reutilization, and has excellent randomness and modeling attack resistance. However, the strong PUF circuit needs to adopt a 2T2R memristor array, and the current comparison mode of the strong PUF circuit has higher requirement on the precision of a reading circuit; meanwhile, the anti-attack capability of the model is realized only by strong randomness, and the attack of machine learning cannot be completely avoided in fact.
The patent technology of 'a high-efficiency reconfigurable ring oscillator PUF circuit based on RRAM' (CN 113707201A) combines an RRAM array and a ring oscillator PUF circuit, and utilizes random distribution of resistance values of the RRAM in a high-resistance state as an entropy source of the PUF circuit. The PUF circuit selects corresponding RRAMs in the RRAM array to participate in the ring oscillator circuit through a row decoder and a column selector according to applied excitation, and finally, pulse signals generated by the ring oscillator circuit are counted by two counters respectively, and the response is obtained by comparing the count values. The circuit design utilizes the RRAM array form, greatly reduces the circuit area and realizes the machine learning resistance through reconstruction. However, the PUF circuit selects part of RRAMs in the RRAM array to participate in the ring oscillator circuit each time according to excitation, and unselected RRAMs cause waste of entropy sources and poor core performance indexes.
The patent technology of 'variable frequency ring oscillator PUF circuit' (CN 106372539A) can change the oscillation frequency generated by an oscillator by configuring the number of inverters in the ring oscillator, and because the oscillation frequency of the oscillator is not fixed, an attacker is difficult to establish a corresponding mathematical model by a mathematical modeling method, so that the PUF circuit has strong machine learning resistance. However, each time the PUF circuit generates a different response, two different ring oscillators need to be selected for comparison, and additional resources are needed to implement configuration of the ring oscillators, so that the hardware consumption of the PUF circuit is large.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a memristor-based ring oscillator PUF circuit with strong machine learning resistance, low hardware consumption and good core performance index and a using method thereof.
In order to achieve the purpose, the invention adopts the technical scheme that:
the memristor-based ring oscillator PUF circuit is composed of a random delay circuit, a 1 st ring oscillator circuit, a 2 nd ring oscillator circuit, a 1 st counter, a 2 nd counter and a digital comparator.
Terminal V of random delay circuit pulse And voltage input terminal V pl Terminal V of connection, random delay circuit c12 、……、V ci2 、……、V cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal V of random delay circuit delay And terminal A of the 1 st ring oscillator circuit dly1 Terminal A of the 2 nd ring oscillator circuit dly2 Are respectively connected.
Terminal A of the 1 st ring oscillator circuit vdd1 Terminal A of the 2 nd ring oscillator circuit vdd2 Respectively connected with voltage input terminal V vdd Connecting terminal A of the 1 st ring oscillator circuit chlg1 Terminal A of the 2 nd ring oscillator circuit chlg2 Respectively connected with voltage input terminal V chlg Connecting, terminal A of the 1 st ring oscillator circuit rd1 Terminal A of the 2 nd ring oscillator circuit rd2 Respectively connected with voltage input terminal V rd Connected, 1 st ringTerminal A of oscillator circuit cr01 Terminal A of the 2 nd ring oscillator circuit cr02 Respectively connected with voltage input terminal V cr0 Connecting, terminal A of the 1 st ring oscillator circuit cr11 Terminal A of the 2 nd ring oscillator circuit cr12 Are respectively connected with a voltage input terminal V cr1 Connecting; terminal A of the 1 st ring oscillator circuit c11 、……、A ci1 、……、A cN1 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connected, terminal A of 2 nd ring oscillator circuit c12 、……、A ci2 、……、A cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal A of the 1 st ring oscillator circuit rs1 Terminal A of the 2 nd ring oscillator circuit rs2 Are respectively connected with a voltage input terminal V rs Connecting; terminal A of the 1 st ring oscillator circuit cr21 Terminal A of the 2 nd ring oscillator circuit cr22 Are respectively connected with a voltage input terminal V cr2 Connecting; terminal f of the 1 st ring oscillator circuit out1 And terminal A of the 1 st counter 10 Connecting terminal f of 2 nd ring oscillator circuit out2 And terminal A of the 2 nd counter 20 And (4) connecting.
Terminal A of 1 st counter 11 And terminal IN of a digital comparator 0 Connected, terminal A of the 2 nd counter 21 And terminal IN of digital comparator 1 Terminal R of a connected, digital comparator out And outputting the response voltage.
At voltage input terminal V pl 、V vdd 、V chlg 、V rd 、V cr0 、V cr1 、V rs 、V cr2 A voltage signal U corresponding to the voltage applied between the terminals GND pl 、U vdd 、U chlg 、U rd 、U cr0 、U cr1 、U rs 、U cr2 At a voltage input terminal V c1 、……、V ci 、……、V cN A voltage signal U corresponding to the voltage applied between the terminals GND c1 、……、U ci 、……、U cN 。
Terminal R of digital comparator out And outputting the response voltage.
The random delay circuit consists of N delay units and NMOS transistors, wherein N is an odd number; the terminal OUT of the 1 st delay unit is connected to the terminal IN of the 2 nd delay unit, … …, the terminal OUT of the i-1 st delay unit is connected to the terminal IN of the i-th delay unit, … …, the terminal OUT of the N-1 st delay unit is connected to the terminal IN of the N-th delay unit, and the terminal OUT of the N-th delay unit is connected to the drain of the NMOS transistor.
The terminal IN of the 1 st delay unit is respectively connected with the terminals A of the memristors of the two delay circuits R0 Terminal A of memristor connected with two delay circuits R1 Connected to the 1 st delay circuit gate at the terminals 1 _chanand 0 _chan; the 2 nd delay unit, … …, the i-th delay unit, … … and the Nth delay unit have the same structure as the 1 st delay unit.
Terminal IN of 1 st delay unit and terminal V of random delay circuit pulse Connecting the terminal OUT of the Nth delay unit with the terminal V of the random delay circuit delay Connecting; terminals SEL, … … of the 1 st delay unit, terminals SEL, … … of the i-th delay unit, and terminal SEL of the N-th delay unit, and terminal V of the corresponding random delay circuit c12 、……、V ci2 、……、V cN2 And (4) connecting.
The 1 st ring oscillator circuit consists of N inverters and N memristor modules, wherein N is an odd number; a terminal OUT of the 1 st inverter is connected to a terminal IN of the 2 nd inverter, … …, a terminal OUT of the i-1 st inverter is connected to a terminal IN of the i th inverter, … …, and a terminal OUT of the N-1 st inverter is connected to a terminal IN of the N th inverter; the terminal IN of the 1 st inverter is connected to the terminal OUT of the Nth inverter, and the terminal OUT of the Nth inverter is connected to the terminal f of the 1 st ring oscillator circuit out1 And (4) connecting.
Source of NMOS transistor of 1 st inverter … …, source of NMOS transistor of I-th inverter … …, source of NMOS transistor of N-th inverter and terminal I of corresponding 1 st memristor module out1 … … and ith memristor dieTerminal I of block outi … …, terminal I of Nth memristor module outN Connecting; the source of the PMOS transistor of the 1 st inverter … …, the source of the PMOS transistor of the i-th inverter … …, and the source of the PMOS transistor of the N-th inverter are connected to the terminal A of the 1 st ring oscillator circuit vdd1 And (4) connecting.
Terminal V of 1 st memristor module chlg1 … …, terminal V of ith memristor module chlgi … …, terminal V of nth memristor module chlgN Respectively connected with terminals A of the 1 st ring oscillator circuit chlg1 Connecting, terminal V of memristor Module 1 st rd1 … …, terminal V of ith memristor module rdi … …, terminal V of Nth memristor module rdN Respectively connected with terminals A of the 1 st ring oscillator circuit rd1 Connecting, 1 st memristor Module terminal V cr01 … …, terminal V of ith memristor module cr0i … …, terminal V of Nth memristor module cr0N Respectively connected with terminals A of the 1 st ring oscillator circuit cr01 Connecting, terminal V of memristor Module 1 st dly1 … …, terminal V of i-th memristor module dlyi … …, terminal V of nth memristor module dlyN Respectively connected with terminals A of the 1 st ring oscillator circuit dly1 Connecting, terminal V of memristor Module 1 st cr11 … …, terminal V of i-th memristor module cr1i … …, terminal V of nth memristor module cr1N Respectively connected with terminals A of the 1 st ring oscillator circuit cr11 Connecting, terminal V of memristor Module 1 st c11 … …, terminal V of ith memristor module ci1 … …, terminal V of nth memristor module cN1 Terminal A of the corresponding 1 st ring oscillator circuit c11 、……、A ci1 、……、A cN1 Connecting; terminal V of 1 st memristor module rs1 … …, terminal V of ith memristor module rsi … …, terminal V of nth memristor module rsN Respectively connected with terminals A of the 1 st ring oscillator circuit rs1 Connecting, 1 st memristor Module terminal V cr21 … …, terminal V of i-th memristor module cr2i … …, terminal V of nth memristor module cr2N Respectively connected with terminals A of the 1 st ring oscillator circuit cr21 And (4) connecting.
The 2 nd ring oscillator circuit has the same structure as the 1 st ring oscillator circuit.
The structure of the 1 st memristor module is that the terminal OUT of the 1 st gating device is connected with the terminal 0 of the 2 nd gating device, the terminal 1 of the 2 nd gating device is connected with GND, the terminal OUT of the 2 nd gating device is connected with the terminal 1 of the 3 rd gating device, the terminal 0 of the 3 rd gating device is connected with GND, and the terminal OUT of the 3 rd gating device is connected with the terminal R of the module memristor M0 Connecting; drain of NMOS transistor and terminal R of module memristor M0 Connected, source of NMOS transistor and terminal R of module memristor M1 Connecting; terminal IN of 1 st shunt and terminal R of module memristor M1 Connection, terminal 1 of the 1 st splitter chan is connected to terminal IN of the 2 nd splitter; terminal 1 of 2 nd splitter chan and terminal I of mirror current source ref Connecting terminal 0 of 2 nd shunt with terminal R of current limiting resistor 0 Terminal R of connecting and current limiting resistor 1 Is connected to GND.
Terminals 1_CHAN, 0_CHAN, SEL of the 1 st gate and a terminal V corresponding to the 1 st memristor module chlg1 、V rd1 、V cr01 Connected, terminal SEL of 2 nd gate and terminal V of 1 st memristor module dly1 Connected, terminal SEL of 3 rd gate and terminal V of 1 st memristor module cr11 Connecting; gate of NMOS transistor and terminal V of 1 st memristor module c11 Connecting; terminal SEL of 1 st shunt and terminal V of 1 st memristor module cr11 Connecting terminal 0 \ CHAN of the 1 st shunt with terminal V of the 1 st memristor module rs1 Connecting terminal SEL of 2 nd shunt with terminal V of 1 st memristor module cr21 Connecting; terminal I of mirror current source out With terminal I of 1 st memristor module out1 And (4) connecting.
The 2 nd memristor module, … …, the ith memristor module, … … and the Nth memristor module are all the same as the 1 st memristor module in structure.
The delay circuit memristor is the same as the module memristor, and both the delay circuit memristor and the module memristor are memristors with threshold voltage; the initial states of the delay circuit memristor and the module memristor are both in a high resistance state.
The use method of the memristor-based ring oscillator PUF circuit comprises the following steps:
step one, resetting all memristors
At voltage input terminal V cr1 A voltage signal U of low level is applied between the terminal and the GND cr1 At a voltage input terminal V rs A high-level voltage signal U is applied between the terminal and the GND rs No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Step two, applying excitation
At voltage input terminal V pl 、V chlg 、V cr0 、V cr1 A high-level voltage signal U corresponding to the voltage applied between the terminals GND pl 、U chlg 、U cr0 、U cr1 At a voltage input terminal V c1 、……、V ci 、……、V cN A high-level or low-level excitation voltage signal U corresponding to the application of the terminal GND c1 、……、U ci 、……、U cN (ii) a At voltage input terminal V cr2 A voltage signal U of low level is applied between the terminal and the GND cr2 No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Step three, responding to output
At a voltage input terminal V vdd 、V rd 、V cr1 、V cr2 A high-level voltage signal U corresponding to the application of the voltage between the terminals GND vdd 、U rd 、U cr1 、U cr2 At a voltage input terminal V cr0 A voltage signal U of low level is applied between the terminal and the GND cr0 No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Terminal R of digital comparator out And outputting the response voltage.
The invention adopts the resistance distribution of the module memristor when the module memristor is in a high resistance stateThe randomness of the memristor-based ring oscillator PUF circuit is used as a main entropy source of the memristor-based ring oscillator PUF circuit, and in the first step, relevant voltage signals are applied to memristor modules, so that all module memristors in the memristor-based ring oscillator PUF circuit are reset to be in a high-resistance state. In the second step, the ring oscillator PUF circuit based on the memristor selects part of module memristors in the 1 st ring oscillator circuit and the 2 nd ring oscillator circuit according to the input excitation voltage signal, and a high-level voltage signal U is applied to the selected module memristors chlg Making the voltage signal U at high level under the action of the random delay circuit chlg The duration time applied to the module memristors is random, and the selected module memristors conduct one-time random resistance reduction in a high-resistance state. In the third step, the 1 st ring oscillator circuit and the 2 nd ring oscillator circuit start to oscillate, pulses of square waves generated by the 1 st ring oscillator circuit and the 2 nd ring oscillator circuit are counted by the 1 st counter and the 2 nd counter respectively, and finally, the digital comparator compares the counted values to obtain response.
Due to the adoption of the technical scheme, the invention has the following positive effects:
in the second step, the annular oscillator PUF circuit based on the memristor selects the module memristor in the memristor module according to the applied excitation voltage signal, the random resistance reduction is performed on the selected module memristor for the first time, the excitation voltage signals are different, the selected module memristors are also different, the resistance reduction amount of the selected module memristors is also different, and therefore when the excitation voltage signals are different, the resistance values of the module memristors in the annular oscillator PUF circuit based on the memristors are also different, namely the parameters of the annular oscillator PUF circuit based on the memristors are different, and the parameters of the annular oscillator PUF circuit based on the memristors are also changed along with the change of the excitation voltage signals, so that a machine learning algorithm is difficult to accurately establish a mathematical model of the annular oscillator PUF circuit based on the memristors, and therefore the machine learning resistance capability is obvious.
In the invention, the randomness of resistance distribution when a module memristor in a memristor module is in a high-resistance state is used as an entropy source of the annular oscillator PUF circuit based on the memristor, and the randomness of resistance distribution when a module memristor in a random delay circuit is in the high-resistance state is also used as an entropy source of the annular oscillator PUF circuit based on the memristor, so that the random delay circuit has double entropy sources and good core performance indexes.
According to the invention, a multi-bit CRP pair can be generated only by two ring oscillator circuits, and the number of memristor modules corresponding to inverters and inverters in the 1 st ring oscillator circuit and the 2 nd ring oscillator circuit is increased only by increasing the number of bits of the CRP pair, so that the expansibility is strong and the hardware consumption is low.
Therefore, the invention has the characteristics of strong machine learning resistance, low hardware consumption and good core performance index.
Drawings
FIG. 1 is a schematic of one embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure of the random delay circuit 101 of FIG. 1;
FIG. 3 is a schematic diagram of one configuration of the 1 st ring oscillator circuit 102 of FIG. 1;
FIG. 4 is a schematic diagram of one configuration of the 1 st memristor module 304 of FIG. 3;
FIG. 5 is another schematic structural view of the present invention;
FIG. 6 is a schematic diagram of a structure of the random delay circuit 101 shown in FIG. 5;
FIG. 7 is a schematic diagram of one configuration of the 1 st ring oscillator circuit 102 of FIG. 5;
FIG. 8 is a schematic view of another embodiment of the present invention;
FIG. 9 is a schematic diagram of a structure of the random delay circuit 101 shown in FIG. 8;
FIG. 10 is a schematic diagram of one configuration of the 1 st ring oscillator circuit 102 of FIG. 8;
Detailed Description
The invention is further described with reference to the following figures and detailed description, without limiting its scope.
A ring oscillator (PUF) circuit based on a memristor and a using method thereof.
As shown in fig. 1, the memristor-based ring oscillator PUF circuit is composed of a random delay circuit 101, a 1 st ring oscillator circuit 102, a 2 nd ring oscillator circuit 106, a 1 st counter 103, a 2 nd counter 105, and a digital comparator 104.
As shown in FIG. 1, terminal V of random delay circuit 101 pulse And voltage input terminal V pl Terminal V of connection, random delay circuit 101 c12 、……、V ci2 、……、V cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal V of random delay circuit 101 delay And terminal A of the 1 st ring oscillator circuit 102 dly1 Terminal A of the 2 nd ring oscillator circuit 106 dly2 Are respectively connected.
Terminal A of 1 st ring oscillator circuit 102 vdd1 Terminal A of the 2 nd ring oscillator circuit 106 vdd2 Respectively connected with voltage input terminal V vdd Connected to terminal A of 1 st ring oscillator circuit 102 chlg1 Terminal A of the 2 nd ring oscillator circuit 106 chlg2 Are respectively connected with a voltage input terminal V chlg Connected to terminal A of 1 st ring oscillator circuit 102 rd1 Terminal A of the 2 nd ring oscillator circuit 106 rd2 Are respectively connected with a voltage input terminal V rd Connected, terminal A of 1 st ring oscillator circuit 102 cr01 Terminal A of the 2 nd ring oscillator circuit 106 cr02 Respectively connected with voltage input terminal V cr0 Connected, terminal A of 1 st ring oscillator circuit 102 cr11 Terminal A of the 2 nd ring oscillator circuit 106 cr12 Respectively connected with voltage input terminal V cr1 Connecting; terminal A of 1 st ring oscillator circuit 102 c11 、……、A ci1 、……、A cN1 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connected, terminal A of 2 nd ring oscillator circuit 106 c12 、……、A ci2 、……、A cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal A of 1 st ring oscillator circuit 102 rs1 2 nd ring oscillator circuit106 terminal a rs2 Respectively connected with voltage input terminal V rs Connecting; terminal A of 1 st ring oscillator circuit 102 cr21 Terminal A of the 2 nd ring oscillator circuit 106 cr22 Are respectively connected with a voltage input terminal V cr2 Connecting; terminal f of 1 st ring oscillator circuit 102 out1 And terminal A of the 1 st counter 103 10 Connected, terminal f of 2 nd ring oscillator circuit 106 out2 And terminal A of the 2 nd counter 105 20 And (4) connecting.
Terminal A of 1 st counter 103 11 And terminal IN of digital comparator 104 0 Connected, terminal A of the 2 nd counter 105 21 And terminal IN of digital comparator 104 1 To terminal R of digital comparator 104 out And outputting the response voltage.
At voltage input terminal V pl 、V vdd 、V chlg 、V rd 、V cr0 、V cr1 、V rs 、V cr2 A voltage signal U corresponding to the voltage applied between the terminals GND pl 、U vdd 、U chlg 、U rd 、U cr0 、U cr1 、U rs 、U cr2 At a voltage input terminal V c1 、……、V ci 、……、V cN A voltage signal U corresponding to the voltage applied between the terminals GND c1 、……、U ci 、……、U cN 。
Terminal R of digital comparator 104 out And outputting the response voltage.
As shown in fig. 2, the random delay circuit 101 is composed of N delay cells 202 and NMOS transistors 204, where N is an odd number; the terminal OUT of the 1 st delay cell 202 is connected to the terminal IN of the 2 nd delay cell 202, … …, the terminal OUT of the i-1 th delay cell 202 is connected to the terminal IN of the i-th delay cell 202, … …, the terminal OUT of the N-1 th delay cell 202 is connected to the terminal IN of the N-th delay cell 202, and the terminal OUT of the N-th delay cell 202 is connected to the drain of the NMOS transistor 204.
As shown IN FIG. 2, the terminals IN of the 1 st delay cell 202 are respectively connected with the terminals A of the two delay circuit memristors 201 R0 Connecting two delay circuit memristors 201Terminal A R1 Connected to the terminal 1 _chanand the terminal 0 _chanof the 1 st delay line gate 203; the 2 nd delay units 202, … …, the i-th delay units 202, … …, and the N-th delay unit 202 have the same structure as the 1 st delay unit 202.
As shown IN FIG. 2, the terminal IN of the 1 st delay cell 202 and the terminal V of the random delay circuit 101 pulse Connected, the terminal OUT of the Nth delay cell 202 and the terminal V of the random delay circuit 101 delay Connecting; terminals SEL, … … of 1 st delay unit 202, terminals SEL, … … of i-th delay unit 202, and terminal SEL of N-th delay unit 202, and corresponding terminal V of random delay circuit 101 c12 、……、V ci2 、……、V cN2 And (4) connecting.
As shown in fig. 3, the 1 st ring oscillator circuit 102 is composed of N inverters 301 and N memristor modules 304, N being an odd number; the terminal OUT of the 1 st inverter 301 is connected to the terminal IN of the 2 nd inverter 301, … …, the terminal OUT of the i-1 st inverter 301 is connected to the terminal IN of the i-th inverter 301, … …, and the terminal OUT of the N-1 st inverter 301 is connected to the terminal IN of the N-1 st inverter 301; the terminal IN of the 1 st inverter 301 is connected to the terminal OUT of the Nth inverter 301, and the terminal OUT of the Nth inverter 301 is connected to the terminal f of the 1 st ring oscillator circuit 102 out1 And (4) connecting.
As shown in fig. 3, the source of the NMOS transistor 303 of the 1 st inverter 301, … …, the source of the NMOS transistor 303 of the I-th inverter 301, … …, the source of the NMOS transistor 303 of the N-th inverter 301, and the corresponding terminal I of the 1 st memristor module 304 out1 … …, terminal I of ith memristor module 304 outi … …, terminal I of Nth memristor module 304 outN Connecting; the source of the PMOS transistor 302 of the 1 st inverter 301, … …, the source of the PMOS transistor 302 of the i-th inverter 301, … …, and the source of the PMOS transistor 302 of the N-th inverter 301 are connected to the terminal a of the 1 st ring oscillator circuit 102 vdd1 And (4) connecting.
As shown in FIG. 3, the terminal V of the 1 st memristor Module 304 chlg1 … …, terminal V of ith memristor module 304 chlgi … …, the Nth memristor module 304V chlgN Respectively connected with terminals A of the 1 st ring oscillator circuit 102 chlg1 Connecting, terminal V of memristor Module 304 1 rd1 … …, terminal V of ith memristor module 304 rdi … …, terminal V of nth memristor module 304 rdN Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rd1 Connecting, terminal V of memristor Module 304 1 cr01 … …, terminal V of ith memristor module 304 cr0i … …, terminal V of nth memristor module 304 cr0N Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr01 Connecting, terminal V of the 1 st memristor module 304 dly1 … …, terminal V of ith memristor module 304 dlyi … …, terminal V of nth memristor module 304 dlyN Respectively connected with terminals A of the 1 st ring oscillator circuit 102 dly1 Connecting, terminal V of the 1 st memristor module 304 cr11 … …, terminal V of ith memristor module 304 cr1i … …, terminal V of nth memristor module 304 cr1N Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr11 Connecting, terminal V of memristor Module 304 1 c11 … …, terminal V of ith memristor module 304 ci1 … …, terminal V of Nth memristor module 304 cN1 Corresponding terminal A of the 1 st ring oscillator circuit 102 c11 、……、A ci1 、……、A cN1 Connecting; terminal V of 1 st memristor module 304 rs1 … …, terminal V of ith memristor module 304 rsi … …, terminal V of nth memristor module 304 rsN Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rs1 Connecting, terminal V of memristor Module 304 1 cr21 … …, terminal V of ith memristor module 304 cr2i … …, terminal V of nth memristor module 304 cr2N Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr21 And (4) connecting.
The 2 nd ring oscillator circuit 106 is identical in structure to the 1 st ring oscillator circuit 102.
As shown in FIG. 4, the 1 st memristor module 304 may be configured with the terminal OUT of the 1 st gate 401 and the terminal of the 2 nd gate 402Sub 0 _CHANconnection, terminal 1 _CHANof the 2 nd gate 402 is connected to GND, terminal OUT of the 2 nd gate 402 is connected to terminal 1 _CHANof the 3 rd gate 403, terminal 0 _CHANof the 3 rd gate 403 is connected to GND, and terminal OUT of the 3 rd gate 403 is connected to terminal R of the module memristor 404 M0 Connecting; the drain of the NMOS transistor 409 and the terminal R of the module memristor 404 M0 Connected, the source of the NMOS transistor 409 and the terminal R of the module memristor 404 M1 Connecting; terminal IN of 1 st shunt 405 and terminal R of module memristor 404 M1 Connected, terminal 1_chan of 1 st splitter 405 is connected to terminal IN of 2 nd splitter 406; terminal 1 of splitter 406 and terminal I of mirror current source 407 ref Terminal 0 \\Chanof shunt 2 406 is connected to terminal R of current limiting resistor 408 0 Terminal R of connecting, current limiting resistor 408 1 Is connected to GND.
As shown in FIG. 4, the terminals 1_CHAN, 0_CHAN, SEL of the 1 st gate 401 correspond to the terminal V of the 1 st memristor module 304 chlg1 、V rd1 、V cr01 Connecting, the terminal SEL of the 2 nd gate 402 with the terminal V of the 1 st memristor module 304 dly1 Connected, the terminal SEL of the 3 rd gate 403 and the terminal V of the 1 st memristor module 304 cr11 Connecting; the gate of the NMOS transistor 409 and the terminal V of the 1 st memristor module 304 c11 Connecting; terminal SEL of 1 st shunt 405 and terminal V of 1 st memristor module 304 cr11 Connect terminal 0 \ u CHAN of 1 st shunt 405 with terminal V of 1 st memristor module 304 rs1 Connecting terminal SEL of 2 nd shunt 406 with terminal V of 1 st memristor module 304 cr21 Connecting; terminal I of mirror current source 407 out With terminal I of the 1 st memristor Module 304 out1 And (4) connecting.
The 2 nd memristor modules 304, … …, the ith memristor module 304, … …, and the nth memristor module 304 are all the same as the 1 st memristor module 304 in structure.
The delay circuit memristor 201 is the same as the module memristor 404, and both the delay circuit memristor and the module memristor are memristors with threshold voltages; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in a high resistance state.
The use method of the memristor-based ring oscillator PUF circuit comprises the following steps:
step one, resetting all memristors
At voltage input terminal V cr1 A voltage signal U of low level is applied between the terminal GND and the ground cr1 At a voltage input terminal V rs A high-level voltage signal U is applied between the terminal and the GND rs No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Step two, excitation is applied
At voltage input terminal V pl 、V chlg 、V cr0 、V cr1 A high-level voltage signal U corresponding to the voltage applied between the terminals GND pl 、U chlg 、U cr0 、U cr1 At a voltage input terminal V c1 、……、V ci 、……、V cN A high-level or low-level excitation voltage signal U corresponding to the application of the terminal GND c1 、……、U ci 、……、U cN (ii) a At voltage input terminal V cr2 A voltage signal U of low level is applied between the terminal and the GND cr2 No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Step three, responding to output
At voltage input terminal V vdd 、V rd 、V cr1 、V cr2 A high-level voltage signal U corresponding to the voltage applied between the terminals GND vdd 、U rd 、U cr1 、U cr2 At a voltage input terminal V cr0 A voltage signal U of low level is applied between the terminal and the GND cr0 No voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Terminal R of digital comparator 104 out And outputting the response voltage.
Example 1
A ring oscillator (PUF) circuit based on a memristor and a using method thereof.
As shown in fig. 5, the memristor-based ring oscillator PUF circuit is composed of a random delay circuit 101, a 1 st ring oscillator circuit 102, a 2 nd ring oscillator circuit 106, a 1 st counter 103, a 2 nd counter 105, and a digital comparator 104.
As shown in FIG. 5, terminal V of random delay circuit 101 pulse And a voltage input terminal V pl Terminal V of connection, random delay circuit 101 c12 、V c22 、V c32 With corresponding voltage input terminal V c1 、V c2 、V c3 Connecting; terminal V of random delay circuit 101 delay And terminal A of the 1 st ring oscillator circuit 102 dly1 Terminal A of the 2 nd ring oscillator circuit 106 dly2 Are respectively connected.
Terminal A of 1 st ring oscillator circuit 102 vdd1 Terminal A of the 2 nd ring oscillator circuit 106 vdd2 Respectively connected with voltage input terminal V vdd Connected, terminal A of 1 st ring oscillator circuit 102 chlg1 Terminal A of the 2 nd ring oscillator circuit 106 chlg2 Respectively connected with voltage input terminal V chlg Connected, terminal A of 1 st ring oscillator circuit 102 rd1 Terminal A of the 2 nd ring oscillator circuit 106 rd2 Respectively connected with voltage input terminal V rd Connected, terminal A of 1 st ring oscillator circuit 102 cr01 Terminal A of the 2 nd ring oscillator circuit 106 cr02 Respectively connected with voltage input terminal V cr0 Connected, terminal A of 1 st ring oscillator circuit 102 cr11 Terminal A of the 2 nd ring oscillator circuit 106 cr12 Respectively connected with voltage input terminal V cr1 Connecting; terminal A of 1 st ring oscillator circuit 102 c11 、A c21 、A c31 With corresponding voltage input terminal V c1 、V c2 、V c3 Connected, terminal A of 2 nd ring oscillator circuit 106 c12 、A c22 、A c32 With corresponding voltage input terminal V c1 、V c2 、V c3 Connecting; terminal A of 1 st ring oscillator circuit 102 rs1 Terminal A of the 2 nd ring oscillator circuit 106 rs2 Respectively connected with voltage input terminal V rs Connecting; terminal A of 1 st ring oscillator circuit 102 cr21 Terminal A of the 2 nd ring oscillator circuit 106 cr22 Respectively with electricityVoltage input terminal V cr2 Connecting; terminal f of 1 st ring oscillator circuit 102 out1 And terminal A of the 1 st counter 103 10 Connected to terminal f of 2 nd ring oscillator circuit 106 out2 And terminal A of the 2 nd counter 105 20 And (4) connecting.
Terminal A of 1 st counter 103 11 And terminal IN of digital comparator 104 0 Connected, terminal A of the 2 nd counter 105 21 And terminal IN of digital comparator 104 1 To terminal R of digital comparator 104 out And outputting the response voltage.
At voltage input terminal V pl 、V vdd 、V chlg 、V rd 、V cr0 、V cr1 、V rs 、V cr2 A voltage signal U corresponding to the voltage applied between the terminals GND pl 、U vdd 、U chlg 、U rd 、U cr0 、U cr1 、U rs 、U cr2 At voltage input terminal V c1 、V c2 、V c3 A voltage signal U corresponding to the voltage applied between the terminals GND c1 、U c2 、U c3 。
Terminal R of digital comparator 104 out And outputting the response voltage.
As shown in fig. 6, the random delay circuit 101 is composed of 3 delay cells 202 and NMOS transistors 204; the terminal OUT of the 1 st delay cell 202 is connected to the terminal IN of the 2 nd delay cell 202, the terminal OUT of the 2 nd delay cell 202 is connected to the terminal IN of the 3 rd delay cell 202, and the terminal OUT of the 3 rd delay cell 202 is connected to the drain of the NMOS transistor 204.
As shown IN FIG. 6, the terminals IN of the 1 st delay cell 202 are respectively connected with the terminals A of the two delay circuit memristors 201 R0 Connected, terminal A of two delay circuit memristors 201 R1 Connected to the terminal 1 _chanand the terminal 0 _chanof the 1 st delay line gate 203; the 2 nd delay unit 202 and the 3 rd delay unit 202 have the same structure as the 1 st delay unit 202.
As shown IN FIG. 6, the terminal IN of the 1 st delay cell 202 and the terminal V of the random delay circuit 101 pulse Connected to delay unit 3 202Terminal OUT and terminal V of random delay circuit 101 delay Connecting; the terminal SEL of the 1 st delay unit 202, the terminal SEL of the 2 nd delay unit 202, the terminal SEL of the 3 rd delay unit 202, and the corresponding terminal V of the random delay circuit 101 c12 、V c22 、V c32 And (4) connecting.
As shown in fig. 7, the 1 st ring oscillator circuit 102 is composed of 3 inverters 301 and 3 memristor modules 304; the terminal OUT of the 1 st inverter 301 is connected to the terminal IN of the 2 nd inverter 301, and the terminal OUT of the 2 nd inverter 301 is connected to the terminal IN of the 3 rd inverter 301; the terminal IN of the 1 st inverter 301 is connected to the terminal OUT of the 3 rd inverter 301, and the terminal OUT of the 3 rd inverter 301 is connected to the terminal f of the 1 st ring oscillator circuit 102 out1 And (4) connecting.
As shown in fig. 7, the source of the NMOS transistor 303 of the 1 st inverter 301, the source of the NMOS transistor 303 of the 2 nd inverter 301, the source of the NMOS transistor 303 of the 3 rd inverter 301, and the corresponding terminal I of the 1 st memristor module 304 out1 Terminal I of the 2 nd memristor module 304 out2 Terminal I of the 3 rd memristor module 304 out3 Connecting; the source of the PMOS transistor 302 of the 1 st inverter 301, the source of the PMOS transistor 302 of the 2 nd inverter 301, and the source of the PMOS transistor 302 of the 3 rd inverter 301 are connected to the terminal A of the 1 st ring oscillator circuit 102 vdd1 And (4) connecting.
As shown in FIG. 7, the terminal V of the 1 st memristor module 304 chlg1 Terminal V of the 2 nd memristor module 304 chlg2 Terminal V of the 3 rd memristor module 304 chlg3 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 chlg1 Connecting, terminal V of memristor Module 304 1 rd1 Terminal V of the 2 nd memristor module 304 rd2 Terminal V of the 3 rd memristor module 304 rd3 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rd1 Connecting, terminal V of the 1 st memristor module 304 cr01 Terminal V of the 2 nd memristor module 304 cr02 Terminal V of the 3 rd memristor module 304 cr03 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr01 Connecting, terminal V of memristor Module 304 1 dly1 Of the 2 nd memristor Module 304Terminal V dly2 Terminal V of the 3 rd memristor module 304 dly3 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 dly1 Connecting, terminal V of the 1 st memristor module 304 cr11 Terminal V of the 2 nd memristor module 304 cr12 Terminal V of the 3 rd memristor module 304 cr13 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr11 Connecting, terminal V of the 1 st memristor module 304 c11 Terminal V of the 2 nd memristor module 304 c21 Terminal V of the 3 rd memristor module 304 c31 Corresponding terminal A of the 1 st ring oscillator circuit 102 c11 、A c21 、A c31 Connecting; terminal V of 1 st memristor module 304 rs1 Terminal V of the 2 nd memristor module 304 rs2 Terminal V of the 3 rd memristor module 304 rs3 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rs1 Connecting, terminal V of memristor Module 304 1 cr21 Terminal V of the 2 nd memristor module 304 cr22 Terminal V of the 3 rd memristor module 304 cr23 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr21 And (4) connecting.
The 2 nd ring oscillator circuit 106 is identical in structure to the 1 st ring oscillator circuit 102.
As shown in FIG. 4, the 1 st memristor module 304 is configured such that the terminal OUT of the 1 st gate 401 is connected to the terminal 0 \Chanof the 2 nd gate 402, the terminal 1_Chan of the 2 nd gate 402 is connected to GND, the terminal OUT of the 2 nd gate 402 is connected to the terminal 1_Chan of the 3 rd gate 403, the terminal 0_Chan of the 3 rd gate 403 is connected to GND, and the terminal OUT of the 3 rd gate 403 is connected to the terminal R of the module memristor 404 M0 Connecting; the drain of the NMOS transistor 409 and the terminal R of the module memristor 404 M0 Connected, the source of the NMOS transistor 409 to the terminal R of the module memristor 404 M1 Connecting; terminal IN of 1 st shunt 405 and terminal R of module memristor 404 M1 Connected, terminal 1_chan of 1 st splitter 405 is connected to terminal IN of 2 nd splitter 406; terminal 1 of splitter 406 and terminal I of mirror current source 407 ref Terminal 0v chan of 2 nd shunt 406 is connected to terminal R of current limiting resistor 408 0 Connecting, limiting currentTerminal R of resistor 408 1 Is connected to GND.
As shown in FIG. 4, the terminals 1_CHAN, 0_CHAN, SEL of the 1 st gate 401 correspond to the terminal V of the 1 st memristor module 304 chlg1 、V rd1 、V cr01 Connecting, the terminal SEL of the 2 nd gate 402 with the terminal V of the 1 st memristor module 304 dly1 Connected, the terminal SEL of the 3 rd gate 403 and the terminal V of the 1 st memristor module 304 cr11 Connecting; the gate of the NMOS transistor 409 and the terminal V of the 1 st memristor module 304 c11 Connecting; terminal SEL of 1 st shunt 405 and terminal V of 1 st memristor module 304 cr11 Connect terminal 0 \ u CHAN of 1 st shunt 405 with terminal V of 1 st memristor module 304 rs1 Connected, terminal SEL of 2 nd shunt 406 to terminal V of 1 st memristor module 304 cr21 Connecting; terminal I of mirror current source 407 out With terminal I of the 1 st memristor module 304 out1 And (4) connecting.
The 2 nd and 3 rd memristor modules 304, 304 are identical in structure to the 1 st memristor module 304.
The delay circuit memristor 201 is the same as the module memristor 404, and both the delay circuit memristor and the module memristor are memristors with threshold voltages; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in the high resistance state.
The use method of the memristor-based ring oscillator PUF circuit comprises the following steps:
step one, resetting all memristors
At voltage input terminal V cr1 A voltage signal U of low level is applied between the terminal GND and the ground cr1 =0V; at a voltage input terminal V rs A high-level voltage signal U is applied between the terminal and the GND rs =2V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
In step one, all module memristors 404 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 are reset to high impedance states:
1 st ring oscillator circuit 102: the resistance values of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304 and the 3 rd memristor module 304 are 9474 Ω, 10502 Ω and 11121 Ω in sequence;
in the 2 nd ring oscillator circuit 106: the resistance values of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304, and the 3 rd memristor module 304 are 8325 Ω, 11718 Ω, and 11103 Ω in sequence.
Step two, applying excitation
At voltage input terminal V pl 、V chlg 、V cr0 、V cr1 A high-level voltage signal U corresponding to the voltage applied between the terminals GND pl ＝2V、U chlg ＝2V、U cr0 ＝1.8V、U cr2 =1.8V; at voltage input terminal V c1 、V c2 、V c3 A high-level or low-level excitation voltage signal U corresponding to the application of the terminal GND c1 ＝1.8V、U c2 ＝1.8V、U c3 =1.8V; at voltage input terminal V cr2 A voltage signal U of low level is applied between the terminal and the GND cr2 =0V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
In step two, the resistance values of all the module memristors 404 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 are randomly reduced, and the reduced resistance values are:
1 st ring oscillator circuit 102: the resistance values of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304 and the 3 rd memristor module 304 are 9275 Ω, 10252 Ω and 10837 Ω in sequence;
in the 2 nd ring oscillator circuit 106: the resistances of the module memristors 404 in the 1 st memristor module 304, and the 3 rd memristor module 304 are 8175 Ω, 11399 Ω, and 10820 Ω in sequence.
Step three, responding to output
At voltage input terminal V vdd 、V rd 、V cr1 、V cr2 A high-level voltage signal U corresponding to the voltage applied between the terminals GND vdd ＝5V、U rd ＝1.5V、U cr1 ＝1.8V、U cr2 =1.8V; at voltage input terminal V cr0 A voltage signal U of low level is applied between the terminal and the GND cr0 =0V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Terminal R of digital comparator 104 out And outputting the response voltage.
In step three, the oscillation frequency f of the square wave generated by the 1 st ring oscillator circuit 102 1 ＝2.468KH Z Oscillation frequency f of square wave generated by 2 nd ring oscillator circuit 106 2 ＝2.471KH Z 。
Terminal R of digital comparator 104 out The output response voltage is 0V.
Example 2
A ring oscillator (PUF) circuit based on a memristor and a using method thereof.
As shown in fig. 8, the memristor-based ring oscillator PUF circuit is composed of a random delay circuit 101, a 1 st ring oscillator circuit 102, a 2 nd ring oscillator circuit 106, a 1 st counter 103, a 2 nd counter 105, and a digital comparator 104.
As shown in FIG. 8, terminal V of random delay circuit 101 pulse And voltage input terminal V p1 Terminal V of connection, random delay circuit 101 c12 、V c22 、V c32 、V c42 、V c52 With corresponding voltage input terminal V c1 、V c2 、V c3 、V c4 、V c5 Connecting; terminal V of random delay circuit 101 delay And terminal A of the 1 st ring oscillator circuit 102 dly1 Terminal A of the 2 nd ring oscillator circuit 106 dly2 Are respectively connected.
Terminal A of 1 st ring oscillator circuit 102 vdd1 Terminal A of the 2 nd ring oscillator circuit 106 vdd2 Are respectively connected with a voltage input terminal V vdd Connected, terminal A of 1 st ring oscillator circuit 102 chlg1 Terminal A of the 2 nd ring oscillator circuit 106 chlg2 Respectively connected with voltage input terminal V chlg Connected, terminal A of 1 st ring oscillator circuit 102 rd1 Terminal A of the 2 nd ring oscillator circuit 106 rd2 Respectively connected with voltage input terminal V rd To the end of the 1 st ring oscillator circuit 102Seed A cr01 Terminal A of the 2 nd ring oscillator circuit 106 cr02 Respectively connected with voltage input terminal V cr0 Connected, terminal A of 1 st ring oscillator circuit 102 cr11 Terminal A of the 2 nd ring oscillator circuit 106 cr12 Are respectively connected with a voltage input terminal V cr1 Connecting; terminal A of 1 st ring oscillator circuit 102 c11 、A c21 、A c31 、A c41 、A c51 With corresponding voltage input terminal V c1 、V c2 、V c3 、V c4 、V c5 Connected, terminal A of 2 nd ring oscillator circuit 106 c12 、A c22 、A c32 、A c42 、A c52 With corresponding voltage input terminal V c1 、V c2 、V c3 、V c4 、V c5 Connecting; terminal A of 1 st ring oscillator circuit 102 rs1 Terminal A of the 2 nd ring oscillator circuit 106 rs2 Respectively connected with voltage input terminal V rs Connecting; terminal A of 1 st ring oscillator circuit 102 cr21 Terminal A of the 2 nd ring oscillator circuit 106 cr22 Respectively connected with voltage input terminal V cr2 Connecting; terminal f of 1 st ring oscillator circuit 102 out1 And terminal A of the 1 st counter 103 10 Connected, terminal f of 2 nd ring oscillator circuit 106 out2 And terminal A of the 2 nd counter 105 20 And (4) connecting.
Terminal A of 1 st counter 103 11 And terminal IN of digital comparator 104 0 Connected to, terminal A of the 2 nd counter 105 21 And terminal IN of digital comparator 104 1 To terminal R of digital comparator 104 out And outputting the response voltage.
At voltage input terminal V pl 、V vdd 、V chlg 、V rd 、V cr0 、V cr1 、V rs 、V cr2 A voltage signal U corresponding to the voltage applied between the terminals GND pl 、U vdd 、U chlg 、U rd 、U cr0 、U cr1 、U rs 、U cr2 At a voltage input terminal V c1 、V c2 、V c3 、V c4 、V c5 A voltage signal U corresponding to the voltage applied between the terminals GND c1 、U c2 、U c3 、U c4 、U c5 。
Terminal R of digital comparator 104 out And outputting the response voltage.
As shown in fig. 9, the random delay circuit 101 is composed of 5 delay cells 202 and NMOS transistors 204; the terminal OUT of the 1 st delay cell 202 is connected to the terminal IN of the 2 nd delay cell 202, the terminal OUT of the 2 nd delay cell 202 is connected to the terminal IN of the 3 rd delay cell 202, the terminal OUT of the 3 rd delay cell 202 is connected to the terminal IN of the 4 th delay cell 202, the terminal OUT of the 4 th delay cell 202 is connected to the terminal IN of the 5 th delay cell 202, and the terminal OUT of the 5 th delay cell 202 is connected to the drain of the NMOS transistor 204.
As shown IN FIG. 9, the terminals IN of the 1 st delay cell 202 are respectively connected with the terminals A of the two delay circuit memristors 201 R0 Connected, terminal A of two delay circuit memristors 201 R1 Connected to the terminal 1 _chanand the terminal 0 _chanof the 1 st delay line gate 203; the 2 nd delay unit 202, the 3 rd delay unit 202, the 4 th delay unit 202, the 5 th delay unit 202 have the same structure as the 1 st delay unit 202.
As shown IN FIG. 9, the terminal IN of the 1 st delay cell 202 and the terminal V of the random delay circuit 101 pulse Connected, the terminal OUT of the Nth delay cell 202 and the terminal V of the random delay circuit 101 delay Connecting; the terminal SEL of the 1 st delay unit 202, the terminal SEL of the 2 nd delay unit 202, the terminal SEL of the 3 rd delay unit 202, the terminal SEL of the 4 th delay unit 202, the terminal SEL of the 5 th delay unit 202, and the corresponding terminal V of the random delay circuit 101 c12 、V c22 、V c32 、V c42 、V c52 And (4) connecting.
As shown in fig. 10, the 1 st ring oscillator circuit 102 is composed of 5 inverters 301 and 5 memristor modules 304; the terminal OUT of the 1 st inverter 301 is connected to the terminal IN of the 2 nd inverter 301, the terminal OUT of the 2 nd inverter 301 is connected to the terminal IN of the 3 rd inverter 301, the terminal OUT of the 3 rd inverter 301 is connected to the terminal IN of the 4 th inverter 301, and the terminal OUT of the 4 th inverter 301The terminal OUT is connected to the terminal IN of the 5 th inverter 301; the terminal IN of the 1 st inverter 301 is connected to the terminal OUT of the 5 th inverter 301, and the terminal OUT of the 5 th inverter 301 is connected to the terminal f of the 1 st ring oscillator circuit 102 out1 And (4) connecting.
As shown in fig. 10, the source of the NMOS transistor 303 of the 1 st inverter 301, the source of the NMOS transistor 303 of the 2 nd inverter 301, the source of the NMOS transistor 303 of the 3 rd inverter 301, the source of the NMOS transistor 303 of the 4 th inverter 301, the source of the NMOS transistor 303 of the 5 th inverter 301, and the corresponding terminal I of the 1 st memristor module 304 out1 Terminal I of the 2 nd memristor module 304 out2 Terminal I of the 3 rd memristor module 304 out3 Connecting terminal I of the 4 th memristor module 304 out4 Terminal I of connecting, 5 th memristor Module 304 out5 Connecting; the source of the PMOS transistor 302 of the 1 st inverter 301, the source of the PMOS transistor 302 of the 2 nd inverter 301, the source of the PMOS transistor 302 of the 3 rd inverter 301, the source of the PMOS transistor 302 of the 4 th inverter 301, the source of the PMOS transistor 302 of the 5 th inverter 301, and the terminal A of the 1 st ring oscillator circuit 102, respectively vdd1 And (4) connecting.
As shown in FIG. 10, the terminal V of the 1 st memristor Module 304 chlg1 Terminal V of the 2 nd memristor module 304 chlg2 Terminal V of the 3 rd memristor module 304 chlg3 Terminal V of the 4 th memristor module 304 chlg4 Terminal V of the 5 th memristor module 304 chlg5 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 chlg1 Connecting, terminal V of memristor Module 304 1 rd1 Terminal V of the 2 nd memristor module 304 rd2 Terminal V of the 3 rd memristor module 304 rd3 Terminal V of the 4 th memristor module 304 rd4 Terminal V of the 5 th memristor module 304 rd5 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rd1 Connecting, terminal V of memristor Module 304 1 cr01 Terminal V of the 2 nd memristor module 304 cr02 Terminal V of the 3 rd memristor module 304 cr03 Terminal V of the 4 th memristor module 304 cr04 Terminal V of the 5 th memristor module 304 cr05 Respectively connected with 1 st ring oscillator circuit 102 terminal a cr01 Connecting, terminal V of memristor Module 304 1 dly1 Terminal V of the 2 nd memristor module 304 dly2 Terminal V of the 3 rd memristor module 304 dly3 Terminal V of the 4 th memristor module 304 dly4 Terminal V of the respective, 5 th memristor module 304 dly5 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 dly1 Connecting, terminal V of memristor Module 304 1 cr11 Terminal V of the 2 nd memristor module 304 cr12 Terminal V of the 3 rd memristor module 304 cr13 Terminal V of the 4 th memristor module 304 cr14 Terminal V of the 5 th memristor module 304 cr15 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr11 Connecting; terminal V of 1 st memristor module 304 c11 Terminal V of the 2 nd memristor module 304 c21 Terminal V of the 3 rd memristor module 304 c31 Terminal V of the 4 th memristor module 304 c41 Terminal V of the 5 th memristor module 304 c51 Corresponding terminal A of the 1 st ring oscillator circuit 102 c11 、A c21 、A c31 、A c41 、A c51 Connecting; terminal V of 1 st memristor module 304 rs1 Terminal V of the 2 nd memristor module 304 rs2 Terminal V of the 3 rd memristor module 304 rs3 Terminal V of the 4 th memristor module 304 rs4 Terminal V of the 5 th memristor module 304 rs5 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 rs1 Connecting, terminal V of the 1 st memristor module 304 cr21 Terminal V of the 2 nd memristor module 304 cr22 Terminal V of the 3 rd memristor module 304 cr23 Terminal V of the 4 th memristor module 304 cr24 Terminal V of the 5 th memristor module 304 cr25 Respectively connected with terminals A of the 1 st ring oscillator circuit 102 cr21 And (4) connecting.
The 2 nd ring oscillator circuit 106 is identical in structure to the 1 st ring oscillator circuit 102.
The structure of the 1 st memristor module 304 described in this embodiment is the same as the structure of the 1 st memristor module 304 described in embodiment 1.
The 2 nd, 3 rd, 4 th, and 5 th memristor modules 304, 304 are identical in structure to the 1 st memristor module 304.
The delay circuit memristor 201 is the same as the module memristor 404, and both the delay circuit memristor and the module memristor are memristors with threshold voltages; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in a high resistance state.
The use method of the memristor-based ring oscillator PUF circuit comprises the following steps:
step one, resetting all memristors
At voltage input terminal V cr1 A voltage signal U of low level is applied between the terminal and the GND cr1 =0V; at voltage input terminal V rs A high-level voltage signal U is applied between the terminal and the GND rs =2V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
In step one, all the module memristors 404 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 are reset to a high resistive state:
1 st ring oscillator circuit 102: the resistances of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304, the 3 rd memristor module 304, the 4 th memristor module 304, and the 5 th memristor module 304 are 11572 Ω, 10813 Ω, 10223 Ω, 8738 Ω, and 8848 Ω in sequence;
in the 2 nd ring oscillator circuit 106: the resistance values of the memristors 404 of the 1 st memristor module 304, the 2 nd memristor module 304, the 3 rd memristor module 304, the 4 th memristor module 304 and the 5 th memristor module 304 are 8309 Ω, 11655 Ω, 10827 Ω, 10231 Ω and 9254 Ω in sequence.
Step two, excitation is applied
At voltage input terminal V pl 、V chlg 、V cr0 、V cr1 A high-level voltage signal U corresponding to the voltage applied between the terminals GND pl ＝2V、U chlg ＝2V、U cr0 ＝1.8V、U cr2 =1.8V; at voltage input terminal V c1 、V c2 、V c3 、V c4 、V c5 Applying a high or low excitation voltage between terminals GNDSignal U c1 ＝1.8V、U c2 ＝1.8V、U c3 ＝1.8V、U c4 ＝1.8V、U c5 =0V; at voltage input terminal V cr2 A voltage signal U of low level is applied between the terminal GND and the ground cr2 =0V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
In step two, the resistance values of all the module memristors 404 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 are randomly reduced, and the reduced resistance values are:
1 st ring oscillator circuit 102: the resistances of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304, the 3 rd memristor module 304, the 4 th memristor module 304, and the 5 th memristor module 304 are 10920 Ω, 10250 Ω, 9725 Ω, 8385 Ω, and 8848 Ω in sequence;
in the 2 nd ring oscillator circuit 106: the resistances of the module memristors 404 in the 1 st memristor module 304, the 2 nd memristor module 304, the 3 rd memristor module 304, the 4 th memristor module 304, and the 5 th memristor module 304 are 7994 Ω, 10993 Ω, 10263 Ω, 9733 Ω, 9254 Ω in sequence.
Step three, responding to output
At voltage input terminal V vdd 、V rd 、V cr1 、V cr2 A high-level voltage signal U corresponding to the voltage applied between the terminals GND vdd ＝5V、U rd ＝1.5V、U cr1 ＝1.8V、U cr2 =1.8V; at voltage input terminal V cr0 A voltage signal U of low level is applied between the terminal and the GND cr0 =0V; no voltage signal is applied between the remaining voltage input terminal and the terminal GND.
Terminal R of digital comparator 104 out And outputting the response voltage.
In step three, the oscillation frequency f of the square wave generated by the 1 st ring oscillator circuit 102 1 ＝3.912KH Z Oscillation frequency f of square wave generated by 2 nd ring oscillator circuit 106 2 ＝3.921KH Z ；
Terminal R of digital comparator 104 out The output response voltage is 0V.
In the specific embodiment, the randomness of the resistance distribution of the memristor 404 in the high-resistance state is used as a main entropy source of the memristor-based ring oscillator PUF circuit, and in step one, a relevant voltage signal is applied to the memristor module 304, so that all the module memristors 404 in the memristor-based ring oscillator PUF circuit are reset to the high-resistance state. In step two, the memristor-based ring oscillator PUF circuit selects a part of module memristors 404 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 according to the input excitation voltage signal, and applies a high-level voltage signal U to the selected module memristors 404 chlg A high-level voltage signal U is generated by the random delay circuit 101 chlg The time duration imposed on the module memristors 404 is random, and the selected module memristors 404 perform a random resistance reduction in the high-resistance state. In step three, the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 start to oscillate, pulses of square waves generated by the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 are counted by the 1 st counter 103 and the 2 nd counter 105, respectively, and finally the counted values are compared by the digital comparator 104 to obtain a response.
The embodiment has the following positive effects:
in step two, in this embodiment, the memristor-based ring oscillator PUF circuit selects the module memristor 404 in the memristor module 304 according to the applied excitation voltage signal, and performs a random resistance reduction on the selected module memristor 404 for once, the excitation voltage signals are different, the selected module memristors 404 are also different, the resistance reduction amount of the selected module memristor 404 is also different, so that the excitation voltage signals are different, the resistances of the module memristors 404 in the memristor-based ring oscillator PUF circuit are also different, that is, the parameters of the memristor-based ring oscillator PUF circuit are different, and the parameters of the memristor-based ring oscillator PUF circuit are also changed along with the change of the excitation voltage signal, which makes it difficult for a machine learning algorithm to accurately establish a mathematical model of the memristor-based ring oscillator PUF circuit, and thus has a significant machine learning resistance.
In the specific embodiment, except that the randomness of the resistance distribution of the memristor 404 in the memristor module 304 in the high-resistance state is used as an entropy source of the memristor-based ring oscillator PUF circuit, the randomness of the resistance distribution of the delay circuit memristor 201 in the random delay circuit 101 in the high-resistance state is also used as an entropy source of the memristor-based ring oscillator PUF circuit, so that the random delay circuit has a dual entropy source and a good core performance index.
In the specific embodiment, a multi-bit CRP pair can be generated only by two ring oscillator circuits, and the number of memristor modules 304 corresponding to the inverters 301 and 301 in the 1 st ring oscillator circuit 102 and the 2 nd ring oscillator circuit 106 is increased only by increasing the number of bits of the CRP pair, so that the expansibility is strong and the hardware consumption is low.
Therefore, the specific implementation mode has the characteristics of strong machine learning resistance, low hardware consumption and good core performance index.

Claims (2)

1. A memristor-based ring oscillator (PUF) circuit, wherein:
the memristor-based ring oscillator PUF circuit is composed of a random delay circuit (101), a 1 st ring oscillator circuit (102), a 2 nd ring oscillator circuit (106), a 1 st counter (103), a 2 nd counter (105) and a digital comparator (104);
terminal V of random delay circuit (101) pulse And voltage input terminal V pl Terminal V of connection, random delay circuit (101) c12 、……、V ci2 、……、V cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal V of random delay circuit (101) delay And terminal A of the 1 st ring oscillator circuit (102) dly1 And terminal A of the 2 nd ring oscillator circuit (106) dly2 Are respectively connected;
terminal A of 1 st ring oscillator circuit (102) vdd1 Terminal A of the 2 nd ring oscillator circuit 106 vdd2 Respectively connected with voltage input terminal V vdd Connected, terminal A of the 1 st ring oscillator circuit (102) chlg1 Terminal A of the 2 nd ring oscillator circuit 106 chlg2 Respectively connected with voltage input terminal V chlg Connected to terminal A of the 1 st ring oscillator circuit (102) rd1 Terminal A of the 2 nd ring oscillator circuit 106 rd2 Respectively connected with voltage input terminal V rd Connected, terminal A of the 1 st ring oscillator circuit (102) cr01 Terminal A of the 2 nd ring oscillator circuit 106 cr02 Respectively connected with voltage input terminal V cr0 Connected to terminal A of the 1 st ring oscillator circuit (102) cr11 Terminal A of the 2 nd ring oscillator circuit 106 cr12 Respectively connected with voltage input terminal V cr1 Connecting; terminal A of 1 st ring oscillator circuit (102) c11 、……、A ci1 、……、A cN1 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connected to terminal A of the 2 nd ring oscillator circuit (106) c12 、……、A ci2 、……、A cN2 With corresponding voltage input terminal V c1 、……、V ci 、……、V cN Connecting; terminal A of 1 st ring oscillator circuit (102) rs1 And terminal A of the 2 nd ring oscillator circuit (106) rs2 Respectively connected with voltage input terminal V rs Connecting; terminal A of 1 st ring oscillator circuit (102) cr21 Terminal A of the 2 nd ring oscillator circuit 106 cr22 Are respectively connected with a voltage input terminal V cr2 Connecting; terminal f of 1 st ring oscillator circuit (102) out1 And a terminal A of the 1 st counter (103) 10 Connected, terminal f of 2 nd ring oscillator circuit (106) out2 And a terminal A of a 2 nd counter (105) 20 Connecting;
terminal A of 1 st counter (103) 11 And a terminal IN of a digital comparator (104) 0 Connected, terminal A of the 2 nd counter (105) 21 And a terminal IN of a digital comparator (104) 1 Connected to a terminal R of a digital comparator (104) out Outputting a response voltage;
at a voltage input terminal V pl 、V vdd 、V chlg 、V rd 、V cr0 、V cr1 、V rs 、V cr2 A voltage signal U corresponding to the voltage applied between the terminals GND pl 、U vdd 、U chlg 、U rd 、U cr0 、U cr1 、U rs 、U cr2 At a voltage input terminal V c1 、……、V ci 、……、V cN A voltage signal U corresponding to the voltage applied between the terminals GND c1 、……、U ci 、……、U cN (ii) a Terminal R of digital comparator (104) out Outputting a response voltage;
the random delay circuit (101) is composed of N delay units (202) and N NMOS transistors (204), wherein N is an odd number; the terminal OUT of the 1 st delay unit (202) is connected with the terminal IN of the 2 nd delay unit (202), … …, the terminal OUT of the i-1 th delay unit (202) is connected with the terminal IN of the i-th delay unit (202), … …, the terminal OUT of the N-1 th delay unit (202) is connected with the terminal IN of the N-th delay unit (202), and the terminal OUT of the N-th delay unit (202) is connected with the drain of the NMOS transistor (204);
the terminal IN of the 1 st delay unit (202) is respectively connected with the terminals A of the two delay circuit memristors (201) R0 Connecting terminals A of two delay circuit memristors (201) R1 Connected to a terminal 1 _CHANand a terminal 0 _CHANof the 1 st delay line gate (203); the 2 nd delay unit (202), … …, the ith delay unit (202), … … and the Nth delay unit (202) have the same structure as the 1 st delay unit (202);
terminal IN of 1 st delay unit (202) and terminal V of random delay circuit (101) pulse A terminal OUT of the Nth delay unit (202) and a terminal V of the random delay circuit (101) are connected delay Connecting; terminals SEL, … … of the 1 st delay unit (202), terminals SEL, … … of the i-th delay unit (202), and terminal SEL of the N-th delay unit (202) are associated with terminal V of the corresponding random delay circuit (101) c12 、……、V ci2 、……、V cN2 Connecting;
the 1 st ring oscillator circuit (102) is composed of N inverters (301) and N memristor modules (304), N being an odd number; terminal OUT of 1 st inverter 301 and 2 nd inverter 301 … …, the terminal OUT of the i-1 th inverter (301) is connected to the terminal IN of the i-th inverter (301), … …, the terminal OUT of the N-1 th inverter (301) is connected to the terminal IN of the N-1 th inverter (301); the terminal IN of the 1 st inverter 301 is connected to the terminal OUT of the Nth inverter 301, and the terminal OUT of the Nth inverter 301 is connected to the terminal f of the 1 st ring oscillator circuit 102 out1 Connecting;
the source of the NMOS transistor (303) of the 1 st inverter (301), … …, the source of the NMOS transistor (303) of the ith inverter (301), … …, the source of the NMOS transistor (303) of the Nth inverter (301), and the corresponding terminal I of the 1 st memristor module (304) out1 … …, terminal I of I-th memristor module (304) outi … …, terminal I of Nth memristor module (304) outN Connecting; the source of the PMOS transistor (302) of the 1 st inverter (301), … …, the source of the PMOS transistor (302) of the i-th inverter (301), … …, and the source of the PMOS transistor (302) of the N-th inverter (301) are connected to the terminal A of the 1 st ring oscillator circuit (102), respectively vdd1 Connecting;
terminal V of 1 st memristor module (304) chlg1 … …, terminal V of i-th memristor module (304) chlgi … …, terminal V of Nth memristor module (304) chlgN Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) chlg1 Connecting, terminal V of 1 st memristor Module (304) rd1 … …, terminal V of ith memristor module (304) rdi … …, terminal V of Nth memristor module (304) rdN Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) rd1 Connecting, terminal V of 1 st memristor Module (304) cr01 … …, terminal V of i-th memristor module (304) cr0i … …, terminal V of Nth memristor module (304) cr0N Respectively connected with terminals A of the 1 st ring oscillator circuit (102) cr01 Connecting, terminal V of 1 st memristor Module (304) dly1 … …, terminal V of i-th memristor module (304) dlyi … …, terminal V of Nth memristor module (304) dlyN Respectively connected with terminals A of the 1 st ring oscillator circuit (102) dly1 Connecting, terminal V of 1 st memristor Module (304) cr11 … …, terminal V of i-th memristor module (304) cr1i … …, terminal V of Nth memristor module (304) cr1N Respectively connected with terminals A of the 1 st ring oscillator circuit (102) cr11 Connecting, terminal V of 1 st memristor Module (304) c11 … …, terminal V of i-th memristor module (304) ci1 … …, terminal V of Nth memristor module (304) cN1 And a terminal A of a corresponding 1 st ring oscillator circuit (102) c11 、……、A ci1 、……、A cN1 Connecting; terminal V of 1 st memristor module (304) rs1 … …, terminal V of i-th memristor module (304) rsi … …, terminal V of Nth memristor module (304) rsN Respectively connected with terminals A of the 1 st ring oscillator circuit (102) rs1 Connecting, terminal V of 1 st memristor Module (304) cr21 … …, terminal V of i-th memristor module (304) cr2i … …, terminal V of Nth memristor module (304) cr2N Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) cr21 Connecting;
the 2 nd ring oscillator circuit (106) is the same structure as the 1 st ring oscillator circuit (102);
the structure of the 1 st memristor module (304) is that the terminal OUT of the 1 st gating device (401) is connected with the terminal 0_CHAN of the 2 nd gating device (402), the terminal 1_CHAN of the 2 nd gating device (402) is connected with GND, the terminal OUT of the 2 nd gating device (402) is connected with the terminal 1_CHAN of the 3 rd gating device (403), the terminal 0_CHAN of the 3 rd gating device (403) is connected with GND, and the terminal OUT of the 3 rd gating device (403) is connected with the terminal R of the module memristor (404) M0 Connecting; a drain of the NMOS transistor (409) and a terminal R of the module memristor (404) M0 Connected, the source of the NMOS transistor (409) and the terminal R of the module memristor (404) M1 Connecting; terminal IN of 1 st shunt (405) and terminal R of module memristor (404) M1 A terminal 1 _CHANof the 1 st splitter (405) is connected to a terminal IN of the 2 nd splitter (406); terminal 1 of the 2 nd splitter (406) chan and terminal I of the mirror current source (407) ref The 2 nd shunt (406) terminal 0 u CHAN is connected to the current limiting resistor (408) terminal R 0 A terminal R connected to a current limiting resistor 408 1 Is connected to GNDConnecting;
the 1 st gate (401) terminals 1_CHAN, 0_CHAN, SEL and the 1 st memristor module (304) corresponding terminal V chlg1 、V rd1 、V cr01 Connected, the terminal SEL of the 2 nd gate (402) and the terminal V of the 1 st memristor module (304) dly1 Connected, the terminal SEL of the 3 rd gate (403) and the terminal V of the 1 st memristor module (304) cr11 Connecting; a gate of the NMOS transistor (409) and a terminal V of the 1 st memristor module (304) c11 Connecting; terminal SEL of 1 st shunt (405) and terminal V of 1 st memristor module (304) cr11 Connecting terminal 0 _CHANof the 1 st shunt (405) with terminal V of the 1 st memristor module (304) rs1 Connected, terminal SEL of 2 nd shunt (406) and terminal V of 1 st memristor module (304) cr21 Connecting; terminal I of mirror current source (407) out With terminal I of the 1 st memristor Module (304) out1 Connecting;
the 2 nd memristor module (304), … …, the ith memristor module (304), … … and the Nth memristor module (304) are all the same as the 1 st memristor module (304) in structure;
the delay circuit memristor (201) is the same as the module memristor (404), and both the delay circuit memristor and the module memristor are memristors with threshold voltages; the initial states of the delay circuit memristor (201) and the module memristor (404) are both in a high resistance state.
2. A use method of a ring oscillator (PUF) circuit based on a memristor is characterized in that the use method is as follows:
step one, resetting all memristors
At voltage input terminal V cr1 A voltage signal U of low level is applied between the terminal and the GND cr1 At a voltage input terminal V rs A high-level voltage signal U is applied between the terminal and the GND rs No voltage signal is applied between the other voltage input terminal and the terminal GND;
step two, applying excitation
At a voltage input terminal V pl 、V chlg 、V cr0 、V cr1 Applying a high level of electricity corresponding to the terminal GNDPressure signal U pl 、U chlg 、U cr0 、U cr1 At a voltage input terminal V c1 、……、V ci 、……、V cN A high-level or low-level excitation voltage signal U corresponding to the application of the terminal GND c1 、……、U ci 、……、U cN (ii) a At voltage input terminal V cr2 A voltage signal U of low level is applied between the terminal and the GND cr2 No voltage signal is applied between the other voltage input terminal and the terminal GND;
step three, responding to output
At a voltage input terminal V vdd 、V rd 、V cr1 、V cr2 A high-level voltage signal U corresponding to the voltage applied between the terminals GND vdd 、U rd 、U cr1 、U cr2 At a voltage input terminal V cr0 A voltage signal U of low level is applied between the terminal GND and the ground cr0 No voltage signal is applied between the other voltage input terminal and the terminal GND;
terminal R of digital comparator (104) out And outputting the response voltage.
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