CN115459923A - A memristor-based ring oscillator PUF circuit and its application method - Google Patents

Abstract

The invention relates to a memristor-based ring oscillator PUF circuit and a method for using the same. Its technical scheme is: described ring oscillator PUF circuit is made of random delay circuit (101), the 1st ring oscillator circuit (102), the 2nd ring oscillator circuit (106), the 1st counter (103), the 2nd counter (105) and a digital comparator (104). The frequency of the square wave generated by the two ring oscillating circuits depends on the resistance value of the module memristor (404) in the memristor module (304). In the present invention, the randomness of the high-resistance distribution of the module memristor (404) in the memristor module (304) is used as the main entropy source, and under the action of the random delay circuit (101), the module memristor is selected according to the input excitation voltage signal The memristor (404) randomly reduces the resistance value of the selected module memristor (404), and then compares the square wave frequencies generated by the two ring oscillator circuits to obtain a response. The invention has the characteristics of strong anti-machine learning ability, low hardware consumption and good core performance index.

Description

A memristor-based ring oscillator PUF circuit and its application method

technical field

The invention belongs to the technical field of PUF circuits. In particular, it relates to a memristor-based ring oscillator PUF circuit and a method for using the same.

Background technique

Physically Unclonable Function (Physically Unclonable Function, PUF) has attracted widespread attention as a new hardware security protection scheme in the field of hardware security. PUF is a concept created by researchers inspired by human fingerprints. Everyone's fingerprints are different, so fingerprints can be used as the unique identifier of the human body. The same batch of products produced by hardware devices under the same production process will have different parameters. Small differences, this difference is random and uncontrollable, PUF extracts this difference as the fingerprint of the hardware device, which is the unique identifier of the hardware device. PUF has input and output signals, its input signal is called challenge (Challenge), and the output signal is called response (Response). Inputting any stimulus will produce a unique and unpredictable response, and each stimulus has its own unique response. A stimulus and its corresponding response are called Challenge Response Pairs (CRPs). PUF has the characteristics of uniqueness and randomness, that is, once PUF is produced, it is unique and cannot be copied by the manufacturer. Taking advantage of these properties, PUF is mainly used in the field of hardware security, especially in hardware device authentication and anti-cloning. It has a unique advantage in security issues.

PUF can be divided into strong PUF and weak PUF according to the number of CRPs. Strong PUF has a large number of CRPs and is generally used in identity authentication; weak PUF generally only has a small amount of CRPs and is used in key generation. Ring oscillator PUF (RO PUF) is a classic strong PUF. RO PUF has high reliability and does not require strict symmetry in the circuit structure, which reduces the difficulty of manufacturing, but RO PUF needs to select two different ring oscillation circuits each time it produces a different response. In comparison, therefore, RO PUF has larger hardware consumption and power consumption.

Regardless of whether it is a strong PUF or a weak PUF, once the adversary can predict its CRPs with high precision, they are no longer safe. Machine learning can realize the cloning of PUF mathematical models to predict its CRPs with high precision, especially for most strong PUFs with strong circuit linear structure and more CRPs pairs, the effect of machine learning modeling attack is better. The researchers found through experiments that for the existing main strong PUFs, such as Arbiter PUF and RO PUF, the accuracy rate of machine learning modeling can reach more than 90%.

Loong J T H et al. (Loong J T H, HashimNAN, Hamid M S, et al.Performance analysis of CMOS-memristorhybridring oscillatorPhysically Unclonable Function(RO-PUF)[C]//2016IEEE International Conference on Semiconductor Electronics(ICSE).IEEE,2016:304- 307.) proposed a memristor-based RO PUF circuit. This design uses a memristor to replace the PMOS transistor of the CMOS inverter in the traditional RO PUF circuit, and uses the non-linear characteristics of the resistance change of the memristor to make the oscillation frequency of the oscillator more random, and the PUF circuit has better randomness . However, the PUF circuit still has the disadvantage that traditional ROPUF circuits are difficult to resist machine learning modeling attacks.

"A strong PUF based on memristor" (CN 109495272 A) patent technology, which uses 2T2R as the basic unit of the memristor array, and generates a unique response value by comparing the currents of the two columns of the memristor array, It has the characteristics of high area utilization, configurability and reuse, and has excellent randomness and resistance to modeling attacks. However, this strong PUF circuit needs to use a 2T2R memristor array, and its current comparison method requires high precision for the reading circuit; at the same time, its anti-attack ability to the model is only realized through strong randomness, and in fact it cannot be completely Avoid machine learning attacks.

"A high-efficiency reconfigurable ring oscillator PUF circuit based on RRAM" (CN 113707201 A) patented technology, which combines the RRAM array and the ring oscillator PUF circuit, and uses the random distribution of resistance when RRAM is in a high-impedance state as a PUF circuit entropy source. According to the applied excitation, the PUF circuit selects the corresponding RRAM in the RRAM array through the row decoder and the column selector to participate in the ring oscillator circuit, and finally uses two counters to count the pulse signals generated by the ring oscillator circuit. Response is obtained by comparing the magnitude of the count value. The circuit design uses the form of RRAM array to greatly reduce the circuit area and realize the ability of anti-machine learning through reconfiguration. However, the PUF circuit selects part of the RRAMs in the RRAM array to participate in the ring oscillator circuit each time according to the incentive, and the unselected RRAMs will cause waste of entropy sources and poor core performance indicators.

"Frequency Variable Ring Oscillator PUF Circuit" (CN 106372539 A) patented technology, which can change the oscillation frequency generated by the oscillator by configuring the number of inverters in the ring oscillator. Since the oscillation frequency of the oscillator is not fixed, the attack It is difficult for the author to establish its corresponding mathematical model through the method of mathematical modeling, so that the PUF circuit has a strong ability to resist machine learning. However, each time the PUF circuit generates different responses, two different ring oscillators need to be selected for comparison, and additional resources are required to configure the ring oscillators, so the hardware consumption of the PUF circuit is large.

Contents of the invention

The present invention aims to overcome the defects of the prior art, and aims to propose a memristor-based ring oscillator PUF circuit with strong anti-machine learning ability, low hardware consumption and good core performance indicators and its application method.

In order to achieve the above object, the technical scheme adopted in the present invention is:

The memristor-based ring oscillator PUF circuit is composed of a random delay circuit, a first ring oscillator circuit, a second ring oscillator circuit, a first counter, a second counter and a digital comparator.

The terminal V _pulse of the random delay circuit is connected to the voltage input terminal V _pl , and the terminals V _c12 , ..., V ci2 , ..., V _cN2 of the random delay circuit are _connected to the corresponding voltage input terminals V _c1 , ..., V _ci , ... . . . are connected to V _cN ; the terminal V _delay of the random delay circuit is connected to the terminal A _dly1 of the first ring oscillator circuit and the terminal A _dly2 of the second ring oscillator circuit, respectively.

The terminal A vdd1 of the first ring oscillator circuit and the terminal A _vdd2 of the second ring oscillator circuit are respectively connected to the voltage input terminal V _vdd , and the terminal A _chlg1 of the first ring oscillator circuit and the terminal A _of the second ring oscillator circuit _{chlg2 is} respectively connected to the voltage input terminal V _chlg , the terminal Ard1 of the first ring oscillator circuit, the terminal _Arrd2 of the second ring oscillator circuit are respectively connected to the voltage input terminal V _rd , and the terminal A _cr01 of the _first ring oscillator circuit , the terminal A _cr02 of the second ring oscillator circuit is respectively connected to the voltage input terminal V _cr0 , the terminal A cr11 of the first ring oscillator circuit, and the terminal A _cr12 of the second ring oscillator circuit _are respectively connected to the voltage input terminal V _cr1 ; Terminals A _c11 , ..., A _ci1 , ..., A _cN1 of the first ring oscillator circuit are connected to corresponding voltage input terminals V _c1 , ..., V _ci , ..., V _cN , and the second ring oscillator circuit The terminals A _c12 , ..., A _ci2 , ..., A _{cN2 are} connected to the corresponding voltage input terminals V _c1 , ..., V _ci , ..., V _cN ; the terminals A rs1 , the terminals A _rs1 of the first ring oscillator circuit 2 The terminals A _rs2 of the ring oscillator circuit are respectively connected to the voltage input terminal V _rs ; the terminals A _cr21 of the first ring oscillator circuit and the terminals A _cr22 of the second ring oscillator circuit are respectively connected to the voltage input terminal V _cr2 ; The terminal f _out1 of the ring oscillator circuit is connected to the terminal _A10 of the first counter, and the terminal f _out2 of the second ring oscillator circuit is connected to the terminal _A20 of the second counter.

The terminal A ₁₁ of the first counter is connected to the terminal IN ₀ of the digital comparator, the terminal A ₂₁ of the second counter is connected to the terminal IN ₁ of the digital comparator, and the terminal R _out of the digital comparator outputs a response voltage.

_Apply corresponding voltage signals U _pl , U _vdd , U _chlg , U _rd , U between voltage input terminals V _pl , V _vdd , V _chlg , V _rd , V _cr0 , V cr1, V _rs , V _cr2 and terminal GND _cr0 , U cr1 , U _rs , U _cr2 , apply corresponding voltage signals U _c1 , ..., U _ci , ... _between voltage input terminals V _c1 , ..., V _ci , ..., V _cN and terminal GND , U _cN .

The terminal R _out of the digital comparator outputs a response voltage.

The random delay circuit is composed of N delay units and NMOS transistors, N is an odd number; the terminal OUT of the first delay unit is connected to the terminal IN of the second delay unit, ..., the terminal OUT of the i-1th delay unit is connected to the terminal IN of the i-1th delay unit The terminal IN of the i delay unit is connected, ..., the terminal OUT of the N-1th delay unit is connected to the terminal IN of the Nth delay unit, and the terminal OUT of the Nth delay unit is connected to the drain of the NMOS transistor.

The terminal IN of the first delay unit is respectively connected to the terminal A _R0 of the two delay circuit memristors, and the terminal A _R1 of the two delay circuit memristors is correspondingly connected to the terminal 1_CHAN and the terminal 0_CHAN of the first delay circuit selector; The second delay unit, ..., the i-th delay unit, ..., the N-th delay unit have the same structure as the first delay unit.

The terminal IN of the first delay unit is connected to the terminal V _pulse of the random delay circuit, and the terminal OUT of the Nth delay unit is connected to the terminal V _delay of the random delay circuit; the terminals SEL of the first delay unit, ..., the terminals of the i delay unit The terminals SEL, ..., the terminal SEL of the Nth delay unit are connected to the terminals V _c12 , ..., V _{ci2 , ..., V cN2 of} the corresponding random delay circuit.

The first ring oscillator circuit is composed of N inverters and N memristor modules, where N is an odd number; the terminal OUT of the first inverter is connected to the terminal IN of the second inverter, ..., the first The terminal OUT of the i-1 inverter is connected to the terminal IN of the i inverter, ..., the terminal OUT of the N-1 inverter is connected to the terminal IN of the N inverter; The terminal IN is connected to the terminal OUT of the Nth inverter, and the terminal OUT of the Nth inverter is connected to the terminal f _out1 of the first ring oscillator circuit.

The source of the NMOS transistor of the first inverter, ..., the source of the NMOS transistor of the i inverter, ..., the source of the NMOS transistor of the N inverter and the corresponding first memristor module The terminal I _out1 of the i-th memristor module, ..., the terminal I _outi of the i-th memristor module, ..., the terminal I _outN of the N-th memristor module are connected; the source of the PMOS transistor of the first inverter, ..., the first The source of the PMOS transistor of the i inverter, . . . , the source of the PMOS transistor of the Nth inverter are respectively connected to the terminal A _vdd1 of the first ring oscillator circuit.

The terminals _{V chlg1 , .} connection, the terminals V _rd1 , ... of the first _memristor module, the terminals V _rdi , ... A _rd1 is connected, the terminals V _cr01 , ... of the first memristor module, the terminals V _cr0i , _... The terminals A _cr01 of the first memristor module are connected, the terminals V _dly1 , ... of the first memristor module, the terminals V _dlyi , _... The terminal A _dly1 of the memristor circuit is connected, the terminal V cr11 of the first memristor module, ..., the terminal V _cr1i of the i-th memristor module, ..., the terminal V _cr1N of the Nth _memristor The terminal A _cr11 of the ring oscillator circuit is connected, and the terminals V _c11 , . . . of the first memristor module, the terminals V _ci1 , . . _. Terminals A _c11 , ..., A _ci1 , ..., A _cN1 of the first ring oscillator circuit are connected; terminals V _rs1 , ... of the first memristor module, terminals V _rsi , ..., the terminal V _rsN of the Nth memristor module are respectively connected to the terminal A _rs1 of the first ring oscillator circuit, the terminal V _cr21 of the first memristor module, ..., the terminal V of the i-th memristor module _cr2i , . . . , terminals V _cr2N of the Nth memristor module are connected to terminals A _cr21 of the first ring oscillator circuit, respectively.

The second ring oscillator circuit has the same structure as the first ring oscillator circuit.

The structure of the first memristor module is that the terminal OUT of the first selector is connected to the terminal 0_CHAN of the second selector, the terminal 1_CHAN of the second selector is connected to GND, and the terminal of the second selector OUT is connected to terminal 1_CHAN of the third strobe, terminal 0_CHAN of the third strobe is connected to GND, terminal OUT of the third strobe is connected to terminal R _M0 of the module memristor; the drain of the NMOS transistor is connected to the module The terminal R _M0 of the memristor is connected, the source of the NMOS transistor is connected to the terminal R _M1 of the module memristor; the terminal IN of the first splitter is connected to the terminal R M1 of the module memristor, and the terminal IN of the first splitter is connected to the terminal R _M1 of the module memristor. The terminal 1_CHAN is connected to the terminal IN of the second shunt; the terminal 1_CHAN of the second shunt is connected to the terminal I _ref of the mirror current source, and the terminal 0_CHAN of the second shunt is connected to the terminal R ₀ of the current limiting resistor. Terminal R1 _of the flow resistor is connected to GND.

The terminals 1_CHAN, 0_CHAN, and SEL of the first gate are connected to the corresponding terminals V _chlg1 , V _rd1 , and V _cr01 of the first memristor module, and the terminal SEL of the second gate is connected to the terminal V of the first memristor module. _dly1 connection, the terminal SEL of the third strobe is connected to the terminal V _cr11 of the first memristor module; the gate of the NMOS transistor is connected to the terminal V _c11 of the first memristor module; the terminal SEL of the first splitter It is connected to the terminal V _cr11 of the first memristor module, the terminal 0_CHAN of the first shunt is connected to the terminal V _rs1 of the first memristor module, and the terminal SEL of the second shunt is connected to the terminal of the first memristor module. The terminal V _cr21 is connected; the terminal I _out of the mirror current source is connected to the terminal I _out1 of the first memristor module.

The structure of the second memristor module, ..., the i-th memristor module, ..., and the N-th memristor module is the same as that of the first memristor module.

The delay circuit memristor and the module memristor are the same, and both are memristors with a threshold voltage; the initial states of the delay circuit memristor and the module memristor are both in a high-impedance state.

The method of using the memristor-based ring oscillator PUF circuit:

Step 1. Reset all memristors

Apply a low-level voltage signal U _cr1 between the voltage input terminal V _cr1 and the terminal GND, apply a high-level voltage signal U rs between the voltage input terminal V _rs and the terminal GND, and apply a high-level voltage signal U _rs between the voltage input terminal V cr1 and the terminal GND. No voltage signal is applied between them.

Step 2. Apply incentives

Apply corresponding high-level voltage signals U _pl , U _chlg , U _cr0 , U _cr1 between the voltage input terminals _{V pl} , V _chlg , V _cr0 , V _cr1 and the terminal GND. , V _ci , ..., V _cN and terminal GND apply corresponding high-level or low-level excitation voltage signals U _c1 , ..., U _ci , ..., U _cN ; between voltage input terminals V _cr2 and A low-level voltage signal U _cr2 is applied between the terminals GND, and no voltage signal is applied between the other voltage input terminals and the terminal GND.

Step 3. Response output

Apply corresponding high-level voltage signals U _vdd , U _rd , U _{cr1 , U cr2 between} the voltage input terminals V _vdd , V _rd , V _cr1 , V _cr2 and the terminal GND, and between the voltage input terminals V _cr0 and the terminal GND A low-level voltage signal U _cr0 is applied between them, and no voltage signal is applied between the other voltage input terminals and the terminal GND.

The terminal R _out of the digital comparator outputs a response voltage.

In the present invention, the randomness of the resistance value distribution when the module memristor is in a high-impedance state is used as the main entropy source of the memristor-based ring oscillator PUF circuit. In step 1, a relevant voltage signal is applied to the memristor module, so that All block memristors in the memristor-based ring oscillator PUF circuit are reset to a high-impedance state. In step two, the memristor-based ring oscillator PUF circuit selects part of the module memristors in the first ring oscillator circuit and the second ring oscillator circuit according to the input excitation voltage signal, and the selected module memristors A high-level voltage signal U _{chlg is applied, and the duration of the high-level voltage signal U chlg applied} to the module memristor is random under the action of the random delay circuit, and the selected module memristor is in a high-impedance state Perform a random resistance reduction. In step three, the first ring oscillator circuit and the second ring oscillator circuit start to oscillate, and the square wave pulses generated by the first ring oscillator circuit and the second ring oscillator circuit are respectively generated by the first counter and the second counter Count, and finally compare the count value through a digital comparator to give a response.

Owing to adopting above-mentioned technical scheme, the present invention has following positive effect:

In the second step of the present invention, the memristor-based ring oscillator PUF circuit selects the module memristor in the memristor module according to the applied excitation voltage signal, and performs a random resistance reduction on the selected module memristor Small, the excitation voltage signal is different, the selected module memristor is also different, and the resistance reduction of the selected module memristor is also different, resulting in different excitation voltage signals, the module in the memristor-based ring oscillator PUF circuit The resistance value of the memristor is also different, that is, the parameters of the ring oscillator PUF circuit based on the memristor are different. As the excitation voltage signal changes, the parameters of the ring oscillator PUF circuit based on the memristor also change accordingly. It makes it difficult for the machine learning algorithm to accurately establish the mathematical model of the memristor-based ring oscillator PUF circuit, so it has significant anti-machine learning ability.

In the present invention, the randomness of the resistance value distribution when the module memristor in the memristor module is in a high-impedance state is used as the entropy source of the ring oscillator PUF circuit based on the memristor, and the delay circuit memristor in the random delay circuit is in the The randomness of the resistance value distribution in the high-impedance state is also used as the entropy source of the ring oscillator PUF circuit based on the memristor, so it has dual entropy sources and the core performance index is good.

The present invention only needs two ring oscillator circuits to generate multi-bit CRP pairs, and increasing the number of CRP pairs only needs to increase the number of inverters and inverters in the first ring oscillator circuit and the second ring oscillator circuit. Corresponds to the number of memristor modules, so the expandability is strong and the hardware consumption is small.

Therefore, the present invention has the characteristics of strong anti-machine learning ability, low hardware consumption and good core performance index.

Description of drawings

Fig. 1 is a kind of structural representation of the present invention;

Fig. 2 is a kind of structural representation of random delay circuit 101 in Fig. 1;

FIG. 3 is a schematic structural diagram of the first ring oscillator circuit 102 in FIG. 1;

FIG. 4 is a schematic structural view of the first memristor module 304 in FIG. 3;

Fig. 5 is another kind of structural representation of the present invention;

FIG. 6 is a schematic structural diagram of the random delay circuit 101 shown in FIG. 5;

FIG. 7 is a schematic structural diagram of the first ring oscillator circuit 102 shown in FIG. 5;

Fig. 8 is another kind of structural representation of the present invention;

FIG. 9 is a schematic structural diagram of the random delay circuit 101 shown in FIG. 8;

FIG. 10 is a schematic structural diagram of the first ring oscillator circuit 102 shown in FIG. 8;

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, which is not intended to limit its protection scope.

A memristor-based ring oscillator PUF circuit and a method of use thereof.

As shown in Figure 1, the ring oscillator PUF circuit based on the memristor is composed of a random delay circuit 101, a first ring oscillator circuit 102, a second ring oscillator circuit 106, a first counter 103, a second counter 105 and digital comparator 104.

As shown in Figure 1, the terminal V _pulse of the random delay circuit 101 is connected to the voltage input terminal V _pl , and the terminals V _c12 , ..., V ci2 , ..., V _cN2 of the random delay circuit 101 are _connected to the corresponding voltage input terminal V _c1 , . _. . , _{V ci , .}

The terminal A vdd1 of the first ring oscillator circuit 102 and the terminal A _vdd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _vdd , and the terminal A _chlg1 of the first ring oscillator circuit ₁₀₂ and the second ring oscillator circuit The terminal A _chlg2 of 106 is respectively connected to the voltage input terminal V _chlg , the terminal A _rd1 of the first ring oscillator circuit 102, and the terminal A _rd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rd , and the first ring oscillator circuit The terminal A cr01 of the oscillator circuit 102 and the terminal A _cr02 of the second ring oscillator circuit 106 are connected to the voltage input terminal V _cr0 respectively, and the terminal A _cr11 of the first ring oscillator circuit 102 and the terminal A _of the second ring oscillator circuit 106 _cr12 are respectively connected to voltage input terminals V _cr1 ; terminals A _c11 , ..., A _ci1 , ..., A _cN1 of the first ring oscillator circuit 102 are connected to corresponding voltage input terminals V _c1 , ..., V _ci , ... , V _cN connection, the terminals A _c12 , ..., A ci2 , ..., A _cN2 of the second ring oscillator circuit 106 are _connected to the corresponding voltage input terminals V _c1 , ..., V _ci , ..., V _cN ; The terminal A _rs1 of the first ring oscillator circuit 102 and the terminal A _rs2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rs ; the terminal A _cr21 of the first ring oscillator circuit 102 and the terminal A rs2 of the second ring oscillator circuit The terminal A _cr22 of 106 is respectively connected with the voltage input terminal V _cr2 ; the terminal f _out1 of the first ring oscillator circuit 102 is connected with the terminal _A10 of the first counter 103, and the terminal f _out2 of the second ring oscillator circuit 106 is connected with the second The terminal A ₂₀ of the counter 105 is connected.

The terminal A11 of the first counter 103 is connected to the terminal _IN0 of the digital comparator 104, the terminal _A21 of the second counter 105 is connected to the terminal IN1 _of the digital comparator 104, and the terminal _Rout of the digital comparator ₁₀₄ outputs a response voltage.

_Apply corresponding voltage signals U _pl , U _vdd , U _chlg , U _rd , U between voltage input terminals V _pl , V _vdd , V _chlg , V _rd , V _cr0 , V cr1, V _rs , V _cr2 and terminal GND _cr0 , U cr1 , U _rs , U _cr2 , apply corresponding voltage signals U _c1 , ..., U _ci , ... _between voltage input terminals V _c1 , ..., V _ci , ..., V _cN and terminal GND , U _cN .

The terminal R _out of the digital comparator 104 outputs a response voltage.

As shown in FIG. 2 , the random delay circuit 101 is composed of N delay units 202 and NMOS transistors 204, where N is an odd number; the terminal OUT of the first delay unit 202 is connected to the terminal IN of the second delay unit 202, ..., The terminal OUT of the i-1th delay unit 202 is connected to the terminal IN of the i-th delay unit 202, ..., the terminal OUT of the N-1th delay unit 202 is connected to the terminal IN of the Nth delay unit 202, and the Nth delay unit 202 The terminal OUT of the NMOS transistor 204 is connected to the drain.

As shown in Figure 2, the terminal IN of the first delay unit 202 is respectively connected to the terminal A _R0 of the two delay circuit memristors 201, and the terminal A _R1 of the two delay circuit memristors 201 is connected to the first delay circuit selector Terminal 1_CHAN and terminal 0_CHAN of 203 are correspondingly connected; the second delay unit 202 , . . . , the i-th delay unit 202 , .

As shown in Figure 2, the terminal IN of the first delay unit 202 is connected to the terminal V _pulse of the random delay circuit 101, and the terminal OUT of the Nth delay unit 202 is connected to the terminal V _delay of the random delay circuit 101; The terminal SEL, ..., the terminal SEL of the i-th delay unit 202, ..., the terminal SEL of the N-th delay unit 202 are connected to the corresponding terminals V _c12 , ..., V _{ci2 , ..., V cN2 of} the random delay circuit 101 .

As shown in Figure 3, the first ring oscillator circuit 102 is composed of N inverters 301 and N memristor modules 304, N is an odd number; the terminal OUT of the first inverter 301 is inverting with the second The terminal IN of the inverter 301 is connected, ..., the terminal OUT of the i-1th inverter 301 is connected to the terminal IN of the i-th inverter 301, ..., the terminal OUT of the N-1th inverter 301 is connected to the Nth The terminal IN of the inverter 301 is connected; the terminal IN of the first inverter 301 is connected to the terminal OUT of the Nth inverter 301, and the terminal OUT of the Nth inverter 301 is connected to the terminal f of the first ring oscillator circuit 102. _out1 connection.

As shown in Figure 3, the source of the NMOS transistor 303 of the 1st inverter 301, ..., the source of the NMOS transistor 303 of the ith inverter 301, ..., the NMOS transistor 303 of the Nth inverter 301 The source of the corresponding first memristor module 304 is connected to the terminal I _out1 , ..., the terminal I _outi of the i-th memristor module 304, ..., the terminal I _outN of the N-th memristor module 304; The source of the PMOS transistor 302 of the 1 inverter 301, ..., the source of the PMOS transistor 302 of the i-th inverter 301, ..., the source of the PMOS transistor 302 of the N-th inverter 301 are respectively connected to the first The terminal A _vdd1 of the ring oscillator circuit 102 is connected.

As shown in FIG. 3 , the terminals V _chlg1 , . . . of the first memristor module 304, the terminals V _chlgi , . _. . 1 The terminal A _chlg1 of the ring oscillator circuit 102 is connected to the terminals V _rd1 , . . . of the first memristor module 304, the terminals V _rdi , . . . The terminals V _rdN are respectively connected to the terminals Ar _rd1 of the first ring oscillator circuit 102, the terminals V _cr01 , . . . of the first memristor module 304, the terminals V _cr0i , . . . The terminal V _cr0N of the memristor module 304 is respectively connected to the terminal A _cr01 of the first ring oscillator circuit 102, the terminal V _dly1 of the first memristor module 304, ..., the terminal V _dlyi of the i-th memristor module 304 , ..., the terminal V _dlyN of the Nth memristor module 304 is respectively connected to the terminal A _dly1 of the first ring oscillator circuit 102, and the terminal V _cr11 of the first memristor module 304, ..., the i-th memristor The terminals _{V cr1i , .} , the terminals _{V ci1 , .} , A _cN1 connection; the terminal V _rs1 of the first memristor module 304, ..., the terminal V _rsi of the i-th memristor module 304, ..., the terminal V _rsN of the Nth memristor module 304 are respectively connected to the first The terminal A _rs1 of the ring oscillator circuit 102 is connected to the terminals V _cr21 , . . . of the first memristor module 304, the terminals V _cr2i , . . . V _cr2N is connected to terminals A _cr21 of the first ring oscillator circuit 102, respectively.

The second ring oscillator circuit 106 has the same structure as the first ring oscillator circuit 102 .

As shown in Figure 4, the structure of the first memristor module 304 is that the terminal OUT of the first gate 401 is connected to the terminal 0_CHAN of the second gate 402, and the terminal 1_CHAN of the second gate 402 is connected to the terminal 0_CHAN of the second gate 402. GND connection, the terminal OUT of the second selector 402 is connected to the terminal 1_CHAN of the third selector 403, the terminal 0_CHAN of the third selector 403 is connected to GND, the terminal OUT of the third selector 403 is connected to the module memristor The terminal R _M0 of the device 404 is connected; the drain of the NMOS transistor 409 is connected to the terminal R _M0 of the module memristor 404, and the source of the NMOS transistor 409 is connected to the terminal R _M1 of the module memristor 404; the first shunt 405 The terminal IN of the module memristor 404 is connected to the terminal R _M1 of the module, the terminal 1_CHAN of the first shunt 405 is connected to the terminal IN of the second shunt 406; the terminal 1_CHAN of the second shunt 406 is connected to the mirror current source 407 The terminal I _ref of the second shunt 406 is connected to the terminal R ₀ of the current limiting resistor 408 , and the terminal R ₁ of the current limiting resistor 408 is connected to GND.

As shown in FIG. 4 , the terminals 1_CHAN, 0_CHAN, and SEL of the first gate 401 are connected to the corresponding terminals V _chlg1 , V _rd1 , and V _cr01 of the first memristor module 304, and the terminals SEL of the second gate 402 are connected to The terminal V _dly1 of the first memristor module 304 is connected, the terminal SEL of the third gate 403 is connected with the terminal V _cr11 of the first memristor module 304; the gate of the NMOS transistor 409 is connected with the first memristor module 304 The terminal V _c11 of the first splitter 405 is connected to the terminal V _cr11 of the first splitter 405 and the terminal V cr11 of the first memristor module 304, and the terminal 0_CHAN of the first splitter 405 is connected to the terminal V _rs1 of the first memristor module 304 connection, the terminal SEL of the second shunt 406 is connected to the terminal V _cr21 of the first memristor module 304; the terminal I _out of the mirror current source 407 is connected to the terminal I _out1 of the first memristor module 304.

The structure of the second memristor module 304 , . . . , the i-th memristor module 304 , .

The delay circuit memristor 201 and the module memristor 404 are the same, both are memristors with a threshold voltage; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in a high impedance state.

The method of using the memristor-based ring oscillator PUF circuit:

Step 1. Reset all memristors

Apply a low-level voltage signal U _cr1 between the voltage input terminal V _cr1 and the terminal GND, apply a high-level voltage signal U rs between the voltage input terminal V _rs and the terminal GND, and apply a high-level voltage signal U _rs between the voltage input terminal V cr1 and the terminal GND. No voltage signal is applied between them.

Step 2. Apply incentives

Apply corresponding high-level voltage signals U _pl , U _chlg , U _cr0 , U _cr1 between the voltage input terminals _{V pl} , V _chlg , V _cr0 , V _cr1 and the terminal GND. , V _ci , ..., V _cN and terminal GND apply corresponding high-level or low-level excitation voltage signals U _c1 , ..., U _ci , ..., U _cN ; between voltage input terminals V _cr2 and A low-level voltage signal U _cr2 is applied between the terminals GND, and no voltage signal is applied between the other voltage input terminals and the terminal GND.

Step 3. Response output

Apply corresponding high-level voltage signals U _vdd , U _rd , U _{cr1 , U cr2 between} the voltage input terminals V _vdd , V _rd , V _cr1 , V _cr2 and the terminal GND, and between the voltage input terminals V _cr0 and the terminal GND A low-level voltage signal U _cr0 is applied between them, and no voltage signal is applied between the other voltage input terminals and the terminal GND.

The terminal R _out of the digital comparator 104 outputs a response voltage.

Example 1

A memristor-based ring oscillator PUF circuit and a method of use thereof.

As shown in Figure 5, the ring oscillator PUF circuit based on memristor is composed of random delay circuit 101, the first ring oscillator circuit 102, the second ring oscillator circuit 106, the first counter 103, the second counter 105 and digital comparator 104.

As shown in Figure 5, the terminal V _pulse of the random delay circuit 101 is connected to the voltage input terminal V _pl , and the terminals V _c12 , V _c22 , V _c32 of the random delay circuit 101 are connected to the corresponding voltage input terminals V _c1 , V _c2 , V _c3 Connection: The terminal V _delay of the random delay circuit 101 is connected to the terminal A _dly1 of the first ring oscillator circuit 102 and the terminal A _dly2 of the second ring oscillator circuit 106 respectively.

The terminal A vdd1 of the first ring oscillator circuit 102 and the terminal A _vdd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _vdd , and the terminal A _chlg1 of the first ring oscillator circuit ₁₀₂ and the second ring oscillator circuit The terminal A _chlg2 of 106 is respectively connected to the voltage input terminal V _chlg , the terminal A _rd1 of the first ring oscillator circuit 102, and the terminal A _rd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rd , and the first ring oscillator circuit The terminal A cr01 of the oscillator circuit 102 and the terminal A _cr02 of the second ring oscillator circuit 106 are connected to the voltage input terminal V _cr0 respectively, and the terminal A _cr11 of the first ring oscillator circuit 102 and the terminal A _of the second ring oscillator circuit 106 _cr12 are connected to voltage input terminals V _cr1 respectively; terminals A _c11 , A _c21 , and A _c31 of the first ring oscillator circuit 102 are connected to corresponding voltage input terminals V _c1 , V _c2 , and V _c3 , and the second ring oscillator circuit 106 The terminals A _c12 , A _c22 , and A _c32 are connected to the corresponding voltage input terminals V _c1 , V _c2 , and V _c3 ; the terminal A _rs1 of the first ring oscillator circuit 102 and the terminal A _rs2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rs ; the terminal A _cr21 of the first ring oscillator circuit 102 and the terminal A _cr22 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _cr2 ; the terminal f of the first ring oscillator circuit 102 _out1 is connected to the terminal _A10 of the first counter 103 , and the terminal f _out2 of the second ring oscillator circuit 106 is connected to the terminal _A20 of the second counter 105 .

The terminal A11 of the first counter 103 is connected to the terminal _IN0 of the digital comparator 104, the terminal _A21 of the second counter 105 is connected to the terminal IN1 _of the digital comparator 104, and the terminal _Rout of the digital comparator ₁₀₄ outputs a response voltage.

_Apply corresponding voltage signals U _pl , U _vdd , U _chlg , U _rd , U between voltage input terminals V _pl , V _vdd , V _chlg , V _rd , V _cr0 , V cr1, V _rs , V _cr2 and terminal GND _cr0 , U cr1 , U _rs , U _cr2 apply corresponding voltage signals U _c1 , U _c2 , U _{c3 between} the voltage input terminals V _c1 , V _c2 , V _c3 and the terminal GND.

The terminal R _out of the digital comparator 104 outputs a response voltage.

As shown in Figure 6, the random delay circuit 101 is composed of three delay units 202 and NMOS transistors 204; the terminal OUT of the first delay unit 202 is connected to the terminal IN of the second delay unit 202, and the terminal of the second delay unit 202 OUT is connected to the terminal IN of the third delay unit 202 , and the terminal OUT of the third delay unit 202 is connected to the drain of the NMOS transistor 204 .

As shown in Figure 6, the terminal IN of the first delay unit 202 is respectively connected to the terminal A _R0 of the two delay circuit memristors 201, and the terminal A _R1 of the two delay circuit memristors 201 is connected to the first delay circuit selector Terminal 1_CHAN and terminal 0_CHAN of 203 are correspondingly connected; the structure of the second delay unit 202 and the third delay unit 202 is the same as that of the first delay unit 202 .

As shown in Figure 6, the terminal IN of the first delay unit 202 is connected to the terminal V _pulse of the random delay circuit 101, and the terminal OUT of the third delay unit 202 is connected to the terminal V _delay of the random delay circuit 101; The terminal SEL, the terminal SEL of the second delay unit 202 , and the terminal SEL of the third delay unit 202 are connected to the corresponding terminals V _c12 , V _c22 , and V _c32 of the random delay circuit 101 .

As shown in Figure 7, the first ring oscillator circuit 102 is composed of three inverters 301 and three memristor modules 304; the terminal OUT of the first inverter 301 is connected to the terminal of the second inverter 301 IN connection, the terminal OUT of the second inverter 301 is connected to the terminal IN of the third inverter 301; the terminal IN of the first inverter 301 is connected to the terminal OUT of the third inverter 301, and the third inverter The terminal OUT of 301 is connected to the terminal f _out1 of the first ring oscillator circuit 102 .

As shown in Figure 7, the source of the NMOS transistor 303 of the first inverter 301, the source of the NMOS transistor 303 of the second inverter 301, the source of the NMOS transistor 303 of the third inverter 301 and the corresponding The terminal I _out1 of the first memristor module 304, the terminal I _out2 of the second memristor module 304, and the terminal I _out3 of the third memristor module 304 are connected; the source of the PMOS transistor 302 of the first inverter 301 The source of the PMOS transistor 302 of the second inverter 301 and the source of the PMOS transistor 302 of the third inverter 301 are respectively connected to the terminal A _vdd1 of the first ring oscillator circuit 102 .

As shown in FIG. 7 , the terminal V chlg1 of the first memristor module 304, the terminal V _chlg2 of the second memristor module 304, and the terminal V _chlg3 of the third memristor module 304 are _connected to the first ring oscillator circuit 102 respectively. The terminal A _chlg1 of the first memristor module 304 is connected, the terminal V _rd1 of the first memristor module 304, the terminal V _rd2 of the second memristor module 304, and the terminal V _rd3 of the third memristor module 304 are respectively connected to the first ring oscillator circuit 102 The terminal _{Ar rd1} of the first memristor module 304 is connected, the terminal V cr01 of the first memristor module 304, the terminal V _cr02 of the second memristor module 304, and the terminal V _cr03 of the third memristor module 304 _are respectively connected to the first ring oscillator circuit 102 The terminal A _cr01 of the first memristor module 304 is connected, the terminal V dly1 of the first memristor module 304, the terminal V _dly2 of the second memristor module 304, and the terminal V _dly3 of the third memristor module 304 _are respectively connected with the first ring oscillator circuit 102 The terminal A _dly1 of the first memristor module 304 is connected, the terminal V cr11 of the first memristor module 304, the terminal V _cr12 of the second memristor module 304, and the terminal V _cr13 of the third memristor module 304 _are respectively connected to the first ring oscillator circuit 102 The terminal A _cr11 of the first memristor module 304 is connected, the terminal V _c11 of the first memristor module 304, the terminal V _c21 of the second memristor module 304, the terminal V _c31 of the third memristor module 304 and the corresponding first ring oscillator circuit The terminals A _c11 , A _c21 , and A _c31 of 102 are connected; the terminal V _rs1 of the first memristor module 304, the terminal V _rs2 of the second memristor module 304, and the terminal V _rs3 of the third memristor module 304 are respectively connected to The terminal A _rs1 of the first ring oscillator circuit 102 is connected, and the terminal V cr21 of the first memristor module 304, the terminal V _cr22 of the second memristor module 304, and the terminal V _cr23 of the third memristor module 304 _are respectively connected to The terminal _Acr21 of the first ring oscillator circuit 102 is connected.

The second ring oscillator circuit 106 has the same structure as the first ring oscillator circuit 102 .

As shown in Figure 4, the structure of the first memristor module 304 is that the terminal OUT of the first gate 401 is connected to the terminal 0_CHAN of the second gate 402, and the terminal 1_CHAN of the second gate 402 is connected to the terminal 0_CHAN of the second gate 402. GND connection, the terminal OUT of the second selector 402 is connected to the terminal 1_CHAN of the third selector 403, the terminal 0_CHAN of the third selector 403 is connected to GND, the terminal OUT of the third selector 403 is connected to the module memristor The terminal R _M0 of the device 404 is connected; the drain of the NMOS transistor 409 is connected to the terminal R _M0 of the module memristor 404, and the source of the NMOS transistor 409 is connected to the terminal R _M1 of the module memristor 404; the first shunt 405 The terminal IN of the module memristor 404 is connected to the terminal R _M1 of the module, the terminal 1_CHAN of the first shunt 405 is connected to the terminal IN of the second shunt 406; the terminal 1_CHAN of the second shunt 406 is connected to the mirror current source 407 The terminal I _ref of the second shunt 406 is connected to the terminal R ₀ of the current limiting resistor 408 , and the terminal R ₁ of the current limiting resistor 408 is connected to GND.

As shown in FIG. 4 , the terminals 1_CHAN, 0_CHAN, and SEL of the first gate 401 are connected to the corresponding terminals V _chlg1 , V _rd1 , and V _cr01 of the first memristor module 304, and the terminals SEL of the second gate 402 are connected to The terminal V _dly1 of the first memristor module 304 is connected, the terminal SEL of the third gate 403 is connected with the terminal V _cr11 of the first memristor module 304; the gate of the NMOS transistor 409 is connected with the first memristor module 304 The terminal V _c11 of the first splitter 405 is connected to the terminal V _cr11 of the first splitter 405 and the terminal V cr11 of the first memristor module 304, and the terminal 0_CHAN of the first splitter 405 is connected to the terminal V _rs1 of the first memristor module 304 connection, the terminal SEL of the second shunt 406 is connected to the terminal V _cr21 of the first memristor module 304; the terminal I _out of the mirror current source 407 is connected to the terminal I _out1 of the first memristor module 304.

Both the second memristor module 304 and the third memristor module 304 have the same structure as the first memristor module 304 .

The delay circuit memristor 201 and the module memristor 404 are the same, both are memristors with a threshold voltage; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in a high impedance state.

The method of using the memristor-based ring oscillator PUF circuit:

Step 1. Reset all memristors

Apply a low-level voltage signal U _cr1 = 0V between the voltage input terminal V _cr1 and the terminal GND; apply a high-level voltage signal U _rs = 2V between the voltage input terminal V _rs and the terminal GND; other voltage input terminals Do not apply any voltage signal to terminal GND.

In step one, all module memristors 404 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 are reset to a high-impedance state:

In the first ring oscillator circuit 102: the resistance values of the respective module memristors 404 in the first memristor module 304, the second memristor module 304, and the third memristor module 304 are 9474Ω, 10502Ω, and 11121Ω in turn. ;

In the second ring oscillator circuit 106: the resistance values of the respective module memristors 404 in the first memristor module 304, the second memristor module 304, and the third memristor module 304 are 8325Ω, 11718Ω, and 11103Ω in turn. .

Step 2. Apply incentives

Apply corresponding high-level voltage signals U _pl =2V, U _chlg =2V, U _cr0 =1.8V, U _cr2 =1.8V between the voltage input terminals V _pl , V _chlg , V _cr0 , V _cr1 and the terminal GND ;Apply corresponding high-level or low-level excitation voltage signals U _c1 =1.8V, U _c2 =1.8V, U _c3 =1.8V between the voltage input terminals V _c1 , V _c2 , V _c3 and the terminal GND; A low-level voltage signal U _cr2 =0V is applied between the voltage input terminal V _cr2 and the terminal GND; no voltage signal is applied between the other voltage input terminals and the terminal GND.

In step 2, the resistance values of all the module memristors 404 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 are randomly reduced, and the reduced resistance values are:

In the first ring oscillator circuit 102: the resistance values of the respective module memristors 404 in the first memristor module 304, the second memristor module 304, and the third memristor module 304 are 9275Ω, 10252Ω, and 10837Ω in turn. ;

In the second ring oscillator circuit 106: the resistance values of the respective module memristors 404 in the first memristor module 304, the first memristor module 304, and the third memristor module 304 are 8175Ω, 11399Ω, and 10820Ω in turn. .

Step 3. Response output

Apply corresponding high-level voltage signals U _vdd =5V, U _rd =1.5V, U _cr1 =1.8V, U _cr2 =1.8 between the voltage input terminals V _vdd , V _rd , V _cr1 , V _cr2 and the terminal GND V; a low-level voltage signal U _cr0 =0V is applied between the voltage input terminal V _cr0 and the terminal GND; no voltage signal is applied between the other voltage input terminals and the terminal GND.

The terminal R _out of the digital comparator 104 outputs a response voltage.

In step three, the oscillation frequency of the square wave generated by the first ring oscillator circuit 102 is f ₁ =2.468KH _Z , and the oscillation frequency of the square wave generated by the second ring oscillator circuit 106 is f ₂ =2.471KH _Z .

The terminal R _out of the digital comparator 104 outputs a response voltage of 0V.

Example 2

A memristor-based ring oscillator PUF circuit and a method of use thereof.

As shown in Figure 8, the ring oscillator PUF circuit based on memristor is composed of random delay circuit 101, the first ring oscillator circuit 102, the second ring oscillator circuit 106, the first counter 103, the second counter 105 and digital comparator 104.

As shown in FIG. 8 , the terminal V _pulse of the random delay circuit 101 is connected to the voltage input terminal V _p1 , and the terminals V _c12 , V _c22 , V _c32 , V _c42 , V _c52 of the random delay circuit 101 are connected to the corresponding voltage input terminal V _c1 , V _c2 , V _c3 , V _c4 , and V _c5 are connected; the terminal V _delay of the random delay circuit 101 is connected to the terminal _Adly1 of the first ring oscillator circuit 102 and the terminal _Adly2 of the second ring oscillator circuit 106, respectively.

The terminal A vdd1 of the first ring oscillator circuit 102 and the terminal A _vdd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _vdd , and the terminal A _chlg1 of the first ring oscillator circuit ₁₀₂ and the second ring oscillator circuit The terminal A _chlg2 of 106 is respectively connected to the voltage input terminal V _chlg , the terminal A _rd1 of the first ring oscillator circuit 102, and the terminal A _rd2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rd , and the first ring oscillator circuit The terminal A cr01 of the oscillator circuit 102 and the terminal A _cr02 of the second ring oscillator circuit 106 are connected to the voltage input terminal V _cr0 respectively, and the terminal A _cr11 of the first ring oscillator circuit 102 and the terminal A _of the second ring oscillator circuit 106 _cr12 are respectively connected to voltage input terminals V _cr1 ; terminals A _c11 , A _c21 , A _c31 , A _c41 , A _c51 of the first ring oscillator circuit 102 are connected to corresponding voltage input terminals V _c1 , V _c2 , V _c3 , V _c4 , V _c5 are connected, the terminals A _c12 , A _c22 , A _c32 , A _c42 , A _c52 of the second ring oscillator circuit 106 are connected to the corresponding voltage input terminals V _c1 , V _c2 , V _c3 , V _c4 , V _c5 ; The terminal A _rs1 of the first ring oscillator circuit 102 and the terminal A _rs2 of the second ring oscillator circuit 106 are respectively connected to the voltage input terminal V _rs ; the terminal A _cr21 of the first ring oscillator circuit 102 and the terminal A rs2 of the second ring oscillator circuit The terminal A _cr22 of 106 is respectively connected with the voltage input terminal V _cr2 ; the terminal f _out1 of the first ring oscillator circuit 102 is connected with the terminal _A10 of the first counter 103, and the terminal f _out2 of the second ring oscillator circuit 106 is connected with the second The terminal A ₂₀ of the counter 105 is connected.

The terminal A11 of the first counter 103 is connected to the terminal _IN0 of the digital comparator 104, the terminal _A21 of the second counter 105 is connected to the terminal IN1 _of the digital comparator 104, and the terminal _Rout of the digital comparator ₁₀₄ outputs a response voltage.

_Apply corresponding voltage signals U _pl , U _vdd , U _chlg , U _rd , U between voltage input terminals V _pl , V _vdd , V _chlg , V _rd , V _cr0 , V cr1, V _rs , V _cr2 and terminal GND _cr0 , U cr1 , U _rs , U _cr2 , apply corresponding voltage signals U _c1 , U _c2 , U _c3 , U _{c4 between} voltage input terminals V _c1 , V _c2 , V _c3 , V _c4 , V _c5 and terminal GND , U _c5 .

The terminal R _out of the digital comparator 104 outputs a response voltage.

As shown in Figure 9, the random delay circuit 101 is composed of five delay units 202 and NMOS transistors 204; the terminal OUT of the first delay unit 202 is connected to the terminal IN of the second delay unit 202, and the terminal of the second delay unit 202 OUT is connected to the terminal IN of the 3rd delay unit 202, the terminal OUT of the 3rd delay unit 202 is connected to the terminal IN of the 4th delay unit 202, the terminal OUT of the 4th delay unit 202 is connected to the terminal IN of the 5th delay unit 202, The terminal OUT of the fifth delay unit 202 is connected to the drain of the NMOS transistor 204 .

As shown in Figure 9, the terminal IN of the first delay unit 202 is respectively connected to the terminal A _R0 of the two delay circuit memristors 201, and the terminal A _R1 of the two delay circuit memristors 201 is connected to the first delay circuit selector Terminal 1_CHAN and terminal 0_CHAN of 203 are correspondingly connected; the structure of the second delay unit 202 , the third delay unit 202 , the fourth delay unit 202 , and the fifth delay unit 202 is the same as that of the first delay unit 202 .

As shown in Figure 9, the terminal IN of the first delay unit 202 is connected to the terminal V _pulse of the random delay circuit 101, and the terminal OUT of the Nth delay unit 202 is connected to the terminal V _delay of the random delay circuit 101; The terminal SEL, the terminal SEL of the second delay unit 202, the terminal SEL of the third delay unit 202, the terminal SEL of the fourth delay unit 202, the terminal SEL of the fifth delay unit 202 and the corresponding terminals _Vc12 , V _c22 , V _c32 , V _c42 , and V _c52 are connected.

As shown in Figure 10, the first ring oscillator circuit 102 is composed of five inverters 301 and five memristor modules 304; the terminal OUT of the first inverter 301 is connected to the terminal of the second inverter 301 IN connection, the terminal OUT of the second inverter 301 is connected to the terminal IN of the third inverter 301, the terminal OUT of the third inverter 301 is connected to the terminal IN of the fourth inverter 301, the fourth inverter The terminal OUT of 301 is connected with the terminal IN of the 5th inverter 301; The terminal IN of the 1st inverter 301 is connected with the terminal OUT of the 5th inverter 301, the terminal OUT of the 5th inverter 301 is connected with the first ring The terminal f _out1 of the oscillator circuit 102 is connected.

As shown in FIG. 10, the source of the NMOS transistor 303 of the first inverter 301, the source of the NMOS transistor 303 of the second inverter 301, the source of the NMOS transistor 303 of the third inverter 301, the fourth The source of the NMOS transistor 303 of the inverter 301, the source of the NMOS transistor 303 of the fifth inverter 301 and the corresponding terminal I _out1 of the first memristor module 304 and the terminal I of the second memristor module 304 _out2 , the terminal I _out3 of the 3rd memristor module 304 is connected, the terminal I _out4 of the 4th memristor module 304 is connected, the terminal I _out5 of the 5th memristor module 304 is connected; the PMOS transistor of the first inverter 301 302, the source of the PMOS transistor 302 of the second inverter 301, the source of the PMOS transistor 302 of the third inverter 301, the source of the PMOS transistor 302 of the fourth inverter 301, the fifth inverter The sources of the PMOS transistors 302 of the phase controller 301 are respectively connected to the terminal A _vdd1 of the first ring oscillator circuit 102 .

As shown in FIG. 10 , the terminal V chlg1 of the first memristor module 304, the terminal V _chlg2 of the second memristor module 304, the terminal V _chlg3 of the third memristor module 304, and the terminal V _chlg3 of the fourth memristor module 304 The terminal V chlg4 and the terminal V _chlg5 of the fifth memristor module 304 are respectively connected to the terminal A _chlg1 of the first ring oscillator circuit 102, and the terminal V _{rd1 of the first memristor module 304 and the terminal V chlg1 of} the second memristor module 304 are connected to each other. The terminal V _rd2 , the terminal V rd3 of the third memristor module 304 , the terminal V _rd4 of the fourth memristor module 304 , the terminal V _rd5 of the fifth memristor module 304 _are respectively connected to the terminals of the first ring oscillator circuit 102 A _rd1 connection, terminal V cr01 of the first memristor module 304, terminal V _cr02 of the second memristor module 304, terminal V _cr03 of the third memristor module 304, terminal V _of the fourth memristor module 304 _cr04 and the terminal V _cr05 of the fifth memristor module 304 are respectively connected to the terminal A _cr01 of the first ring oscillator circuit 102, the terminal V _dly1 of the first memristor module 304, the terminal V of the second memristor module 304 _dly2 , the terminal V dly3 of the third memristor module 304 , the terminal V _dly4 of the fourth memristor module 304 respectively, the terminal V _dly5 of the fifth memristor module 304 and the terminal _A of the first ring oscillator circuit 102 respectively _dly1 connection, terminal V cr11 of the first memristor module 304, terminal V _cr12 of the second memristor module 304, terminal V _cr13 of the third memristor module 304, terminal V _cr14 of the _fourth memristor module 304 , the terminal V _cr15 of the fifth memristor module 304 is respectively connected to the terminal A _cr11 of the first ring oscillator circuit 102; the terminal V _c11 of the first memristor module 304, the terminal V _c21 of the second memristor module 304 , the terminal V _c31 of the third memristor module 304, the terminal V c41 of the fourth memristor module 304, the terminal V _c51 of the fifth memristor module 304 _, and the corresponding terminal A _c11 of the first ring oscillator circuit 102 , A _c21 , A _c31 , A _c41 , and A _c51 are connected; the terminal V _rs1 of the first memristor module 304, the terminal V _rs2 of the second memristor module 304, the terminal V _rs3 of the third memristor module 304, The terminal V _rs4 of the fourth memristor module 304 and the terminal V _rs5 of the fifth memristor module 304 are respectively connected to the terminal A _rs1 of the first ring oscillator circuit 102, and the terminals V _cr21 , The terminal V _cr22 of the second memristor module 304, the terminal V _cr23 of the third memristor module 304, the fourth The terminal V cr24 of the memristor module 304 and the terminal V _cr25 of the fifth memristor module 304 are _respectively connected to the terminal _Acr21 of the first ring oscillator circuit 102 .

The second ring oscillator circuit 106 has the same structure as the first ring oscillator circuit 102 .

The structure of the first memristor module 304 in this embodiment is the same as the structure of the first memristor module 304 in the first embodiment.

The structure of the second memristor module 304 , the third memristor module 304 , the fourth memristor module 304 and the fifth memristor module 304 is the same as that of the first memristor module 304 .

The delay circuit memristor 201 and the module memristor 404 are the same, both are memristors with a threshold voltage; the initial states of the delay circuit memristor 201 and the module memristor 404 are both in a high impedance state.

The method of using the memristor-based ring oscillator PUF circuit:

Step 1. Reset all memristors

Apply a low-level voltage signal U _cr1 = 0V between the voltage input terminal V _cr1 and the terminal GND; apply a high-level voltage signal U _rs = 2V between the voltage input terminal V _rs and the terminal GND; other voltage input terminals Do not apply any voltage signal to terminal GND.

In step one, all module memristors 404 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 are reset to a high-impedance state:

In the first ring oscillator circuit 102: each of the first memristor module 304, the second memristor module 304, the third memristor module 304, the fourth memristor module 304, and the fifth memristor module 304 The resistance values of the module memristor 404 are 11572Ω, 10813Ω, 10223Ω, 8738Ω, 8848Ω in turn;

In the second ring oscillator circuit 106: each of the first memristor module 304, the second memristor module 304, the third memristor module 304, the fourth memristor module 304, and the fifth memristor module 304 The resistance values of the module memristor 404 are 8309Ω, 11655Ω, 10827Ω, 10231Ω, 9254Ω in sequence.

Step 2. Apply incentives

Apply corresponding high-level voltage signals U _pl =2V, U _chlg =2V, U _cr0 =1.8V, U _cr2 =1.8V between the voltage input terminals V _pl , V _chlg , V _cr0 , V _cr1 and the terminal GND ; Apply corresponding _high -level or low-level _excitation voltage signals U _{c1 = 1.8V} , U _c2 = _1.8V , U _c3 =1.8V, U _c4 =1.8V, U _c5 =0V; a low-level voltage signal U _cr2 =0V is applied between the voltage input terminal V _cr2 and the terminal GND; Apply any voltage signal.

In step 2, the resistance values of all the module memristors 404 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 are randomly reduced, and the reduced resistance values are:

In the first ring oscillator circuit 102: each of the first memristor module 304, the second memristor module 304, the third memristor module 304, the fourth memristor module 304, and the fifth memristor module 304 The resistance values of the module memristor 404 are 10920Ω, 10250Ω, 9725Ω, 8385Ω, 8848Ω in sequence;

In the second ring oscillator circuit 106: each of the first memristor module 304, the second memristor module 304, the third memristor module 304, the fourth memristor module 304, and the fifth memristor module 304 The resistance values of the module memristor 404 are 7994Ω, 10993Ω, 10263Ω, 9733Ω, 9254Ω in turn.

Step 3. Response output

Apply corresponding high-level voltage signals U _vdd =5V, U _rd =1.5V, U _cr1 =1.8V, U _cr2 =1.8 between the voltage input terminals V _vdd , V _rd , V _cr1 , V _cr2 and the terminal GND V; a low-level voltage signal U _cr0 =0V is applied between the voltage input terminal V _cr0 and the terminal GND; no voltage signal is applied between the other voltage input terminals and the terminal GND.

The terminal R _out of the digital comparator 104 outputs a response voltage.

In step three, the oscillation frequency of the square wave generated by the first ring oscillator circuit 102 is f ₁ =3.912KH _Z , and the oscillation frequency of the square wave generated by the second ring oscillator circuit 106 is f ₂ =3.921KH _Z ;

The terminal R _out of the digital comparator 104 outputs a response voltage of 0V.

In this specific embodiment, the randomness of the resistance value distribution when the module memristor 404 is in a high-impedance state is used as the main entropy source of the memristor-based ring oscillator PUF circuit. In step 1, a correlation is applied to the memristor module 304. voltage signal to reset all module memristors 404 in the memristor-based ring oscillator PUF circuit to a high-impedance state. In step 2, the memristor-based ring oscillator PUF circuit selects part of the module memristors 404 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 according to the input excitation voltage signal, and the selected modules The memristor 404 applies a high-level voltage signal U _chlg , under the action of the random delay circuit 101, the duration of the high-level voltage signal U _chlg applied to the module memristor 404 is random, and the selected module memristor The device 404 performs a random resistance reduction in the high resistance state. In step three, the first ring oscillator circuit 102 and the second ring oscillator circuit 106 start to oscillate, and the first ring oscillator circuit 102 and the second ring oscillator circuit 106 are controlled by the first counter 103 and the second counter 105 respectively The pulses of the generated square wave are counted, and finally the counted value is compared by the digital comparator 104 to obtain a response.

This embodiment has the following positive effects:

In this specific embodiment, in step 2, the memristor-based ring oscillator PUF circuit selects the module memristor 404 in the memristor module 304 according to the applied excitation voltage signal, and conducts a process on the selected module memristor 404 once. The random resistance decreases, the excitation voltage signal is different, the selected module memristor 404 is also different, and the resistance value reduction of the selected module memristor 404 is also different, resulting in different excitation voltage signals. The resistance value of the module memristor 404 in the ring oscillator PUF circuit is also different, that is, the parameters of the ring oscillator PUF circuit based on the memristor are different. With the change of the excitation voltage signal, the ring oscillator PUF circuit based on the memristor The parameters of the memristor also change accordingly, which makes it difficult for the machine learning algorithm to accurately establish the mathematical model of the memristor-based ring oscillator PUF circuit, so it has a significant ability to resist machine learning.

In this specific embodiment, the randomness of the resistance value distribution when the module memristor 404 in the memristor module 304 is in a high-impedance state is used as the entropy source of the ring oscillator PUF circuit based on the memristor, the delay in the random delay circuit 101 When the circuit memristor 201 is in a high-impedance state, the randomness of the resistance value distribution also serves as the entropy source of the ring oscillator PUF circuit based on the memristor, so it has dual entropy sources, and the core performance index is good.

This specific embodiment only needs two ring oscillator circuits to generate multi-bit CRP pairs, and increasing the number of CRP pairs only needs to increase the inverter 301 in the first ring oscillator circuit 102 and the second ring oscillator circuit 106 and the number of memristor modules 304 corresponding to the inverter 301, so the expandability is strong and the hardware consumption is small.

Therefore, this embodiment has the characteristics of strong machine learning resistance, low hardware consumption and good core performance indicators.

Claims (2)

1. A memristor-based ring oscillator (PUF) circuit, wherein:

the memristor-based ring oscillator PUF circuit is composed of a random delay circuit (101), a 1 st ring oscillator circuit (102), a 2 nd ring oscillator circuit (106), a 1 st counter (103), a 2 nd counter (105) and a digital comparator (104);

terminal V of random delay circuit (101) _pulse And voltage input terminal V _pl Terminal V of connection, random delay circuit (101) _c12 、……、V _ci2 、……、V _cN2 With corresponding voltage input terminal V _c1 、……、V _ci 、……、V _cN Connecting; terminal V of random delay circuit (101) _delay And terminal A of the 1 st ring oscillator circuit (102) _dly1 And terminal A of the 2 nd ring oscillator circuit (106) _dly2 Are respectively connected;

terminal A of 1 st ring oscillator circuit (102) _vdd1 Terminal A of the 2 nd ring oscillator circuit 106 _vdd2 Respectively connected with voltage input terminal V _vdd Connected, terminal A of the 1 st ring oscillator circuit (102) _chlg1 Terminal A of the 2 nd ring oscillator circuit 106 _chlg2 Respectively connected with voltage input terminal V _chlg Connected to terminal A of the 1 st ring oscillator circuit (102) _rd1 Terminal A of the 2 nd ring oscillator circuit 106 _rd2 Respectively connected with voltage input terminal V _rd Connected, terminal A of the 1 st ring oscillator circuit (102) _cr01 Terminal A of the 2 nd ring oscillator circuit 106 _cr02 Respectively connected with voltage input terminal V _cr0 Connected to terminal A of the 1 st ring oscillator circuit (102) _cr11 Terminal A of the 2 nd ring oscillator circuit 106 _cr12 Respectively connected with voltage input terminal V _cr1 Connecting; terminal A of 1 st ring oscillator circuit (102) _c11 、……、A _ci1 、……、A _cN1 With corresponding voltage input terminal V _c1 、……、V _ci 、……、V _cN Connected to terminal A of the 2 nd ring oscillator circuit (106) _c12 、……、A _ci2 、……、A _cN2 With corresponding voltage input terminal V _c1 、……、V _ci 、……、V _cN Connecting; terminal A of 1 st ring oscillator circuit (102) _rs1 And terminal A of the 2 nd ring oscillator circuit (106) _rs2 Respectively connected with voltage input terminal V _rs Connecting; terminal A of 1 st ring oscillator circuit (102) _cr21 Terminal A of the 2 nd ring oscillator circuit 106 _cr22 Are respectively connected with a voltage input terminal V _cr2 Connecting; terminal f of 1 st ring oscillator circuit (102) _out1 And a terminal A of the 1 st counter (103) ₁₀ Connected, terminal f of 2 nd ring oscillator circuit (106) _out2 And a terminal A of a 2 nd counter (105) ₂₀ Connecting;

terminal A of 1 st counter (103) ₁₁ And a terminal IN of a digital comparator (104) ₀ Connected, terminal A of the 2 nd counter (105) ₂₁ And a terminal IN of a digital comparator (104) ₁ Connected to a terminal R of a digital comparator (104) _out Outputting a response voltage;

at a voltage input terminal V _pl 、V _vdd 、V _chlg 、V _rd 、V _cr0 、V _cr1 、V _rs 、V _cr2 A voltage signal U corresponding to the voltage applied between the terminals GND _pl 、U _vdd 、U _chlg 、U _rd 、U _cr0 、U _cr1 、U _rs 、U _cr2 At a voltage input terminal V _c1 、……、V _ci 、……、V _cN A voltage signal U corresponding to the voltage applied between the terminals GND _c1 、……、U _ci 、……、U _cN (ii) a Terminal R of digital comparator (104) _out Outputting a response voltage;

the random delay circuit (101) is composed of N delay units (202) and N NMOS transistors (204), wherein N is an odd number; the terminal OUT of the 1 st delay unit (202) is connected with the terminal IN of the 2 nd delay unit (202), … …, the terminal OUT of the i-1 th delay unit (202) is connected with the terminal IN of the i-th delay unit (202), … …, the terminal OUT of the N-1 th delay unit (202) is connected with the terminal IN of the N-th delay unit (202), and the terminal OUT of the N-th delay unit (202) is connected with the drain of the NMOS transistor (204);

the terminal IN of the 1 st delay unit (202) is respectively connected with the terminals A of the two delay circuit memristors (201) _R0 Connecting terminals A of two delay circuit memristors (201) _R1 Connected to a terminal 1 _CHANand a terminal 0 _CHANof the 1 st delay line gate (203); the 2 nd delay unit (202), … …, the ith delay unit (202), … … and the Nth delay unit (202) have the same structure as the 1 st delay unit (202);

terminal IN of 1 st delay unit (202) and terminal V of random delay circuit (101) _pulse A terminal OUT of the Nth delay unit (202) and a terminal V of the random delay circuit (101) are connected _delay Connecting; terminals SEL, … … of the 1 st delay unit (202), terminals SEL, … … of the i-th delay unit (202), and terminal SEL of the N-th delay unit (202) are associated with terminal V of the corresponding random delay circuit (101) _c12 、……、V _ci2 、……、V _cN2 Connecting;

the 1 st ring oscillator circuit (102) is composed of N inverters (301) and N memristor modules (304), N being an odd number; terminal OUT of 1 st inverter 301 and 2 nd inverter 301 … …, the terminal OUT of the i-1 th inverter (301) is connected to the terminal IN of the i-th inverter (301), … …, the terminal OUT of the N-1 th inverter (301) is connected to the terminal IN of the N-1 th inverter (301); the terminal IN of the 1 st inverter 301 is connected to the terminal OUT of the Nth inverter 301, and the terminal OUT of the Nth inverter 301 is connected to the terminal f of the 1 st ring oscillator circuit 102 _out1 Connecting;

the source of the NMOS transistor (303) of the 1 st inverter (301), … …, the source of the NMOS transistor (303) of the ith inverter (301), … …, the source of the NMOS transistor (303) of the Nth inverter (301), and the corresponding terminal I of the 1 st memristor module (304) _out1 … …, terminal I of I-th memristor module (304) _outi … …, terminal I of Nth memristor module (304) _outN Connecting; the source of the PMOS transistor (302) of the 1 st inverter (301), … …, the source of the PMOS transistor (302) of the i-th inverter (301), … …, and the source of the PMOS transistor (302) of the N-th inverter (301) are connected to the terminal A of the 1 st ring oscillator circuit (102), respectively _vdd1 Connecting;

terminal V of 1 st memristor module (304) _chlg1 … …, terminal V of i-th memristor module (304) _chlgi … …, terminal V of Nth memristor module (304) _chlgN Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) _chlg1 Connecting, terminal V of 1 st memristor Module (304) _rd1 … …, terminal V of ith memristor module (304) _rdi … …, terminal V of Nth memristor module (304) _rdN Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) _rd1 Connecting, terminal V of 1 st memristor Module (304) _cr01 … …, terminal V of i-th memristor module (304) _cr0i … …, terminal V of Nth memristor module (304) _cr0N Respectively connected with terminals A of the 1 st ring oscillator circuit (102) _cr01 Connecting, terminal V of 1 st memristor Module (304) _dly1 … …, terminal V of i-th memristor module (304) _dlyi … …, terminal V of Nth memristor module (304) _dlyN Respectively connected with terminals A of the 1 st ring oscillator circuit (102) _dly1 Connecting, terminal V of 1 st memristor Module (304) _cr11 … …, terminal V of i-th memristor module (304) _cr1i … …, terminal V of Nth memristor module (304) _cr1N Respectively connected with terminals A of the 1 st ring oscillator circuit (102) _cr11 Connecting, terminal V of 1 st memristor Module (304) _c11 … …, terminal V of i-th memristor module (304) _ci1 … …, terminal V of Nth memristor module (304) _cN1 And a terminal A of a corresponding 1 st ring oscillator circuit (102) _c11 、……、A _ci1 、……、A _cN1 Connecting; terminal V of 1 st memristor module (304) _rs1 … …, terminal V of i-th memristor module (304) _rsi … …, terminal V of Nth memristor module (304) _rsN Respectively connected with terminals A of the 1 st ring oscillator circuit (102) _rs1 Connecting, terminal V of 1 st memristor Module (304) _cr21 … …, terminal V of i-th memristor module (304) _cr2i … …, terminal V of Nth memristor module (304) _cr2N Are respectively connected with the terminals A of the 1 st ring oscillator circuit (102) _cr21 Connecting;

the 2 nd ring oscillator circuit (106) is the same structure as the 1 st ring oscillator circuit (102);

the structure of the 1 st memristor module (304) is that the terminal OUT of the 1 st gating device (401) is connected with the terminal 0_CHAN of the 2 nd gating device (402), the terminal 1_CHAN of the 2 nd gating device (402) is connected with GND, the terminal OUT of the 2 nd gating device (402) is connected with the terminal 1_CHAN of the 3 rd gating device (403), the terminal 0_CHAN of the 3 rd gating device (403) is connected with GND, and the terminal OUT of the 3 rd gating device (403) is connected with the terminal R of the module memristor (404) _M0 Connecting; a drain of the NMOS transistor (409) and a terminal R of the module memristor (404) _M0 Connected, the source of the NMOS transistor (409) and the terminal R of the module memristor (404) _M1 Connecting; terminal IN of 1 st shunt (405) and terminal R of module memristor (404) _M1 A terminal 1 _CHANof the 1 st splitter (405) is connected to a terminal IN of the 2 nd splitter (406); terminal 1 of the 2 nd splitter (406) chan and terminal I of the mirror current source (407) _ref The 2 nd shunt (406) terminal 0 u CHAN is connected to the current limiting resistor (408) terminal R ₀ A terminal R connected to a current limiting resistor 408 ₁ Is connected to GNDConnecting;

the 1 st gate (401) terminals 1_CHAN, 0_CHAN, SEL and the 1 st memristor module (304) corresponding terminal V _chlg1 、V _rd1 、V _cr01 Connected, the terminal SEL of the 2 nd gate (402) and the terminal V of the 1 st memristor module (304) _dly1 Connected, the terminal SEL of the 3 rd gate (403) and the terminal V of the 1 st memristor module (304) _cr11 Connecting; a gate of the NMOS transistor (409) and a terminal V of the 1 st memristor module (304) _c11 Connecting; terminal SEL of 1 st shunt (405) and terminal V of 1 st memristor module (304) _cr11 Connecting terminal 0 _CHANof the 1 st shunt (405) with terminal V of the 1 st memristor module (304) _rs1 Connected, terminal SEL of 2 nd shunt (406) and terminal V of 1 st memristor module (304) _cr21 Connecting; terminal I of mirror current source (407) _out With terminal I of the 1 st memristor Module (304) _out1 Connecting;

the 2 nd memristor module (304), … …, the ith memristor module (304), … … and the Nth memristor module (304) are all the same as the 1 st memristor module (304) in structure;

the delay circuit memristor (201) is the same as the module memristor (404), and both the delay circuit memristor and the module memristor are memristors with threshold voltages; the initial states of the delay circuit memristor (201) and the module memristor (404) are both in a high resistance state.

2. A use method of a ring oscillator (PUF) circuit based on a memristor is characterized in that the use method is as follows:

step one, resetting all memristors

At voltage input terminal V _cr1 A voltage signal U of low level is applied between the terminal and the GND _cr1 At a voltage input terminal V _rs A high-level voltage signal U is applied between the terminal and the GND _rs No voltage signal is applied between the other voltage input terminal and the terminal GND;

step two, applying excitation

At a voltage input terminal V _pl 、V _chlg 、V _cr0 、V _cr1 Applying a high level of electricity corresponding to the terminal GNDPressure signal U _pl 、U _chlg 、U _cr0 、U _cr1 At a voltage input terminal V _c1 、……、V _ci 、……、V _cN A high-level or low-level excitation voltage signal U corresponding to the application of the terminal GND _c1 、……、U _ci 、……、U _cN (ii) a At voltage input terminal V _cr2 A voltage signal U of low level is applied between the terminal and the GND _cr2 No voltage signal is applied between the other voltage input terminal and the terminal GND;

step three, responding to output

At a voltage input terminal V _vdd 、V _rd 、V _cr1 、V _cr2 A high-level voltage signal U corresponding to the voltage applied between the terminals GND _vdd 、U _rd 、U _cr1 、U _cr2 At a voltage input terminal V _cr0 A voltage signal U of low level is applied between the terminal GND and the ground _cr0 No voltage signal is applied between the other voltage input terminal and the terminal GND;

terminal R of digital comparator (104) _out And outputting the response voltage.

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