CN109711537A - A kind of prediction circuit based on memristor neural network - Google Patents
A kind of prediction circuit based on memristor neural network Download PDFInfo
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Abstract
The invention proposes a kind of prediction circuits based on memristor neural network, solve existing artificial neural network dependent on computer, need to consume a large amount of the problem of calculating power.The present invention includes memristor neural network module, iterator, signal input module and signal output module, the input terminal of signal input module is connected with input signal, the output terminal of signal input module is connected with the first input end of iterator, second input terminal of iterator is connected with the output terminal of memristor neural network module, the output terminal of iterator is connected with the input terminal of the input terminal of memristor neural network module and signal output module respectively, the output signal of the output terminal output circuit of signal output module.The prediction result that the present invention is exported is according to the information stored in memristor neural network by training intellectual determination to made by input information, and the memristor nerve network circuit with forecast function is of great practical significance.
Description
Technical field
The present invention relates to the technical field of digital-to-analog circuit more particularly to a kind of prediction circuits based on memristor neural network.
Background technique
In recent years, artificial neural network technology is grown rapidly.Artificial neural network has been used for solving all kinds of
The problem of, solution outstanding in the various engineering fields such as pattern-recognition, automatic control, predictive estimation, biology, medicine, economy
It has determined much by the indeterminable problem of traditional calculations mode.But current artificial neural network is all based on greatly computer volume
Journey and realize, still operate on the computer based on traditional von Neumann framework, consume and a large amount of calculate power.
Hewlett-Packard in 2008 has prepared a kind of resistance with memory property in laboratory, sends out on Nature magazine
Here it is be just predicted existing 5th kind of passive electronic component memristor many years ago for text title.Since the characteristic of memristor is very similar
Cynapse in biological neural network, and there is very fast speed and extremely low energy consumption, it can be used directly to simulate biological mind
Through network, therefore many scholars begin one's study the artificial neural network based on memristor.
Artificial neural network based on memristor has been used for handling basic problem of image recognition, also it is proposed that being based on
The associative memory neural network circuit of memristor.Neural network based on memristor relies on its exclusive advantage, is widely used in more
A class brain intellectual technology direction, is greatly developed.
Summary of the invention
A large amount of the technical issues of calculating power is consumed for existing artificial neural network, the present invention proposes that one kind is based on recalling
The prediction circuit for hindering neural network, can make intelligent decision to the information being input in circuit, to export expression prediction knot
Fruit signal.
In order to achieve the above object, the technical scheme of the present invention is realized as follows: it is a kind of based on memristor neural network
Prediction circuit, including memristor neural network module, iterator, signal input module and signal output module, signal input module
Input terminal be connected with input signal, the output terminal of signal input module is connected with the first input end of iterator
It connects, the second input terminal of iterator is connected with the output terminal of memristor neural network module, the output terminal point of iterator
It is not connected with the input terminal of the input terminal of memristor neural network module and signal output module, the output of signal output module
The output signal of terminal output circuit.
The signal input module is equipped with the first clock signal, and iterator is equipped with second clock signal and third clock
Signal
The memristor neural network module includes one group of input terminal and one group of output terminal, and iterator includes one group of output
Terminal, one group of first input end and one group of second input terminal, the one group of first input end and signal of the iterator are defeated
One group of output terminal for entering module connects one to one, and signal input module is converted into input signal to meet memristor neural network
The signal that module requires simultaneously is sent to iterator, the first input end of iterator receive the signal from signal input module with
Initialize iterator；One group of second input terminal of one group of output terminal of the memristor neural network module and iterator is one by one
It is correspondingly connected with, one group of input terminal of memristor neural network module and one group of output terminal of iterator connect one to one, repeatedly
One group of input terminal of one group of output terminal and signal output module for device connects one to one, and iterator is received from recalling
The information of neural network module is hindered, and information is transmitted to by the output terminal of iterator the input of memristor neural network module
Terminal completes iterative operation；Signal output module receives the signal from iterator and the output signal after conversion.
The memristor neural network module includes the memristor array and eight voltage summation comparing units of a 8*8, memristor
The p of 8 memristors of each column is extremely connected with output terminal corresponding in iterator in array, 8 memristors of every row in memristor array
M extremely with corresponding voltage summation comparing unit be connected, voltage sum comparing unit output be 8 output terminals.
The voltage summation comparing unit includes the first operational amplifier, second operational amplifier and third operation amplifier
Device, the inverting input terminal of the first operational amplifier are connected with the pole m of memristor, and the inverting input terminal of the first operational amplifier passes through
First resistor is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier is connected with second resistance
It connects, second resistance is connected with the reverse input end of second operational amplifier, and the reverse input end of second operational amplifier passes through
3rd resistor is connected with the output end of second operational amplifier, and the first operational amplifier is same mutually defeated with second operational amplifier
Enter end to be grounded；The output end of the second operational amplifier is connected with the non-inverting input terminal of third operational amplifier, third
The inverting input terminal of operational amplifier is connected with voltage source, and the output end of third operational amplifier is memristor neural network module
An output terminal.
The iterator includes 8 iteration units being connected in parallel, and iteration unit includes that the first d type flip flop and the 2nd D are touched
Device is sent out, the input terminal of the first d type flip flop is connected with an output terminal of memristor neural network module, the first d type flip flop
Control terminal is connected with second clock signal, the output end of the first d type flip flop and the first initialization input respectively with or door
Input terminal be connected or the output end of door is connected with the input terminal of the second d type flip flop, the control terminal of the second d type flip flop with
Third clock signal is connected, and the output end of the second d type flip flop is connected with the input terminal of the first buffered gate, the first buffered gate
Output end is the output terminal of iterator；First d type flip flop and the second d type flip flop it is asynchronous set 0 end R ' with second at the beginning of
Beginningization input terminal is connected, and the asynchronous 1 end S ' of first d type flip flop and the second d type flip flop is initialized with third and inputted
Terminal is connected, the first initialization input, the second initialization input and third initialization input respectively with letter
The output terminal of number input module is connected.
The signal input module includes four groups of signal input units being connected in parallel, signal input unit and an input
Signal is connected, and signal input unit includes the first votage control switch, the second votage control switch, third votage control switch, the 4th voltage-controlled opens
Close and absolute value of voltage module, the first votage control switch, the second votage control switch, third votage control switch and the 4th votage control switch it is reversed
Control voltage input end is grounded, positive control voltage input end is connected with the first clock signal；Input signal respectively with
The input terminal of absolute value of voltage module, the input terminal of the first NOT gate, the second votage control switch the first contact be connected with output terminal I
It connects, the output end of the first NOT gate is connected with the first contact of the first votage control switch, the second contact difference of the first votage control switch
It is connected with the input terminal of resistance I and the second NOT gate, the output end of the second NOT gate is connected with output terminal II, resistance I ground connection；
Second contact of second votage control switch is connected with the input terminal of resistance II and third NOT gate respectively, the output of third NOT gate
End is connected with output terminal III, resistance II ground connection；The output end of the absolute value of voltage module and the input terminal of the 4th NOT gate
Be connected, the output end of the 4th NOT gate respectively with the input terminal of the 5th NOT gate, the first contact of the 4th votage control switch and output end
Sub- VI is connected, and the output end of the 5th NOT gate is connected with the first contact of third votage control switch, and the second of third votage control switch
Contact is connected with the input terminal of the 6th NOT gate and resistance III, and the output end of the 6th NOT gate is connected with output terminal IV, resistance
III ground connection；Second contact of the 4th votage control switch is connected with the input terminal of the 7th NOT gate and resistance IV respectively, the 7th NOT gate
Output end is connected with output terminal V, resistance IV ground connection；The output terminal I-VI iteration unit adjacent with 2 respectively
First initialization input, the second initialization input are connected with third initialization input.
The signal output module includes four groups of signal output units being connected in parallel, and each signal output unit has respectively
Two input terminals and an output end；Signal output unit includes NOT gate and door, buffered gate and resistance；Signal output unit
First input end is connected with the 11st NOT gate, the 13rd NOT gate, second with door and the 4th with the input terminal of door respectively, and signal is defeated
Out the second input terminal of unit respectively with first and the input of the input terminal of door, the input terminal, the 14th NOT gate of the 12nd NOT gate
End and the 4th is connected with another input terminal of door, and the output end of the 11st NOT gate is connected with first with another input terminal of door
Connect, the output end of the 12nd NOT gate is connected with second with another input terminal of door, the 13rd NOT gate and the 14th NOT gate it is defeated
Outlet is connected with third with the input terminal of door respectively；First passes through the second buffered gate and the first output resistance with the output end of door
It is connected, second is connected by third buffered gate with the second output resistance with the output end of door, and the output end of third and door is logical
It crosses the 4th buffered gate to be connected with third output resistance, the 4th passes through the 5th buffered gate and the 4th output resistance with the output end of door
It is connected, the first output resistance, the second output resistance, third output resistance and the 4th output resistance are used as output after being connected in parallel
End.
Beneficial effects of the present invention: when inputting an incomplete information into circuit, circuit can be according to memristor nerve
The information stored in network by training exports a prediction result by processing；The prediction result exported is that basis is recalled
Hinder the information intellectual determination to made by input information stored in neural network by training.The present invention solves existing
Artificial neural network depends on computer, needs to consume a large amount of the problem of calculating power, the memristor neural network with forecast function
Circuit is of great practical significance.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is circuit diagram of the invention.
Fig. 2 is the circuit diagram of memristor neural network module in Fig. 1.
Fig. 3 is the circuit diagram of iterator in Fig. 1.
Fig. 4 is the circuit diagram of signal input module in Fig. 1.
Fig. 5 is the circuit diagram of signal output module in Fig. 1.
Fig. 6 is simulation result diagram of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under that premise of not paying creative labor
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of prediction circuit based on memristor neural network, which is characterized in that including memristor neural network
The input terminal of module, iterator, signal input module and signal output module, signal input module is connected with input signal
It connects, the output terminal of signal input module is connected with the first input end B of iterator, the second input terminal A of iterator
It is connected with the output terminal of memristor neural network module, the output terminal of iterator is defeated with memristor neural network module respectively
Enter end to be connected with the input terminal of signal output module, the output signal of the output terminal output circuit of signal output module.
The signal input module is equipped with the first clock signal, and iterator is equipped with second clock signal and third clock
Signal.When there is signal to be input to signal input module, the first clock signal is in high level state, so that signal input module
Output information can be normally sent to iterator, to complete the initial work of iterator.After iterator is initialised,
First clock signal becomes low level, thus make the asynchronous zero setting of iterator, set one end to be high level, in order to avoid influence iterator
In each trigger normal work.The pulsewidth of second clock signal and third clock signal is a quarter clock cycle,
And third clock signal lags the second clock signal a quarter clock cycle.Second clock signal and third clock signal
Output pulse is alternately present, and completes iterative operation to control iterator.
The memristor neural network module includes one group of input terminal and one group of output terminal, and iterator includes one group of output
Terminal, one group of first input end B and one group of second input terminal A, the one group of first input end B and signal of the iterator
One group of output terminal of input module connects one to one, and signal input module is converted into input signal to meet memristor nerve net
The signal of network module requirement is simultaneously sent to iterator, and the first input end B of iterator receives the letter from signal input module
Number to initialize iterator；One group of output terminal of the memristor neural network module and one group of second input terminal of iterator
A connects one to one, and one group of input terminal of memristor neural network module and one group of output terminal of iterator correspond and connect
It connects, memristor neural network module receives information to be processed and exports processed information.One group of output terminal of iterator with
One group of input terminal of signal output module connects one to one, and the second input terminal A that iterator connects is received from memristor
The information of neural network module, and by the output terminal of iterator information is transmitted to the input terminal of memristor neural network module
Son completes iterative operation；Signal output module receives the signal from iterator and the output signal after conversion.It can prolong
Reach 2 or multiple.Below to there is 8 signals to be transmitted as between memristor neural network module, iterator and signal output module
Example introduces the circuit structure of each module.
As shown in Fig. 2, the memristor neural network module includes that the memristor array of a 8*8 and eight voltage summations are compared
Unit, memristor array are arranged in the matrix of 8*8 by 64 memristors, and every row has 8 memristors, and each column also has 8 memristors.Memristor array
The p of middle 8 memristors of each column is extremely connected with output terminal corresponding in iterator, the pole m of 8 memristors of every row in memristor array
It is connected with corresponding voltage summation comparing unit, the output of voltage summation comparing unit is 8 output terminals.That is memristor battle array
One group of pin I of columnM1~IM8Respectively with the output terminal O of iteratorT1~OT8Be connected, each column memristor of memristor array with one
Input pin is connected.The pin O ' of every row memristor of the i.e. memristor matrix of another group of memristor arrayM1~O 'M8Respectively with eight groups
The input pin I ' of voltage summation comparing unitM1~I 'M8It is connected.The output end O of eight voltage summation comparing unitsM1~OM8Point
Not with the second input terminal I of iteratorT1~IT8It is connected.
The voltage summation comparing unit includes the first operational amplifier, second operational amplifier and third operation amplifier
Device, the inverting input terminal of the first operational amplifier are connected with the pole m of memristor, and the inverting input terminal of the first operational amplifier passes through
First resistor is connected with the output end of the first operational amplifier, and the output end of the first operational amplifier is connected with second resistance
It connects, second resistance is connected with the reverse input end of second operational amplifier, and the reverse input end of second operational amplifier passes through
3rd resistor is connected with the output end of second operational amplifier, and the first operational amplifier is same mutually defeated with second operational amplifier
Enter end to be grounded；The output end of the second operational amplifier is connected with the non-inverting input terminal of third operational amplifier, third
The inverting input terminal of operational amplifier is connected with voltage source, and the output end of third operational amplifier is memristor neural network module
An output terminal.
Specifically, for voltage summation comparing unit VSU1, first resistor RM1It is connected to the first operational amplifier OPM1It is anti-
Between phase input terminal and output end, the first operational amplifier OPM1Inverting input terminal as voltage sum comparing unit VSU1's
Input terminal I 'M1, and an output pin O ' with memristor arrayM1It is connected.First operational amplifier OPM1Non-inverting input terminal
Ground connection.Second resistance RM2It is connected to second operational amplifier OPM1Output end and second operational amplifier OPM2Anti-phase input
Between end, 3rd resistor RM3It is connected to second operational amplifier OPM2Inverting input terminal and output end between, the second operation is put
Big device OPM2Non-inverting input terminal ground connection.Third operational amplifier OPM3Non-inverting input terminal and second operational amplifier OPM2It is defeated
Outlet is connected, third operational amplifier OPM3Inverting input terminal and voltage source VM1It is connected, voltage source VM1Other end ground connection, the
Three operational amplifier OPM3Output end as voltage sum comparing unit VSU1Output terminal OM1, output terminal OM1With iteration
One input terminal I of deviceT1It is connected.Remaining 7 groups of voltage summation comparing unit structure is similar, and its input pin I 'M2~I 'M8
Respectively with the output pin O ' of memristor arrayM2~O 'M8It is connected, output end OM2~OM8Respectively with the input terminal I of iteratorT2
~IT8It is connected.
As shown in figure 3, iterator includes 8 iteration units being connected in parallel, iteration unit includes the first d type flip flop and the
2-D trigger, the input terminal of the first d type flip flop are connected with an output terminal of memristor neural network module, the first D triggering
The control terminal of device is connected with second clock signal, the output end of the first d type flip flop and the first initialization input respectively with
Or the input terminal of door is connected or the output end of door is connected with the input terminal of the second d type flip flop, the control of the second d type flip flop
End is connected with third clock signal, and the output end of the second d type flip flop is connected with the input terminal of the first buffered gate, the first buffering
The output end of door is the output terminal of iterator；The asynchronous of first d type flip flop and the second d type flip flop sets 0 end R ' with
Two initialization input are connected, and the asynchronous 1 end S ' of first d type flip flop and the second d type flip flop is initialized with third
Input terminal is connected, the first initialization input, the second initialization input and third initialization input difference
It is connected with the output terminal of signal input module.
Specifically, iteration unit ITU1Including the first d type flip flop FT1, the second d type flip flop FT2Or door DT1With the first buffering
Door DT2.First d type flip flop FT1Input terminal as iteration unit ITU1Input terminal IT1And with voltage sum comparing unit
VSU1Output terminal OM1It is connected, the first d type flip flop FT1Control terminal connect second clock signal CLKT1, the first d type flip flop FT1
Output end with or door DT1An input terminal be connected or door DT1Another input terminal as iteration unit ITU1First at the beginning of
Beginningization input terminal PT1, and it is connected to an output terminal O of signal input moduleI1.Second d type flip flop FT2Input terminal connect
It connects or door DT1Output end, the second d type flip flop FT2Control terminal connect third clock signal clkT2, the second d type flip flop FT2It is defeated
Outlet connects buffered gate DT2, buffered gate DT2Output as iteration unit ITU1Output terminal OT1, output terminal OT1With memristor
One input terminal I of neural network moduleM1It is connected.First d type flip flop FT1With the second d type flip flop FT2It is asynchronous set 0 end R ' altogether
With being connected, as iteration unit ITU1The sub- P of the second initialization inputT2, the sub- P of the second initialization inputT2It is inputted with signal
One output terminal O of moduleI2It is connected, the first d type flip flop FT1With the second d type flip flop FT2It is asynchronous set 1 end S ' jointly be connected,
As iteration unit ITU1The sub- P of third initialization inputT3, and an output terminal O with signal input moduleI3It is connected.
The composed structure and iteration unit ITU of remaining 7 groups of iteration unit1It is similar, and its input terminal IT2~IT8Respectively with the voltage
The output O of summation comparison moduleM2~OM8Be connected, output respectively with the input terminal I of memristor arrayM2~IM8It is connected, initialization
Input terminal PT4~PT24Respectively with the output O of the signal input moduleI4~OI24It is connected.
As shown in figure 4, the signal input module includes four groups of signal input units being connected in parallel, signal input unit
Be connected with an input signal, signal input unit include the first votage control switch, the second votage control switch, third votage control switch,
4th votage control switch and absolute value of voltage module, the first votage control switch, the second votage control switch, third votage control switch and the 4th are voltage-controlled
The Reverse Turning Control voltage input end of switch is grounded, positive control voltage input end is connected with the first clock signal；Input
Signal respectively with the input terminal of absolute value of voltage module, the input terminal of the first NOT gate, the first contact of the second votage control switch and defeated
Terminal I is connected out, and the output end of the first NOT gate is connected with the first contact of the first votage control switch, and the of the first votage control switch
Two contacts are connected with the input terminal of resistance I and the second NOT gate respectively, and the output end of the second NOT gate is connected with output terminal II,
Resistance I ground connection；Second contact of second votage control switch is connected with the input terminal of resistance II and third NOT gate respectively, third
The output end of NOT gate is connected with output terminal III, resistance II ground connection；The output end of the absolute value of voltage module and the 4th non-
The input terminal of door is connected, the first touching with the input terminal of the 5th NOT gate, the 4th votage control switch respectively of the output end of the 4th NOT gate
Point is connected with output terminal VI, and the output end of the 5th NOT gate is connected with the first contact of third votage control switch, and third is voltage-controlled
Second contact of switch is connected with the input terminal of the 6th NOT gate and resistance III, the output end and output terminal IV of the 6th NOT gate
It is connected, resistance III ground connection；Second contact of the 4th votage control switch is connected with the input terminal of the 7th NOT gate and resistance IV respectively
It connects, the output end of the 7th NOT gate is connected with output terminal V, resistance IV ground connection；The input terminal I-VI is adjacent with 2 respectively
Iteration unit the first initialization input, the second initialization input be connected with third initialization input.
Specifically, signal input unit SIU1Including 4 the first votage control switch SI1, the second votage control switch SI2, third it is voltage-controlled
Switch SI3With the 4th votage control switch SI4, 7 the first NOT gate DI2, the second NOT gate DI4, third NOT gate DI5, the 4th NOT gate DI1, the 5th
NOT gate DI3, the 6th NOT gate DI6With the 7th NOT gate DI7, 4 resistance IRI1, resistance IIRI2, resistance IIIRI3With resistance IVRI4With one
Absolute value of voltage modules A BSI1.Absolute value of voltage modules A BSI1Input terminal be both used as signal input unit SIU1One input
Terminal II1External input signal is received, and as an output terminal IOI1With the first initialization input P of iteratorT1Phase
Even.In addition absolute value of voltage modules A BSI1Input terminal again with the first NOT gate DI2Input terminal be connected, the first NOT gate DI2Output
With the first votage control switch SI1A contact be connected, the second votage control switch SI2A contact and absolute value of voltage modules A BSI1
Input terminal be connected, directly reception input signal, absolute value of voltage modules A BSI1Output end pass through the 4th NOT gate DI1, the 5th
NOT gate DI3It is connected to third votage control switch SI3A contact, the 4th votage control switch SI4A contact and the 4th NOT gate DI1's
Output end and the 5th NOT gate DI3Input terminal connect jointly.First votage control switch SI1, the second votage control switch SI2, third is voltage-controlled opens
Close SI3With the 4th votage control switch SI4Another contact pass through resistance IR respectivelyI1, resistance IIRI2, resistance IIIRI3And resistance
IVRI4Ground connection, and it is connected to the second NOT gate DI4, third NOT gate DI5, the 6th NOT gate DI6, the 7th NOT gate DI7Input terminal.The
One votage control switch SI1, the second votage control switch SI2, third votage control switch SI3With the 4th votage control switch SI4Reverse Turning Control voltage input
The common ground connection in end, positive control voltage input end connect the first clock of signal source of clock CLKI.Second NOT gate DI4, third NOT gate
DI5, the 6th NOT gate DI6, the 7th NOT gate DI7Output end respectively as signal input unit SIU1Output terminal IIOI2, output
Terminal II IOI3, output terminal VIOI4With output terminal VOI5.4th NOT gate DI1Output directly as signal input unit SIU1
The sub- VIO of another outputI6.Signal input unit SIU1Output terminal OI1~OI6It is connected to the initial of iterator
Change input terminal PT1~PT6.Remaining 3 groups of signal input unit structure is similar, the input I of signal input unitI2~II4It connects respectively
External input signal is received, O is exportedI7~OI24Respectively with the sub- P of the initialization input of iteratorT7~PT24It is connected.
As shown in figure 5, the signal output module includes four groups of signal output units being connected in parallel, each signal output
There are two input terminal and an output ends respectively for unit；Signal output unit includes NOT gate and door, buffered gate and resistance；Signal
The first input end of output unit respectively with the 11st NOT gate, the 13rd NOT gate, second with door and the 4th with the input terminal phase of door
Connection, the second input terminal of signal output unit respectively with first and the input terminal of door, the input terminal of the 12nd NOT gate, the 14th
The input terminal of NOT gate and the 4th is connected with another input terminal of door, and the output end of the 11st NOT gate is another defeated with door with first
Enter end to be connected, the output end of the 12nd NOT gate is connected with second with another input terminal of door, the 13rd NOT gate and the 14th
The output end of NOT gate is connected with third with the input terminal of door respectively；First passes through the second buffered gate and first with the output end of door
Output resistance is connected, and second is connected by third buffered gate with the second output resistance with the output end of door, third and door
Output end is connected by the 4th buffered gate with third output resistance, and the 4th passes through the 5th buffered gate and the 4th with the output end of door
Output resistance is connected, after the first output resistance, the second output resistance, third output resistance and the 4th output resistance are connected in parallel
As output end.
Specifically, signal output unit SOU1Including four NOT gates --- the 11st NOT gate DO1, the 12nd NOT gate DO2, the tenth
Three NOT gate DO3With the 14th NOT gate DO4, four and door --- first and door DO5, second with door DO6, third and door DO7, the 4th and door
DO8, four buffered gates --- the second buffered gate DO9, third buffered gate DO10, the 4th buffered gate DO11, the 5th buffered gate DO12With four
Output resistance --- the first output resistance RO1, the second output resistance RO2, third output resistance RO3, the 4th output resistance RO4.Tenth
One NOT gate DO1, the 13rd NOT gate DO3Input terminal and second with door DO6, the 4th with door DO8An input terminal connect and make jointly
For signal output unit SOU1An input terminal -- first input end IO1.First input end IO1With an output of iterator
Terminal OT1It is connected.NOT gate DO2、DO4Input terminal and with door DO5An input terminal and DO8Another input terminal connect jointly
And as signal output unit SOU1An input terminal IO2。IO2With an output terminal O of the iteratorT2It is connected.The
11 NOT gate DO1, the 12nd NOT gate DO2Output end be separately connected first and door DO5, second with door DO6Another input
End, the 13rd NOT gate DO3, the 14th NOT gate DO4Output end be separately connected third and door DO7Two input terminals, first and door
DO5, second with door DO6, third and door DO7, the 4th with door DO8Output end pass through the second buffered gate D respectivelyO9, third buffered gate
DO10, the 4th buffered gate DO11, the 5th buffered gate DO12With the first output resistance RO1, the second output resistance RO2, third output resistance
RO3, the 4th output resistance RO4Connection, the first output resistance RO1, the second output resistance RO2, third output resistance RO3, the 4th output
Resistance RO4It is 1 ohm.First output resistance RO1, the second output resistance RO2, third output resistance RO3, the 4th output resistance RO4
The other end connect jointly, and as signal output unit SOU1Output terminal OO1.Second buffered gate DO9Output level it is permanent
For 0v, third buffered gate DO10Output level be respectively 0v and 4v, the 4th buffered gate DO11Output level be respectively 0v and-
4v, the D of the 5th buffered gateO12Output level be respectively 0v and -8v.Remaining 3 groups of signal output unit structure is similar, and signal is defeated
The input I of unit outO3~IO8Respectively with the output terminal O of iteratorT3~OT8It is connected, output terminal OO2~OO4Respectively as
The output of signal output module.
Four modules of the invention --- memristor neural network module, iterator module, signal input module and signal output
Module according to the complete memristor neural network that is formed by connecting shown in Fig. 1 prediction circuit.The input terminal of signal input module
[II1,II2,II3,II4] input terminal [I as complete circuit1,I2,I3,I4], the output terminal [O of signal output moduleO1,
OO2,OO3,OO4] output terminal [O as complete circuit1,O2,O3,O4].When the one incomplete information of input into circuit
When, circuit can export a prediction result, institute by processing according to the information stored in memristor neural network by training
The prediction result of output indicates the intellectual determination to made by input information.
Specifically, circuit structure of the invention can be completed to judge the trivial games of scientist.There are four scientists -- and it is rich
Blue crin, figure spirit, Shannon and Ka Haer, there are four types of attributes by each scientist: 1 whether researching neural network, whether 2 be Britain
People, whether 3 be born in for 20th century, and whether 4 be a concrete number scholar.For every attribute, if answer is "Yes", attribute value is
" 1 ", if answer is "No", attribute value is " 0 ", if answer is " not knowing ", attribute value is " -1 ".Then Franklin
It is represented by [0,1,1,0], figure spirit is represented by [1,1,1,1], and Shannon is represented by [0,0,1,1], and Ka Haer is represented by
[1,0,0,0]。
Existing one group of Incomplete information: not knowing whether researching neural network, is Englishman, it is not known that whether be born in 20
Century is not mathematician.It can be expressed as vector [- 1,1, -1,0]T.The signal for being input to circuit using this vector as signal is defeated
Enter terminal [I1,I2,I3,I4] in.Signal input unit SIU in signal input module1Input correspond to -1, -1 by signal
Input unit SIU1It is converted into [- 1,0,1,0,1,0], the signal input unit SIU in signal input module2Input it is corresponding
It is 1,1 by signal input unit SIU2It is converted into [1,1,0,0,1,0], signal input unit SIU in signal input module3
Input correspond to -1, -1 pass through signal input unit SIU3It is converted into [- 1,0,1,0,1,0], believes in signal input module
Number input unit SIU4Input correspond to 0,0 pass through signal input unit SIU4It is converted into [0,0,1,1,0,1].By connecing
The signal from each signal input unit is received, the state of iterator is initialized to OT=[0,0,1,0,0,0,0,1]T, one second
Completion, clock signal clk are initialized after clockIBecome low level, makes trigger is asynchronous to set 1 end and asynchronous 0 end of setting keeps high electricity
It is flat, it is persistently influenced by initializing signal with guaranteeing iterator no longer, and then complete iterative operation.Period, if DT1、DT3、
DT5、DT7、DT9、DT11、DT13、DT15In the signal value that receives of certain several or door be 1, then the iteration unit where it is transported in iteration
Output valve perseverance in calculation is 1.
After iterator receives initializing signal, clock signal clkT1Keep 1/4 iteration cycle (iteration cycle 4
Second).CLKT1After becoming low level 1s clock, clock signal clkT2There is high level and keeps 1/4 iteration cycle.When hereafter
Clock signal cycle occurs repeatedly.Two column triggers of the left and right sides alternately trigger under the action of clock signal, change and latch shape
State is sent the signal received from signal input module to memristor neural network module and is handled repeatedly, finally enters signal
Reach convergence in the treatment process of iterator and memristor neural network, no longer change state.
The memristor of memristor neural network module its resistance value after training is arranged to (unit is ohm):
Correspondingly, matrix W ' weight be set as
Summation comparison operation of the output of memristor array through overvoltage summation comparing unit.The ratio of voltage summation comparing unit
Compared with value by adjusting each voltage source VMValue can be set as T=VM=[1.5,2.5,2.5,1.5,0.5,2.5,2.5,1.5]T.Memristor
The output valve of array is greater than or equal to fiducial value and then exports 1, then exports 0 less than fiducial value.The result of voltage summation comparing unit
It send to iterator, then memristor array is back to by iterator and is iterated.In the effect of memristor neural network module and iterator
Lower signal is iterated.The input of memristor array, the i.e. output of iterator are as follows:
OT=f (W (f (W (f (W (f (W*OT- T))-T))-T))-T) ...,
Wherein,
The output O of iteratorTIn the case where iterating, [0,1,1,0,1,0,0,1] is finally converged on.Signal output module handle
8 signals received from the output of iterator are re-converted into 4, i.e., [0,1,1,0].
It follows that working as the input information of circuit are as follows: do not know whether researching neural network, be Englishman, it is not known that be
It is no to be born in for 20th century, it is not mathematician, is expressed as vector [- 1,1, -1,0]TWhen.Circuit is input to using this vector as signal
Signal input terminal [I1,I2,I3,I4] after, [0,1,1,0] is finally converged on after the iterative processing of oversampling circuit, and as most
Output eventually.The final output of circuit predicts that inputted information is Franklin.The simulation result of circuit of the invention such as Fig. 6 institute
To show, input signal is [- 1,1, -1,0], is become [- 1,1,1,0] after first time iteration, become after second of iteration [0,1,1,
0], [0,1,1,0] is finally converged on after third and fourth iteration.
The prediction circuit of memristor neural network proposed by the present invention, when inputting an incomplete information in circuit, electricity
Road can export a prediction result, be exported according to the information stored in memristor neural network by training by processing
Prediction result indicates the intellectual determination to made by input information.Memristor neural network module of the invention has bionical spy
Property, it is expected to solve pattern-recognition, the challenge occurred in artificial intelligence.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of prediction circuit based on memristor neural network, which is characterized in that including memristor neural network module, iterator,
The input terminal of signal input module and signal output module, signal input module is connected with input signal, and signal inputs mould
The output terminal of block is connected with the first input end of iterator, the second input terminal and memristor neural network mould of iterator
The output terminal of block is connected, and the output terminal of iterator exports mould with the input terminal of memristor neural network module and signal respectively
The input terminal of block is connected, the output signal of the output terminal output circuit of signal output module.
2. the prediction circuit according to claim 1 based on memristor neural network, which is characterized in that the signal inputs mould
Block is equipped with the first clock signal, and iterator is equipped with second clock signal and third clock signal.
3. the prediction circuit according to claim 1 or 2 based on memristor neural network, which is characterized in that the memristor mind
It include one group of input terminal and one group of output terminal through network module, iterator includes one group of output terminal, one group of first input
Terminal and one group of second input terminal, one group of first input end of the iterator and one group of output end of signal input module
Son connects one to one, and signal input module is converted into input signal to meet the signal and biography of memristor neural network module requirement
It send to iterator, the first input end of iterator receives the signal from signal input module to initialize iterator；It is described
One group of output terminal of memristor neural network module and one group of second input terminal of iterator connect one to one, memristor nerve
One group of input terminal of network module and one group of output terminal of iterator connect one to one, one group of output terminal of iterator
It connects one to one with one group of input terminal of signal output module, iterator receives the letter from memristor neural network module
It ceases, and information is transmitted to by the output terminal of iterator the input terminal of memristor neural network module, complete iterative operation；
Signal output module receives the signal from iterator and the output signal after conversion.
4. the prediction circuit according to claim 3 based on memristor neural network, which is characterized in that the memristor nerve net
Network module includes the memristor array and eight voltage summation comparing units of a 8*8, the pole p of 8 memristors of each column in memristor array
It is connected with output terminal corresponding in iterator, the m of every 8 memristors of row extremely sums with corresponding voltage in memristor array
Comparing unit is connected, and the output of voltage summation comparing unit is 8 output terminals.
5. the prediction circuit according to claim 4 based on memristor neural network, which is characterized in that the voltage summation ratio
It include the first operational amplifier, second operational amplifier and third operational amplifier, the reverse phase of the first operational amplifier compared with unit
Input terminal is connected with the pole m of memristor, and the inverting input terminal of the first operational amplifier passes through first resistor and the first operation amplifier
The output end of device is connected, and the output end of the first operational amplifier is connected with second resistance, and second resistance is put with the second operation
The reverse input end of big device is connected, and the reverse input end of second operational amplifier passes through 3rd resistor and second operational amplifier
Output end be connected, the non-inverting input terminal of the first operational amplifier and second operational amplifier is grounded；Second operation
The output end of amplifier is connected with the non-inverting input terminal of third operational amplifier, the inverting input terminal of third operational amplifier with
Voltage source is connected, and the output end of third operational amplifier is an output terminal of memristor neural network module.
6. the prediction circuit according to claim 3 based on memristor neural network, which is characterized in that the iterator includes
8 iteration units being connected in parallel, iteration unit include the first d type flip flop and the second d type flip flop, the input of the first d type flip flop
End is connected with an output terminal of memristor neural network module, control terminal and the second clock signal phase of the first d type flip flop
Connection, the output end of the first d type flip flop and the first initialization input respectively with or door input terminal be connected or door it is defeated
Outlet is connected with the input terminal of the second d type flip flop, and the control terminal of the second d type flip flop is connected with third clock signal, the 2nd D
The output end of trigger is connected with the input terminal of the first buffered gate, and the output end of the first buffered gate is the output end of iterator
Son；The asynchronous 0 end R' that sets of first d type flip flop and the second d type flip flop is connected with the second initialization input, described
The asynchronous 1 end S' of first d type flip flop and the second d type flip flop is connected with third initialization input, and the first initialization is defeated
Enter terminal, the second initialization input and third initialization input to be connected with the output terminal of signal input module respectively
It connects.
7. the prediction circuit based on memristor neural network according to claim 3 or 6, which is characterized in that the signal is defeated
Entering module includes four groups of signal input units being connected in parallel, and signal input unit is connected with an input signal, and signal is defeated
Entering unit includes the first votage control switch, the second votage control switch, third votage control switch, the 4th votage control switch and absolute value of voltage mould
Block, the first votage control switch, the second votage control switch, the Reverse Turning Control voltage input end of third votage control switch and the 4th votage control switch are equal
Ground connection, positive control voltage input end are connected with the first clock signal；Input signal respectively with absolute value of voltage module
Input terminal, the input terminal of the first NOT gate, the second votage control switch the first contact be connected with output terminal I, the first NOT gate it is defeated
Outlet is connected with the first contact of the first votage control switch, and the second contact of the first votage control switch is non-with resistance I and second respectively
The input terminal of door is connected, and the output end of the second NOT gate is connected with output terminal II, resistance I ground connection；Described second voltage-controlled opens
The second contact closed is connected with the input terminal of resistance II and third NOT gate respectively, the output end and output terminal of third NOT gate
III is connected, resistance II ground connection；The output end of the absolute value of voltage module is connected with the input terminal of the 4th NOT gate, and the 4th
The output end of NOT gate is connected with the input terminal of the 5th NOT gate, the first contact of the 4th votage control switch and output terminal VI respectively,
The output end of 5th NOT gate is connected with the first contact of third votage control switch, the second contact of third votage control switch and the 6th non-
The input terminal of door is connected with resistance III, and the output end of the 6th NOT gate is connected with output terminal IV, resistance III ground connection；4th
Second contact of votage control switch is connected with the input terminal of the 7th NOT gate and resistance IV respectively, the output end of the 7th NOT gate and output
Terminal V is connected, resistance IV ground connection；First initialization input of the output terminal I-VI iteration unit adjacent with 2 respectively
Son, the second initialization input are connected with third initialization input.
8. the prediction circuit according to claim 3 based on memristor neural network, which is characterized in that the signal exports mould
Block includes four groups of signal output units being connected in parallel, and there are two input terminals and an output respectively for each signal output unit
End；Signal output unit includes NOT gate and door, buffered gate and resistance；The first input end of signal output unit is respectively with the tenth
One NOT gate, the 13rd NOT gate, second are connected with door and the 4th with the input terminal of door, the second input terminal point of signal output unit
It is another not defeated with the input terminal of door, the input terminal of the 12nd NOT gate, the input terminal of the 14th NOT gate and the 4th and door with first
Enter end to be connected, the output end of the 11st NOT gate is connected with first with another input terminal of door, the output end of the 12nd NOT gate
It is connected with second with another input terminal of door, the output end of the 13rd NOT gate and the 14th NOT gate is defeated with third and door respectively
Enter end to be connected；First is connected by the second buffered gate with the first output resistance with the output end of door, second with the output of door
End is connected by third buffered gate with the second output resistance, and the output end of third and door is exported by the 4th buffered gate and third
Resistance is connected, and the 4th is connected by the 5th buffered gate with the 4th output resistance with the output end of door, the first output resistance,
Two output resistances, third output resistance and the 4th output resistance are used as output end after being connected in parallel.
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