CN112734022A - Four-character memristor neural network circuit with recognition and sorting functions - Google Patents
Four-character memristor neural network circuit with recognition and sorting functions Download PDFInfo
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Abstract
The invention provides a four-character memristor neural network circuit with recognition and sorting functions, which is used for solving the technical problem that the existing artificial neural network consumes a large amount of computing power. The four-character memristor neural network circuit comprises a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is respectively connected with a character input signal and a clock signal, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit. The Hopfield neural network is constructed by memristors, so that the weight can be repeatedly trained; the weight value can be represented by a synaptic circuit composed of a memory resistor and an operational amplifier so as to obtain a positive synaptic weight value and a negative synaptic weight value; the invention can simultaneously identify and sort the four characters interfered by the noise, and converge the final result into a word form.
Description
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to a four-character memristive neural network circuit with recognition and sequencing functions.
Background
The artificial neural network is a research hotspot in the field of artificial intelligence, and shows good intelligent characteristics in the aspects of biological recognition, prediction estimation, mode recognition, robot control and the like. Constructing a human brain-like mechanism on a traditional digital computer based on von neumann architecture is a difficult task. Digital computers typically process information in a sequential order, while the brain processes information in parallel. Compared with a digital computer, the biological brain is more flexible and easier to learn new things. To effectively implement the functions of a biological brain, a new computing architecture is required.
In 1971, professor Chua creatively proposed a basic element defining the relationship between charge and magnetic flux and named memristor. In 2008, memristors were invented by professor Strukov and his colleagues in hewlett packard laboratories. The memory action of memristors is analogous to the function of synapses in biological nervous systems. Memristors are better suited for electronic synapses due to their nanometer size, non-volatility, and integration with CMOS. Subsequently, many studies have shown that memristors can act as electronic synapses, and the weights of the synapses can be represented by the conductance of the memristors. The combination of the memory resistor and the neural network can greatly simplify the circuit structure and optimize the information processing capability. Thus, memristors provide a new technique for the design of synaptic hardware circuits.
The traditional number recognition method cannot well recognize under the condition of interference, and the associative memory function of the Hopfield neural network has great advantages in this respect. The Hopfield neural network and the learning algorithm were originally proposed by the American physicist Hopfield in 1982, and a new research approach was developed for the development of the artificial neural network. In addition, different structural features and learning methods of the hierarchical neural network are utilized to simulate the memory mechanism of the biological neural network, and a satisfactory result is obtained. By constructing a complementary metal oxide semiconductor circuit as a synapse, a Hopfield neural network with large chip area and high power consumption is realized. The artificial neural network based on the memristor provides a foundation for the development of the image recognition technology, and an associative memory neural network circuit based on the memristor is also proposed. Memristance-based neural networks have been greatly developed by virtue of their unique advantages.
Disclosure of Invention
Aiming at the technical problem that the existing artificial neural network depends on a von Neumann structure and needs to consume a large amount of computing power, therefore, based on the fact that the artificial neural network needs a new computing architecture, the invention provides a four-character memristive neural network circuit with the functions of identification and sequencing, which can identify four letters simultaneously and converge the final result into a word WHAT form.
The technical scheme of the invention is realized as follows:
a four-character memristor neural network circuit with recognition and sorting functions comprises a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is respectively connected with a character input signal and a clock signal, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is respectively connected with a character input signal and a clock signal, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier, and the output end of the feedback amplifier is connected with the input end of the iteration submodule.
The calculation submodule comprises a calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4(ii) a Calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4Are all connected with the output end of the iteration submodule, and a calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4The output ends of the signal processing modules are connected with the input end of the signal processing module; calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4Each comprising a first memristor array, a first amplifier, and a first inverter; first memristor arrayThe input end of the first memristor array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of the first amplifier, the output end of the first amplifier is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier.
The first memristor array comprises 625 memristors, the size of the first memristor array being 25 × 25; 25 first amplifiers are arranged, and 25 first inverters are arranged; each row of memristors of the first memristor array is connected with a first amplifier, the first amplifiers are connected with the first inverters in a one-to-one correspondence mode, and the inverting input end of each first amplifier is connected with the output end of the corresponding first amplifier through a resistor.
The memristor comprises a combination switch and a memristor M, the combination switch comprises a first buffer, a phase inverter INV ' and a switch K, the common end of the input end of the first buffer and the input end of the phase inverter INV ' is the input end of the memristor, the output end of the first buffer or the output end of the phase inverter INV ' is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor.
The iteration submodule comprises 100 iterator units, and each iterator unit comprises a first D trigger, a second D trigger and a second buffer; the input ends I of the first D trigger and the second D trigger are connected with a character input signal, the clock terminals of the first D trigger and the second D trigger are connected with a clock signal, the input end II of the first D trigger is connected with the output end of the feedback amplifier, the output end of the first D trigger is connected with the input end II of the second D trigger, the output end of the second D trigger is connected with the inverting input end of the second buffer, the non-inverting input end of the second buffer is grounded, and the output end of the second buffer is connected with the first memristor array.
The clock signals include a first clock signal and a second clock signal, the first clock signal is connected with a clock terminal of the first D flip-flop, and the second clock signal is connected with a clock terminal of the second D flip-flop.
The first D flip-flop comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a second inverter; the input end of the first NAND gate is respectively connected with the output end of the feedback amplifier and the first clock signal, and the output end of the first NAND gate is connected with the input end of the third NAND gate; the input end of the second NAND gate is respectively connected with the first clock signal and the output end of the second inverter, the input end of the second inverter is connected with the output end of the feedback amplifier, and the output end of the second NAND gate is connected with the input end of the fourth NAND gate; an S terminal is arranged on the third NAND gate, the S terminal of the third NAND gate is connected with a character input signal, and the output end of the third NAND gate is respectively connected with the input end of the fourth NAND gate and the input end of the second D trigger; the fourth NAND gate is provided with an R terminal, the R terminal of the fourth NAND gate is connected with a character input signal, and the output end of the fourth NAND gate is connected with the input end of the third NAND gate;
the second D flip-flops respectively comprise a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate and a third inverter; the input end of the fifth NAND gate is respectively connected with the output end of the third NAND gate and the second clock signal, and the output end of the fifth NAND gate is connected with the input end of the seventh NAND gate; the output end of the sixth NAND gate is respectively connected with the second clock signal and the output end of the third inverter, the input end of the third inverter is connected with the output end of the third NAND gate, and the output end of the sixth NAND gate is connected with the input end of the eighth NAND gate; an S terminal is arranged on the seventh NAND gate, the S terminal of the seventh NAND gate is connected with the character input signal, and the output end of the seventh NAND gate is respectively connected with the input end of the eighth NAND gate and the input end of the second buffer; and the eighth NAND gate is provided with an R terminal, the R terminal of the eighth NAND gate is connected with a character input signal, and the output end of the eighth NAND gate is connected with the input end of the seventh NAND gate.
The signal processing module comprises an adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4(ii) a Adder unit AD1And an input terminal ofCalculation unit CAL1Are connected to the output of the adder unit AD2Is connected to the calculation unit CAL2Are connected to the output of the adder unit AD3Is connected to the calculation unit CAL3Are connected to the output of the adder unit AD4Is connected to the calculation unit CAL4Are connected to the output of the adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4The output ends of the convergence modules are connected with the input end of the convergence module; adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4All comprise a memristor M1，M2，...，M38The first amplifier, the second amplifier, the third amplifier, the first comparator and the second comparator; memory resistance M1，M2，...，M17The input ends of the first inverter and the second inverter are respectively connected with the 1 st first inverter to the 17 th first inverter of each calculation unit in a one-to-one correspondence mode, and the memristor M1，M2，...，M17The output ends of the first and second amplifiers are connected with the inverting input end of the second amplifier, and the inverting input end of the second amplifier is connected with the inverting input end of the second amplifier through a memristor M37The output end of the second amplifier is connected with the inverting input end of the first comparator, the positive phase input end of the first comparator is connected with the voltage input signal, and the output end of the first comparator is connected with the input end of the convergence module; memory resistance M18，M19，...，M36The input ends of the memristors are respectively connected with the output ends of the 7 th to the 25 th first inverters of each computing unit in a one-to-one correspondence manner, and the memristor M18，M19，...，M36The output ends of the first and second amplifiers are connected with the inverting input end of a third amplifier, and the inverting input end of the third amplifier is connected with the inverting input end of the third amplifier through a memristor M38The output end of the third amplifier is connected with the inverting input end of the second comparator, the non-inverting input end of the second comparator is connected with the voltage input signal, and the output end of the second comparator is connected with the input end of the convergence module.
The convergence module comprises a second memristor array, a fourth amplifier, and a fourth inverter; the input end of the second memristor array is connected with the output end of the first comparator respectively, the output end of the second memristor array is connected with the input end of the fourth amplifier, the output end of the fourth amplifier is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs an output signal of the four-character memristor neural network circuit.
The second memristor array comprises 64 memristors, the size of the second memristor array being 8 × 8; the number of the fourth amplifiers is 8, and the number of the fourth inverters is 8; each column of memristors of the second memristor array is connected with a fourth amplifier, and the inverting input end of the fourth amplifier is connected with the fourth amplifier through a memristor R2The output end of the fourth amplifier is correspondingly connected with the input end of the fourth inverter.
Compared with the prior art, the invention has the following beneficial effects:
1) the Hopfield neural network is constructed by memristors, so that the weight can be repeatedly trained; the weight value can be represented by a synaptic circuit composed of a memory resistor and an operational amplifier so as to obtain a positive synaptic weight value and a negative synaptic weight value;
2) the neural network circuit based on the memristor can simultaneously recognize and sequence four characters interfered by noise, and the function has very important significance for the development of artificial intelligence.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a neuron according to the present invention.
FIG. 2 is a circuit diagram of the compute submodule of the present invention.
Fig. 3 is a circuit diagram of an iteration sub-module of the present invention.
FIG. 4 is a circuit diagram of the character recognition module of the present invention.
Fig. 5 is a circuit diagram of a signal processing module according to the present invention.
FIG. 6 is a circuit diagram of a convergence module according to the present invention.
FIG. 7 is a complete circuit diagram of the present invention
FIG. 8 is a simulation of the two types of clock inputs of the present invention.
Fig. 9 is a schematic illustration of the present invention.
FIG. 10 is a diagram of simulation results of the character recognition module of the present invention.
FIG. 11 is a final simulation result diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 7, an embodiment of the present invention provides a four-character memristive neural network circuit with functions of identification and sorting, including a character identification module, a signal processing module, and a convergence module, where an input end of the character identification module is connected to a character input signal and a clock signal, an output end of the character identification module is connected to an input end of the signal processing module, an output end of the signal processing module is connected to an input end of the convergence module, and an output end of the convergence module outputs an output signal of the four-character memristive neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is respectively connected with a character input signal and a clock signal, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier, and the output end of the feedback amplifier is connected with the input end of the iteration submodule. The iteration submodule has three input ends, the first is an initial input end controlled by an SR terminal, the second is a clock signal terminal controlled by a control clock, and the third is an input end fed back from the calculation submodule.
Specifically, the character recognition module employs four CR units to process the character image with noise. The method mainly comprises a calculation submodule and an iteration submodule. By calculating the processing function of the sub-module and the iterative effect of the iterative sub-module, four character images 'W', 'H', 'A' and 'T' interfered by noise can be identified. The signal processing module with simplified circuit function is realized by adopting four adder units. In the signal processing module, the 100 output signals from the character recognition module are processed into eight output signals, and abstract meanings are given to the eight output signals. The convergence module is implemented by designing a fully-connected memristive neural network circuit that can converge 24 ordering cases to one case (WHAT).
As shown in fig. 2, the computation submodule will have 100 inputs for four characters since each character can be mapped into a 5 x 5 matrix, i.e. 25 inputs per character. The input ends of the computation submodule are connected with the output ends of the iteration submodule in a one-to-one correspondence mode, every 25 input signals of the computation submodule are connected with a memristor array in series, the output ends of the memristor array are connected with one input end of 100 operational amplifiers in a one-to-one correspondence mode, and the other input end of each operational amplifier is grounded. The input ends of the 100 inverters are connected with the output ends of the operational amplifiers in a one-to-one correspondence mode, and the output ends of the inverters output signals of the calculation sub-modules.
The calculation submodule comprises a calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4(ii) a Calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4All input ends ofConnected to the output of the iteration submodule, a calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4The output ends of the signal processing modules are connected with the input end of the signal processing module; calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4Each comprising a first memristor array, a first amplifier AM and a first inverter INV'; the input end of the first memristor array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of a first amplifier AM, the output end of the first amplifier AM is connected with the input end of a first inverter INV ', and the output end of the first inverter INV ' is respectively connected with the input end of the signal processing module and the input end of a feedback amplifier OP '.
The first memristor array comprises 625 memristors, the size of the first memristor array being 25 × 25; 25 first amplifiers are arranged, and 25 first inverters are arranged; each row of memristors of the first memristor array is connected with a first amplifier AM, the first amplifiers AM are connected with the first inverters in a one-to-one correspondence mode, and the inverting input end of each first amplifier AM is connected with a resistor R1Connected to the output of the first amplifier AM. The memristor comprises a combination switch and a memristor M, the combination switch comprises a first buffer OP, an inverter INV ' and a switch K, the common end of the input end of the first buffer OP after the input end of the first buffer OP is connected with the inverter INV ' in parallel is the input end of the memristor, the output end of the first buffer OP or the output end of the inverter INV ' after the output end of the first buffer OP is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor.
Fig. 1 shows a basic neuron circuit designed according to an embodiment of the present invention, in which input ends of a first buffer OP and an inverter INV ' are used as a total input end, an output end of the first buffer OP or an output end of the inverter INV ' is connected to one end of a switch K, the first buffer OP, the inverter INV ' and the switch K are referred to as a combination switch, and a memristor M is connected in series to the other end of the combination switch. The inverting input end of the first amplifier AM is connected with the memristor M, and the inverse of the first amplifier AMPhase input terminal through memristor R1The output end of the first amplifier AM is connected with a first inverter INV ', and the first inverter INV' outputs an output signal of the four-character memristive neural network circuit. The positive and negative threshold voltages of the four-character memristive neural network circuit are controlled by a combined switch, M, R1AM and INV' together form a proportional amplifier. The first inverter INV ″ is a threshold voltage inverter. When the input voltage of INV 'is less than the threshold voltage, the output voltage is 1v, and when the input voltage of INV' is greater than the threshold value, the output voltage is-1 v.
In particular, the calculation submodule comprises a unit CAL1-CAL4. Each CAL cell includes a first memristor array with combinational switches, 25 first amplifiers, and 25 first inverters. In-unit CAL1Middle, IN1-IN25Representative of the input signal, OT1-OT25Representing the output signal. M1-M625Memristors forming a memristor array, each combination switch being connected in series to each memristor in the first memristor array. Each first amplifier AM is connected to a column of the memristor array, and output signals of the first amplifiers AM are connected with the first inverters INV ″ in a one-to-one correspondence. R1Is a resistance of 1k omega. The first inverter INV "receives the output signal of the first amplifier AM and compares with a voltage of-0.04 v. OT when the input signal of the first inverter INV' is greater than-0.04 v1-OT25Is-1 v; OT when the input signal of the first inverter INV' is less than-0.04 v1-OT25Is 1 v. The circuit connection principle of the remaining three computation units and the computation unit CAL1The same is true.
In order to feed back the output signal of the calculation submodule to the signal input, an iteration submodule is designed. As shown in fig. 3, the output signal of the iteration sub-module is repeatedly fed back to the input signal port of the iteration sub-module through the computation sub-module. The iteration submodule comprises 100 iterator units, each iterator unit comprises a first D trigger, a second D trigger and a second buffer OP1(ii) a Input ends I of the first D trigger and the second D triggerThe input end II of the first D trigger is connected with the output end of the feedback amplifier OP', the output end of the first D trigger is connected with the input end II of the second D trigger, and the output end of the second D trigger is connected with the second buffer OP1Is connected to the inverting input terminal of the second buffer OP1The non-inverting input terminal of the second buffer OP is grounded1Is connected to the first memristor array.
The clock signal comprises a first clock signal CL1And a second clock signal CL2First clock signal CL1Connected to the clock terminal of the first D flip-flop, a second clock signal CL2Is connected to the clock terminal of the second D flip-flop. The first D flip-flop comprises a first NAND gate NAND1A second NAND gate NAND2NAND of the third NAND gate3NAND gate, and a fourth NAND gate4And a second inverter; first NAND gate NAND1Respectively with the output of the feedback amplifier OP', the first clock signal CL1Connected to a first NAND gate1And the output end of the first NAND gate NAND with the third NAND gate NAND3Are connected with the input end of the power supply; second NAND gate NAND2Respectively with a first clock signal CL1The output end of the second inverter is connected, the input end of the second inverter is connected with the output end of the feedback amplifier OP', and the NAND gate is NAND2And the output end of the fourth NAND gate NAND4Are connected with the input end of the power supply; third NAND gate NAND3Is provided with an S terminal, a third NAND gate NAND3The S terminal of the NAND-gate is connected with a character input signal, and the NAND-gate of the third NAND-gate3Respectively with a fourth NAND gate4The input end of the second D trigger is connected with the input end II of the second D trigger; the fourth NAND gate NAND4Is provided with an R terminal, a fourth NAND gate NAND4Is connected with the character input signal, a fourth NAND gate NAND4And the output end of the first NAND gate NAND with the third NAND gate NAND3Are connected.
The second D flip-flops each include a fifth flip-flopNAND gate1And a sixth NAND gate NAND2NAND gate3And an eighth NAND gate NAND4And a third inverter; the fifth NAND gate NAND1The input end of the first NAND gate is respectively connected with the output end of the third NAND gate and the second clock signal, and the fifth NAND gate1And the seventh NAND gate NAND3Are connected with the input end of the power supply; the sixth NAND gate NAND2Respectively with the second clock signal CL2The output end of the third inverter is connected, and the input end of the third inverter is connected with the NAND gate of the third NAND gate3Is connected with the output end of the sixth NAND gate NAND2And the eighth NAND gate NAND4Are connected with the input end of the power supply; the seventh NAND gate NAND3Is provided with an S terminal, a seventh NAND gate3Is connected with the character input signal, a seventh NAND gate NAND3Respectively with the eighth NAND gate4Input terminal of, second buffer OP1Are connected with the input end of the power supply; the eighth NAND gate NAND4Is provided with an R terminal, an eighth NAND gate NAND4Is connected with the character input signal, an eighth NAND gate NAND4And the seventh NAND gate NAND3Are connected.
Specifically, the iteration submodel is composed of 100 iteration units, namely ITE1-ITE100. As shown in fig. 3(b), each iterator unit is composed of two D flip-flops and a buffer, and each D flip-flop is composed of four nand gates and an inverter. The structure of the D flip-flop is shown in fig. 3 (a). NAND1The D and CL input signals may be received. In order to obtain a voltage opposite to the input signal at the D terminal, an inverter is added. NAND2Can receive input signals of inverter terminal and CL terminal, S terminal, NAND1、NAND4Are all NAND3Connected, R terminal, NAND2、NAND3Are all NAND4Are connected. Q terminal represents NAND3The output signal of (1). When the initial value of CL is set to 0v, the D flip-flop does not function, and the output signal is affected only by the output signals of the S terminal and the R terminal. If the S terminal is 0v and the R terminal is 1v, the outputThe signal Q is 1v, at which time the state of the D flip-flop is "1". If the S terminal is 1v and the R terminal is 0v, the output signal Q is 0v, and the state of the D flip-flop is "0". To ensure that the D terminal does not function at the beginning, both the S terminal and the R terminal should be set to 1v before the CL terminal is given a voltage of 1 v. In this case, if the output signal of the D terminal is 0v, the NAND1And NAND2Are 1v and 0v, respectively. Thus, NAND4Is 1v, and then NAND is obtained3The output signal of (1). Output voltage due to Q and NAND3The output voltage of (2) is 0v, so the state of the D flip-flop is "0". When the output signal of D is 1v, NAND1And NAND2Are 0v and 1v, respectively. Then NAND3The output signal of (1) is 1v and the state of the D flip-flop is "1".
In the iteration unit of the iteration sub-module, ITE1Composed of a first D flip-flop, a second D flip-flop and an OP1And (4) forming. The two D flip-flops are controlled by a clock signal to delay the input signal. In iteration unit ITE1The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop, and the Q terminal of the second D flip-flop is connected to the OP1。OP1Is a buffer with a threshold of 0.8 v. If from OP1If the received voltage is greater than 0.8v, the output voltage is 1 v; if OP1The received voltage is less than 0.8v, and the output voltage is-1 v. The initial state is represented by signal R before both clock signals are set to 1v1And S1And (5) controlling. When R is1And S1The state of the second D flip-flop is "1" at voltages of 0v and 1v, respectively. When R is1And S1The state of the second D flip-flop is "0" at voltages of 1v and 0v, respectively. When R is1And S1When the voltage of the second D flip-flop is 1v, the second D flip-flop is kept in the original state. If OP1Receiving an output signal initialized to 1v, then OP1The output state of (1) is "1". On the contrary, if OP1Receiving an output signal initialized to 0v, then OP1The output state of (1) is "-1". The D terminal of the first D flip-flop is connected to O1，OP1Is connected to the calculationIN of submodule1. Architecture and ITE of the remaining 99 iterator units1Similarly.
As shown in fig. 4, the character recognition module includes a computation submodule and an iteration submodule. The computation submodule processes the information received from the iteration submodule and returns the result to the input of the iteration submodule. To facilitate the iterative logic of the submodule, a buffer with a threshold voltage of 0.8v is added. The input ends of the buffers are connected with the output signals in the calculation submodule in a one-to-one correspondence mode, the other input end of each buffer is grounded, and the output ends of the buffers are connected with the input ends of the iteration submodule in a one-to-one correspondence mode. The output signal of the computation submodule passes through a buffer OP1And (6) performing conversion. Therefore, when OT1-OT100Is greater than 0.8v, O1-O100Is 1 v; when OT1-OT100Is less than 0.8v, O1-O100Is 0 v. CR1-CR4The four character recognition units jointly construct a character recognition module which simultaneously recognizes four characters. The initial signal of the character recognition module is controlled by S and R.
As shown in fig. 5, the signal processing module comprises an adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4(ii) a Adder unit AD1Is connected to the calculation unit CAL1Are connected to the output of the adder unit AD2Is connected to the calculation unit CAL2Are connected to the output of the adder unit AD3Is connected to the calculation unit CAL3Are connected to the output of the adder unit AD4Is connected to the calculation unit CAL4Are connected to the output of the adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4The output ends of the convergence modules are connected with the input end of the convergence module; adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4All comprise a memristor M1，M2，...，M38A second amplifier, a third amplifier, a first comparisonA comparator and a second comparator; memory resistance M1，M2，...，M17The input ends of the first inverter and the second inverter are respectively connected with the 1 st first inverter to the 17 th first inverter of each calculation unit in a one-to-one correspondence mode, and the memristor M1，M2，...，M17Are all connected to a second amplifier AM1Is connected to the inverting input terminal of the second amplifier AM1Is connected to the inverting input terminal through the memristor M37Connected to the output of a second amplifier AM1And the first comparator CP1Is connected to the inverting input terminal of the first comparator CP1Is connected to a voltage input signal (+2V), a first comparator CP1The output end of the convergence module is connected with the input end of the convergence module; memory resistance M18，M19，...，M36The input ends of the memory resistors are respectively connected with the output ends of the 7 th to the 25 th first inverters INV' of each calculation unit in a one-to-one correspondence mode, and the memory resistors M18，M19，...，M36Are all connected to a third amplifier AM2Is connected to the inverting input terminal of the third amplifier AM2Is connected to the inverting input terminal through the memristor M38And a third amplifier AM2Is connected to the output terminal of the third amplifier AM2And the output of the second comparator CP2Is connected to the inverting input terminal of the second comparator CP2Is connected to a voltage input signal (+2V), and a second comparator CP2The output end of the convergence module is connected with the input end of the convergence module.
In particular, the resistance M is memorized in the adder unit1-M17Respectively with the output signal OT1-OT17Are connected. Second amplifier AM1And memristor M37Respectively with M1-M17Is connected to the output terminal of the second amplifier AM1Through memory resistor M37And a second amplifier AM1Is connected to the output terminal of the second amplifier AM1And the first comparator CP1The inverting input ends of the two are correspondingly connected; in the same way, memory resistance M18-M36Respectively with the output signal OT7-OT25Are connected in a one-to-one correspondence. Third amplifier AM2And memristor M38Respectively with M18-M36Is connected to the output terminal of the third amplifier AM2Through memory resistor M38And a third amplifier AM2Is connected to the output terminal of the third amplifier AM2And the output of the third comparator CP2Are connected. CP (CP)1And CP2Is grounded through a 2v voltage, U1-U2Are respectively CP1-CP2The input signal of (1). Comparator CP1And CP2For comparison of the voltage of 2 v. When U is turned1And U2Greater than 2v, IC1And IC2The output signal of (1 v); when U is turned1And U2Less than 2v, IC1And IC2The output signal of (2) is 0 v. In AD1Two adder circuits are constructed to convert the 25 output signals of the recognized character into 2 output signals that can be adapted to the convergence module. Circuit design and AD of the remaining three adder units1Similarly.
As shown in fig. 6, the convergence module converts multiple input cases into one output case using a memristor-based neural network. The convergence module is composed of a fully-connected neural network circuit based on memristors. The convergence module comprises a second memristor array and a fourth amplifier AM3And a fourth inverter INV1(ii) a The input ends of the second memristor array are respectively connected with the first comparator CP1A second comparator CP2Is connected with the output end of the second memristor array, and the output end of the second memristor array is connected with the fourth amplifier AM3Is connected to the input terminal of the fourth amplifier AM3Output terminal of and fourth inverter INV1Is connected to the input terminal of the fourth inverter INV1The output end of the four-character memristor neural network circuit outputs an output signal of the four-character memristor neural network circuit. The second memristor array comprises 64 memristors, the size of the second memristor array being 8 × 8; the fourth amplifier AM3Is provided with 8, a fourth inverter INV1There are 8; each column of memristors of the second memristor array is connected with a fourth amplifier AM3Fourth amplifier AM3Is provided with an inverting input end passing through a memristor R2And a fourth amplifier AM3Is connected to the output terminal of the fourth amplifier AM3Output terminal of and fourth inverter INV1And the connection is in one-to-one correspondence.
The second memristor array is connected with input signals in the horizontal direction, is connected with one input end of eight amplifiers in the vertical direction, the other input end of the amplifier is grounded, and the fourth amplifier AM3Respectively with the fourth inverter INV1Are connected in one-to-one correspondence, a fourth inverter INV1The output terminal of the convergence module outputs the output signal of the convergence module. I isC1-IC8Input signal to the convergence module, OC1-OC8Is the output signal of the convergence module. M702-M765And forming an 8 x 8 second memristor array, wherein the connected input signals are output signals of the memristor array in the horizontal direction and in the vertical direction. AM (amplitude modulation)3Is connected to the output signal of the second memristor array. R2Is a 1k omega resistor. AM (amplitude modulation)3Is passed through INV1To obtain OC1-OC8。INV1An inverter with a threshold voltage of-0.4 v. When INV1Is less than-0.4 v, OC1-OC8Is 1 v. When INV1When the input voltage is greater than-0.4 v, OC1-OC8Is 0 v.
As shown in fig. 8, the iteration sub-module can be divided into two initial states of the input signal due to the output states of "1" and "-1". When the output state is "1", setting the input signal to type 1; when the output state is "-1", the input signal is set to type 2. To show the iteration steps more clearly, the delay time is set to 1us, with two D flip-flops per ITE cell at CL1And CL2Under the control of (3), the states are changed alternately, and the iterative operation is completed. For example, if the initial state of the first input is "-1", then at ITE1The input signal in the cell is set to type 1. At 0us, CL1＝CL2＝0v，S11v and R10v, then the Q terminal output of the second D flip-flop is0v，OP1The output voltage of (1) is-1 v. To ensure CL1Is 1v, the output state is not limited by S1And R1The influence of (c). After 1us, S1And R1Given 1 v. At 2us, CL1＝1v，CL20v, then Q1＝O1. Since the second D flip-flop is not affected by the clock signal at this time, -1v is still output. At 5us, CL1＝0v，CL21v, then Q1And Q2Output signal of (1) and O1The previous moment of time of (a) is equal. At 7us, CL1＝CL20v, then Q1And Q2The output signal of (2) is maintained in the original state. Thus, from 0us to 8us, signal initialization and the first iteration are completed. The output signal of the iteration submodule is sent to the calculation submodule for the next processing. Simultaneous flip-flop at CL1And CL2Alternately changing their states under control of (2). The iterative principle of type 2 is similar to type 1. Based on this principle, the input signal of the character recognition module can be preset.
As shown in fig. 9, the noisy character image is converted into 4 5 × 5 matrices, and the element values in each matrix are preset to the initial value states of the respective ITE cells in fig. 8. "1" and "-1" represent two types of input states in the circuit. When the input state of the element is "-1", the input signal corresponding to the ITE unit is set as type 1; when the input state of the element is "1", the input signal corresponding to the ITE cell is set to type 2. As shown in FIG. 9(a), if the element value of sequence number 1 is "1", ITE is obtained1Unit S1、R1、CL1、CL2Is type 2; when the element value of sequence number 2 is "-1", ITE is set2S of the unit2、R2、CL1、CL2Is type 1; likewise, ITE3-ITE100Selects the setting type according to the element values of sequence numbers 3-100. Application of ITE in circuit1-ITE100As an input signal for the character recognition module.
Simulation of the character recognition Module Circuit As shown in FIG. 10, four characters "W"The simulations of "H", "A" and "T" correspond to FIGS. 10(a) - (d), respectively. O isT1-OT100Representing the output signal of the character recognition module. The output signals are of four types as shown in FIG. 10, all 1v, all-1 v, 1v to-1 v, -1v to 1v, respectively. Since the initialization process and the first iteration are completed in 0 us. The output signal changes only 5us later, and remains stable after 5us later, which indicates that the character recognition module reaches a stable state only after the first iteration. When the output signal is 1v, the state is 1; when the output signal is-1 v, the state is "-1". Mixing O withT1-OT100The state after 5us is compared with the four matrices in fig. 9(b), and if the comparison results are the same, the four characters are recognized.
As shown in fig. 11, the signal processing module is used to simplify the output signal, four characters are replaced with four binary digits, and thus two signals represent one character. The features "W", "H", "a" and "T" are denoted by "00", "01", "10" and "11", respectively. O isT1-OT100Representing the input signal of the signal processing module, IC1-IC8Representing the output signal. The simulation of the signal processing module is shown in fig. 11 (a). Due to the receipt of OT1-OT100Influence of (A) IC1-IC8Changes also occur. In FIG. 11(a), IC1-IC8The voltage value before 5us was "00001011". I isC1-IC8Becomes "00011011" at 5us and remains stable after 5 us.
The final convergence result is shown in FIG. 11(b), where the convergence module is used to implement the Word (WHAT), IC1-IC8Representing the input signal of the convergence module, OC1-OC8Representing the output signal. The simulation of the convergence module is shown in fig. 11. 0us-16us, OC1-OC8The output signal of (a) is "00011011". Due to OC1-OC8The stable output signal of "00011011" demonstrates the final convergence results as "W", "H", "a", "T", and simulation results show that the circuit can recognize four characters simultaneously and converge to a Word (WHAT).
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A four-character memristor neural network circuit with recognition and sorting functions is characterized by comprising a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is respectively connected with a character input signal and a clock signal, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is respectively connected with a character input signal and a clock signal, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier, and the output end of the feedback amplifier is connected with the input end of the iteration submodule.
2. The four-character memristive neural network circuit with recognition and sorting functions of claim 1, wherein the computation submodule comprises a computation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4(ii) a Calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4Are all connected with the output end of the iteration submodule, and a calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4The output ends of the signal processing modules are connected with the input end of the signal processing module; calculation unit CAL1Computing unit CAL2Computing unit CAL3And a calculation unit CAL4Each comprising a first memristor array, a first amplifier, and a first inverter; first memristorThe input end of the array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of the first amplifier, the output end of the first amplifier is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier.
3. The four-character memristive neural network circuit with recognition and sorting functionality of claim 2, wherein the first memristor array comprises 625 memristors, the first memristor array being 25 x 25 in size; 25 first amplifiers are arranged, and 25 first inverters are arranged; each row of memristors of the first memristor array is connected with a first amplifier, the first amplifiers are connected with the first inverters in a one-to-one correspondence mode, and the inverting input end of each first amplifier is connected with the output end of the corresponding first amplifier through a resistor.
4. The four-character memristor neural network circuit with the functions of identification and sequencing as claimed in claim 3, wherein the memristor comprises a combination switch and a memristor M, the combination switch comprises a first buffer, an inverter INV ' and a switch K, the common end of the input end of the first buffer and the input end of the inverter INV ' is the input end of the memristor, the output end of the first buffer or the output end of the inverter INV ' is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor.
5. The four-character memristive neural network circuit with recognition and sorting functions of claim 2, wherein the iterator submodule comprises 100 iterator cells, each iterator cell comprising a first D flip-flop, a second D flip-flop, and a second buffer; the input ends I of the first D trigger and the second D trigger are connected with a character input signal, the clock terminals of the first D trigger and the second D trigger are connected with a clock signal, the input end II of the first D trigger is connected with the output end of the feedback amplifier, the output end of the first D trigger is connected with the input end II of the second D trigger, the output end of the second D trigger is connected with the inverting input end of the second buffer, the non-inverting input end of the second buffer is grounded, and the output end of the second buffer is connected with the first memristor array.
6. The four-character memristive neural network circuit with recognition and sorting functions of claim 5, wherein the clock signals comprise a first clock signal connected with a clock terminal of a first D flip-flop and a second clock signal connected with a clock terminal of a second D flip-flop.
7. The four-character memristive neural network circuit with recognition and sorting functions of claim 6, wherein the first D flip-flop comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a second inverter; the input end of the first NAND gate is respectively connected with the output end of the feedback amplifier and the first clock signal, and the output end of the first NAND gate is connected with the input end of the third NAND gate; the input end of the second NAND gate is respectively connected with the first clock signal and the output end of the second inverter, the input end of the second inverter is connected with the output end of the feedback amplifier, and the output end of the second NAND gate is connected with the input end of the fourth NAND gate; an S terminal is arranged on the third NAND gate, the S terminal of the third NAND gate is connected with a character input signal, and the output end of the third NAND gate is respectively connected with the input end of the fourth NAND gate and the input end of the second D trigger; the fourth NAND gate is provided with an R terminal, the R terminal of the fourth NAND gate is connected with a character input signal, and the output end of the fourth NAND gate is connected with the input end of the third NAND gate;
the second D flip-flops respectively comprise a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate and a third inverter; the input end of the fifth NAND gate is respectively connected with the output end of the third NAND gate and the second clock signal, and the output end of the fifth NAND gate is connected with the input end of the seventh NAND gate; the output end of the sixth NAND gate is respectively connected with the second clock signal and the output end of the third inverter, the input end of the third inverter is connected with the output end of the third NAND gate, and the output end of the sixth NAND gate is connected with the input end of the eighth NAND gate; an S terminal is arranged on the seventh NAND gate, the S terminal of the seventh NAND gate is connected with the character input signal, and the output end of the seventh NAND gate is respectively connected with the input end of the eighth NAND gate and the input end of the second buffer; and the eighth NAND gate is provided with an R terminal, the R terminal of the eighth NAND gate is connected with a character input signal, and the output end of the eighth NAND gate is connected with the input end of the seventh NAND gate.
8. The four-character memristive neural network circuit with recognition and sorting functions of claim 3, wherein the signal processing module comprises an adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4(ii) a Adder unit AD1Is connected to the calculation unit CAL1Are connected to the output of the adder unit AD2Is connected to the calculation unit CAL2Are connected to the output of the adder unit AD3Is connected to the calculation unit CAL3Are connected to the output of the adder unit AD4Is connected to the calculation unit CAL4Are connected to the output of the adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4The output ends of the convergence modules are connected with the input end of the convergence module; adder unit AD1Adder unit AD2Adder unit AD3Sum adder unit AD4All comprise a memristor M1，M2，...，M38The first amplifier, the second amplifier, the third amplifier, the first comparator and the second comparator; memory resistance M1，M2，...，M17The input ends of the first inverter and the second inverter are respectively connected with the 1 st first inverter to the 17 th first inverter of each calculation unit in a one-to-one correspondence mode, and the memristor M1，M2，...，M17And the output end of the first amplifier and the inverting input end of the second amplifierThe inverting input end of the second amplifier is connected through a memristor M37The output end of the second amplifier is connected with the inverting input end of the first comparator, the positive phase input end of the first comparator is connected with the voltage input signal, and the output end of the first comparator is connected with the input end of the convergence module; memory resistance M18，M19，...，M36The input ends of the memristors are respectively connected with the output ends of the 7 th to the 25 th first inverters of each computing unit in a one-to-one correspondence manner, and the memristor M18，M19，...，M36The output ends of the first and second amplifiers are connected with the inverting input end of a third amplifier, and the inverting input end of the third amplifier is connected with the inverting input end of the third amplifier through a memristor M38The output end of the third amplifier is connected with the inverting input end of the second comparator, the non-inverting input end of the second comparator is connected with the voltage input signal, and the output end of the second comparator is connected with the input end of the convergence module.
9. The four-character memristive neural network circuit with recognition and sorting functions of claim 8, wherein the convergence module comprises a second memristor array, a fourth amplifier, and a fourth inverter; the input end of the second memristor array is connected with the output end of the first comparator respectively, the output end of the second memristor array is connected with the input end of the fourth amplifier, the output end of the fourth amplifier is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs an output signal of the four-character memristor neural network circuit.
10. The four-character memristive neural network circuit with recognition and sorting functionality of claim 9, wherein the second memristor array comprises 64 memristors, the size of the second memristor array being 8 x 8; the number of the fourth amplifiers is 8, and the number of the fourth inverters is 8; each column of memristors of the second memristor array is connected with a fourth amplifier, and the inverting input end of the fourth amplifier is connected with the fourth amplifier through a memristor R2Connected to the output of the fourth amplifierAnd the output end of the fourth amplifier is correspondingly connected with the input end of the fourth inverter one by one.
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| CN113642723A (en) * | 2021-07-29 | 2021-11-12 | 安徽大学 | GRU neural network circuit for realizing original-ectopic training |
| CN113642723B (en) * | 2021-07-29 | 2024-05-31 | 安徽大学 | GRU neural network circuit for implementing original-ectopic training |
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| CN112734022B (en) | 2023-12-19 |
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