CN112734022B - Four-character memristor neural network circuit with recognition and sequencing functions - Google Patents
Four-character memristor neural network circuit with recognition and sequencing functions Download PDFInfo
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Abstract
The invention provides a four-character memristor neural network circuit with identification and sequencing functions, which is used for solving the technical problem that the existing artificial neural network consumes a large amount of computing power. The invention comprises a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is respectively connected with a character input signal and a clock signal, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristive neural network circuit. The Hopfield neural network is constructed by memristors to ensure that weights can be trained repeatedly; the weight can be expressed by a synaptic circuit formed by a memory resistor and an operational amplifier so as to obtain a positive synaptic weight and a negative synaptic weight; the invention can simultaneously recognize and sort four characters interfered by noise and converge the final result into a word form.
Description
Technical Field
The invention relates to the technical field of digital-analog circuits, in particular to a four-character memristor neural network circuit with identification and sequencing functions.
Background
An artificial neural network is a research hotspot in the field of artificial intelligence, and shows good intelligent characteristics in the aspects of biological recognition, predictive estimation, pattern recognition, robot control and the like. It is a difficult task to build a human brain-like mechanism on a traditional digital computer based on von neumann architecture. Digital computers typically process information in sequence, while the brain processes information in parallel. Compared with digital computers, the biological brain is more flexible and easier to learn new things. In order to effectively perform the functions of the biological brain, a new computing architecture is required.
In 1971, professor Chua creatively proposed a basic element defining the relationship of charge to magnetic flux and named memristor. In 2008, memristors were taught by Strukov and their colleagues in the hewlett-packard laboratory. Memristors function similarly to synapses in biological nervous systems. Memristors are more suitable for electronic synapses due to their nano-size, non-volatility, and integration with CMOS. Subsequently, many studies have shown that memristors can act as electronic synapses, and the weight of the synapses can be represented by the conductance of the memristors. The combination of the memory resistor and the neural network can greatly simplify the circuit structure and optimize the information processing capability. Memristors therefore provide a new technology for the design of synaptic hardware circuits.
The conventional digital recognition method cannot recognize well in the presence of interference, and the associative memory function of the Hopfield neural network is of great advantage in this respect. Hopfield neural network and learning algorithm were first proposed by the United states physicist Hopfield in 1982, and have opened up a new research path for the development of artificial neural networks. In addition, the memory mechanism of the biological neural network is simulated by utilizing different structural characteristics and learning methods of the hierarchical neural network, and a satisfactory result is obtained. By constructing complementary metal oxide semiconductor circuits as synapses, hopfield neural networks with large chip area and high power consumption are realized. Memristor-based artificial neural networks provide a foundation for the development of image recognition technology, and associative memory neural network circuits based on memristor are also proposed. Memristive-based neural networks have been greatly developed by virtue of their unique advantages.
Disclosure of Invention
Aiming at the technical problem that the existing artificial neural network depends on a von Neumann structure and needs to consume a large amount of calculation force, the invention provides a four-character memristor neural network circuit with identification and sequencing functions based on the novel calculation system structure, which can identify four letters at the same time and converge the final result into a word WHAT form.
The technical scheme of the invention is realized as follows:
the four-character memristor neural network circuit with the recognition and sequencing functions comprises a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is connected with a character input signal and a clock signal respectively, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is connected with a character input signal and a clock signal respectively, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is connected with the input end of the signal processing module and the input end of the feedback amplifier respectively, and the output end of the feedback amplifier is connected with the input end of the iteration submodule.
The computing submodule comprises a computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The method comprises the steps of carrying out a first treatment on the surface of the Calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The input ends of the (a) are connected with the output ends of the iteration submodules, and the computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The output ends of the signal processing modules are connected with the input ends of the signal processing modules; calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 Each including a first memristor array, a first amplifier, and a first inverter; the input end of the first memristor array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of the first amplifier, the output end of the first amplifier is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier.
The first memristor array comprises 625 memristors, and the size of the first memristor array is 25×25; the number of the first amplifiers is 25, and the number of the first inverters is 25; each column of memristors of the first memristor array is connected with a first amplifier, the first amplifiers are connected with the first inverters in one-to-one correspondence, and the inverting input ends of the first amplifiers are connected with the output ends of the first amplifiers through resistors.
The memristor comprises a combined switch and memristor M, the combined switch comprises a first buffer, an inverter INV ' and a switch K, the common end of the input end of the first buffer and the input end of the inverter INV ' is the input end of the memristor, the output end of the first buffer or the output end of the inverter INV ' is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor.
The iteration submodule comprises 100 iterator units, and each iterator unit comprises a first D trigger, a second D trigger and a second buffer; the input ends I of the first D trigger and the second D trigger are connected with character input signals, clock terminals of the first D trigger and the second D trigger are connected with clock signals, the input end II of the first D trigger is connected with the output end of the feedback amplifier, the output end of the first D trigger is connected with the input end II of the second D trigger, the output end of the second D trigger is connected with the inverting input end of the second buffer, the non-inverting input end of the second buffer is grounded, and the output end of the second buffer is connected with the first memristor array.
The clock signals comprise a first clock signal and a second clock signal, the first clock signal is connected with the clock terminal of the first D trigger, and the second clock signal is connected with the clock terminal of the second D trigger.
The first D trigger comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a second inverter; the input end of the first NAND gate is respectively connected with the output end of the feedback amplifier and the first clock signal, and the output end of the first NAND gate is connected with the input end of the third NAND gate; the input end of the second NAND gate is respectively connected with the first clock signal and the output end of the second inverter, the input end of the second inverter is connected with the output end of the feedback amplifier, and the output end of the second NAND gate is connected with the input end of the fourth NAND gate; the S terminal is arranged on the third NAND gate, the S terminal of the third NAND gate is connected with a character input signal, and the output end of the third NAND gate is respectively connected with the input end of the fourth NAND gate and the input end of the second D trigger; the R terminal is arranged on the fourth NAND gate, the R terminal of the fourth NAND gate is connected with a character input signal, and the output end of the fourth NAND gate is connected with the input end of the third NAND gate;
the second D flip-flops comprise a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate and a third inverter; the input end of the fifth NAND gate is connected with the output end of the third NAND gate and the second clock signal respectively, and the output end of the fifth NAND gate is connected with the input end of the seventh NAND gate; the output end of the sixth NAND gate is respectively connected with the second clock signal and the output end of the third inverter, the input end of the third inverter is connected with the output end of the third NAND gate, and the output end of the sixth NAND gate is connected with the input end of the eighth NAND gate; the S terminal is arranged on the seventh NAND gate, the S terminal of the seventh NAND gate is connected with a character input signal, and the output end of the seventh NAND gate is respectively connected with the input end of the eighth NAND gate and the input end of the second buffer; and the output end of the eighth NAND gate is connected with the input end of the seventh NAND gate.
The signal processing module comprises an adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The method comprises the steps of carrying out a first treatment on the surface of the Adder unit AD 1 Input of (c) and computing unit CAL 1 Is connected to the output terminal of the adder unit AD 2 Input of (c) and computing unit CAL 2 Is connected to the output terminal of the adder unit AD 3 Input of (c) and computing unit CAL 3 Is connected to the output terminal of the adder unit AD 4 Input of (c) and computing unit CAL 4 Is connected to the output terminal of the adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The output ends of the convergence module are connected with the input end of the convergence module; adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 All include memristance M 1 ，M 2 ，...，M 38 The second amplifier, the third amplifier, the first comparator and the second comparator; memristor M 1 ，M 2 ，...，M 17 The input ends of the first and the second inverters are respectively connected with the 1 st to the 17 th first inverters of each calculation unit in a one-to-one correspondence manner, and the memristor M 1 ，M 2 ，...，M 17 The output ends of the second amplifier are connected with the inverting input end of the second amplifier, and the inverting input end of the second amplifier passes through the memristor M 37 The output end of the second amplifier is connected with the inverting input end of the first comparator, the non-inverting input end of the first comparator is connected with the voltage input signal, and the output end of the first comparator is connected with the input end of the convergence module; memristor M 18 ，M 19 ，...，M 36 The input ends of the first inverters from 7 to 25 of each calculation unit are respectively connected in one-to-one correspondence with the output ends of the first inverters, and the memristor M 18 ，M 19 ，...，M 36 The output ends of the third amplifier are connected with the inverting input end of the third amplifier, and the inverting input end of the third amplifier passes through the memristor M 38 The output end of the second comparator is connected with the input end of the convergence module.
The convergence module comprises a second memristor array, a fourth amplifier and a fourth inverter; the input end of the second memristor array is respectively connected with the output end of the first comparator, the output end of the second memristor array is connected with the input end of the fourth amplifier, the output end of the fourth amplifier is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs an output signal of the four-character memristor neural network circuit.
The second memristor array comprises 64 memristors, and the size of the second memristor array is 8×8; the number of the fourth amplifiers is 8, and the number of the fourth inverters is 8; each column of memristors of the second memristor array is connected with a fourth amplifier, and the inverting input end of the fourth amplifier passes through memristor R 2 The output ends of the fourth amplifiers are connected with the input ends of the fourth inverter in a one-to-one correspondence.
Compared with the prior art, the invention has the beneficial effects that:
1) The Hopfield neural network is constructed by memristors to ensure that weights can be trained repeatedly; the weight can be expressed by a synaptic circuit formed by a memory resistor and an operational amplifier so as to obtain a positive synaptic weight and a negative synaptic weight;
2) The invention solves the problem that the traditional artificial neural network depends on a von Neumann structure and needs to consume a large amount of computation force, and the memristor-based neural network circuit can simultaneously identify and sort four characters interfered by noise, so that the function has very important significance for the development of artificial intelligence.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit diagram of a neuron according to the present invention.
Fig. 2 is a circuit diagram of a calculation sub-module of the present invention.
Fig. 3 is a circuit diagram of an iterative sub-module of the present invention.
Fig. 4 is a circuit diagram of a character recognition module according to the present invention.
Fig. 5 is a circuit diagram of a signal processing module according to the present invention.
Fig. 6 is a circuit diagram of a convergence module of the present invention.
FIG. 7 is a complete circuit diagram of the present invention
Fig. 8 is a simulation diagram of two types of clock inputs of the present invention.
Fig. 9 is a schematic illustration of the present invention.
Fig. 10 is a diagram showing simulation results of the character recognition module according to the present invention.
FIG. 11 is a diagram of the final simulation results of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 7, the embodiment of the invention provides a four-character memristor neural network circuit with recognition and sequencing functions, which comprises a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is respectively connected with a character input signal and a clock signal, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is connected with a character input signal and a clock signal respectively, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is connected with the input end of the signal processing module and the input end of the feedback amplifier respectively, and the output end of the feedback amplifier is connected with the input end of the iteration submodule. The iteration submodule has three input ends, the first is an initial input end controlled by the SR terminal, the second is a clock signal terminal triggered by a control clock, and the third is an input end fed back from the calculation submodule.
Specifically, the character recognition module processes noisy character images using four CR units. The method mainly comprises a calculation sub-module and an iteration sub-module. Four character images W, H, A and T which are interfered by noise can be identified through the processing function of the calculation sub-module and the iteration effect of the iteration sub-module. The signal processing module with simplified circuit function is realized by adopting four adder units. In the signal processing module, 100 output signals from the character recognition module are processed into eight output signals, and abstract meanings are given to the eight output signals. The convergence module is realized by designing a fully connected memristive neural network circuit, and the fully connected memristive neural network circuit can converge 24 sort cases to one case (WHAT).
As shown in fig. 2, the computation submodule has 100 inputs for each character since each character can be mapped to a 5 x 5 matrix, i.e., 25 inputs for each character. The input ends of the calculation submodules are connected with the output ends of the iteration submodules in a one-to-one correspondence mode, every 25 input signals of the calculation submodules are connected with a memristor array in series, the output ends of the memristor array are connected with one input end of 100 operational amplifiers in a one-to-one correspondence mode, and the other input ends of the operational amplifiers are grounded. The input ends of the 100 inverters are connected with the output ends of the operational amplifier in a one-to-one correspondence manner, and the output ends of the inverters output signals of the computing submodule.
The computing submodule comprises a computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The method comprises the steps of carrying out a first treatment on the surface of the Calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The input ends of the (a) are connected with the output ends of the iteration submodules, and the computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The output ends of the signal processing modules are connected with the input ends of the signal processing modules; calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 Each comprising a first memristor array, a first amplifier AM and a first inverter INV "; the input end of the first memristor array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of the first amplifier AM, the output end of the first amplifier AM is connected with the input end of the first inverter INV ', and the output end of the first inverter INV is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier OP'.
The first memristor array comprises 625 memristors, and the size of the first memristor array is 25×25; the number of the first amplifiers is 25, and the number of the first inverters is 25; each column of memristors of the first memristor array A first amplifier AM is connected with the first inverter in a one-to-one correspondence manner, and the inverting input end of the first amplifier AM is connected with the first inverter through a resistor R 1 Is connected to the output of the first amplifier AM. The memristor comprises a combined switch and memristor M, the combined switch comprises a first buffer OP, an inverter INV ' and a switch K, the common end of the input end of the first buffer OP and the input end of the inverter INV ' after being connected in parallel is the input end of the memristor, the output end of the first buffer OP or the output end of the inverter INV ' after being connected in parallel is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor.
Fig. 1 shows a basic neuron circuit designed according to an embodiment of the present invention, in which input ends of a first buffer OP and an inverter INV ' are used as total input ends, an output end of the first buffer OP or an output end of the inverter INV ' is connected to one end of a switch K, the first buffer OP, the inverter INV ' and the switch K are called a combination switch, and the other end of the combination switch is connected in series with a memristor M. The inverting input end of the first amplifier AM is connected with the memristor M, and the inverting input end of the first amplifier AM passes through the memristor R 1 The output end of the first amplifier AM is connected with a first inverter INV' which outputs an output signal of the four-character memristor neural network circuit. Positive and negative threshold voltages of the four-character memristor neural network circuit are controlled by a combined switch, M, R 1 Together, AM, INV "form a proportional amplifier. The first inverter inv″ is a threshold voltage inverter. When the input voltage of INV 'is smaller than the threshold voltage, the output voltage is 1v, and when the input voltage of INV' is larger than the threshold value, the output voltage is-1 v.
Specifically, the computation submodule includes a unit CAL 1 -CAL 4 . Each CAL unit includes a first memristor array with a combination switch, 25 first amplifiers, and 25 first inverters. In unit CAL 1 IN (1) 1 -IN 25 Represents the input signal, OT 1 -OT 25 Representing the output signal. M is M 1 -M 625 Memristors constituting a memory resistor array, each combination switch being connected in series toEach memristor in the first array of memristors. Each first amplifier AM is connected to a column of the memristor array, and the output signals of the first amplifiers AM are connected to the first inverters inv″ in a one-to-one correspondence. R is R 1 Is a 1k omega resistor. The first inverter inv″ receives the output signal of the first amplifier AM and compares with a voltage of-0.04 v. When the input signal of the first inverter inv″ is greater than-0.04 v, OT 1 -OT 25 Is-1 v; when the input signal of the first inverter inv″ is less than-0.04 v, OT 1 -OT 25 1v. Circuit connection principle of the remaining three computing units and computing unit CAL 1 The same applies.
In order to feed back the output signal of the calculation submodule to the signal input, an iteration submodule is designed. As shown in fig. 3, the output signal of the iteration submodule is repeatedly fed back to the input signal port of the iteration submodule through the calculation submodule. The iteration submodule comprises 100 iterator units, each iterator unit comprises a first D trigger, a second D trigger and a second buffer OP 1 The method comprises the steps of carrying out a first treatment on the surface of the The input ends I of the first D trigger and the second D trigger are connected with the character input signal, the clock terminals of the first D trigger and the second D trigger are connected with the clock signal, the input end II of the first D trigger is connected with the output end of the feedback amplifier OP', the output end of the first D trigger is connected with the input end II of the second D trigger, and the output end of the second D trigger is connected with the second buffer OP 1 Is connected to the inverting input terminal of the second buffer OP 1 The non-inverting input terminal of (a) is grounded, and the second buffer OP 1 Is connected to the first memristor array.
The clock signal comprises a first clock signal CL 1 And a second clock signal CL 2 First clock signal CL 1 Connected to the clock terminal of the first D flip-flop, the second clock signal CL 2 Is connected to the clock terminal of the second D flip-flop. The first D flip-flop includes a first NAND gate NAND 1 Second NAND gate NAND 2 Third NAND gate NAND 3 NAND with fourth NAND gate 4 And a second inverter; first NAND gate NAND 1 Is input to (a)Respectively with the output end of the feedback amplifier OP', the first clock signal CL 1 Connected with a first NAND gate NAND 1 And a third NAND gate NAND 3 Is connected with the input end of the power supply; second NAND gate NAND 2 Respectively with the input end of the first clock signal CL 1 The output end of the second inverter is connected with the output end of the feedback amplifier OP', and the second NAND gate NAND 2 And a fourth NAND gate NAND 4 Is connected with the input end of the power supply; third NAND gate NAND 3 An S terminal and a third NAND gate NAND are arranged on 3 S terminal of the third NAND gate is connected with the character input signal 3 Respectively with the output end of the fourth NAND gate 4 The input end II of the second D trigger is connected with the input end II of the second D trigger; fourth NAND gate NAND 4 An R terminal and a fourth NAND gate NAND are arranged on 4 R terminal of (2) is connected with character input signal, fourth NAND gate NAND 4 And a third NAND gate NAND 3 Is connected to the input terminal of the circuit.
The second D flip-flops each include a fifth NAND gate 1 NAND with sixth NAND gate 2 NAND with seventh NAND gate 3 NAND of eighth NAND gate 4 And a third inverter; fifth NAND gate NAND 1 The input end of the third NAND gate is connected with the output end of the second clock signal, and the fifth NAND gate NAND 1 NAND with seventh NAND gate 3 Is connected with the input end of the power supply; sixth NAND gate NAND 2 Respectively with the second clock signal CL 2 The output end of the third inverter is connected with the NAND gate of the third NAND gate 3 Is connected with the output end of the sixth NAND gate 2 And an eighth NAND gate NAND 4 Is connected with the input end of the power supply; seventh NAND gate NAND 3 An S terminal and a seventh NAND gate NAND are arranged on 3 S terminal of (A) is connected with character input signal, seventh NAND gate NAND 3 Respectively with the eighth NAND gate 4 Input end of (a) second buffer OP 1 Is connected with the input end of the power supply; eighth NAND gate NAND 4 The R terminal is arranged on the upper part of the connecting rod,eighth NAND gate NAND 4 R terminal of (2) is connected with character input signal, eighth NAND gate NAND 4 NAND with seventh NAND gate 3 Is connected to the input terminal of the circuit.
Specifically, the iterative submodel consists of 100 iterative units, ITE respectively 1 -ITE 100 . As shown in fig. 3 (b), each iterator unit is composed of two D flip-flops and one buffer, and each D flip-flop is composed of four nand gates and one inverter. The structure of the D flip-flop is shown in fig. 3 (a). NAND 1 The D-side and CL-side input signals may be received. To obtain a voltage opposite to the input signal at the D terminal, an inverter is added. NAND 2 Can receive input signals of an inverter end and a CL end, an S terminal and NAND 1 、NAND 4 Are all with NAND 3 Connected with R terminal and NAND 2 、NAND 3 Are all with NAND 4 Are connected. The Q terminal represents NAND 3 Is provided. When the initial value of CL is set to 0v, the d flip-flop is not active and the output signal is affected only by the output signals of the S terminal and the R terminal. If the S terminal is 0v and the R terminal is 1v, then the output signal Q is 1v, and the state of the D flip-flop is "1". If the S terminal is 1v and the R terminal is 0v, then the output signal Q is 0v, at which time the state of the D flip-flop is "0". To ensure that the D terminal is not active at the beginning, both the S and R terminals should be set to 1v before the CL terminal is given a voltage of 1v. In this case, if the output signal of the D terminal is 0v, NAND 1 And NAND 2 The output signals of (2) are 1v and 0v, respectively. Thus, NAND 4 The output signal of (2) is 1v, thereby obtaining NAND 3 Is provided. Due to the output voltage of Q and NAND 3 The output voltages of the D flip-flops are all 0v, so the state of the D flip-flop is "0". When the output signal of D is 1v, NAND 1 And NAND 2 The output signals of (2) are 0v and 1v, respectively. Then NAND 3 The output signal of (1 v) and the state of the d flip-flop is "1".
In the iteration unit of the iteration sub-module, ITE 1 From a first D flip-flop, a second D flip-flop and OP 1 Composition is prepared. The two D flip-flops are controlled by a clock signal to delay the input signal. In iterationUnit ITE 1 Wherein the Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop, and the Q terminal of the second D flip-flop is connected to the OP 1 。OP 1 Is a buffer with a threshold of 0.8 v. If from OP 1 The received voltage is greater than 0.8v, and the output voltage is 1v; if OP 1 The received voltage is less than 0.8v, and the output voltage is-1 v. The initial state is defined by signal R before the two clock signals are set to 1v 1 And S is 1 And (5) controlling. When R is 1 And S is 1 When the voltages are 0v and 1v, respectively, the state of the second D flip-flop is "1". When R is 1 And S is 1 When the voltages are 1v and 0v, respectively, the state of the second D flip-flop is "0". When R is 1 And S is 1 When the voltages of the two flip-flops are 1v, the second D flip-flop is kept in the original state. If OP 1 Receiving the output signal initialized to 1v, then OP 1 The output state of (2) is "1". Conversely, if OP 1 Receiving an output signal initialized to 0v, then OP 1 The output state of (2) is "-1". The D terminal of the first D flip-flop is connected to O 1 ，OP 1 Is connected to the IN of the calculation submodule 1 . Structure and ITE of the remaining 99 iterator units 1 Similarly.
As shown in fig. 4, the character recognition module includes a calculation sub-module and an iteration sub-module. The computation submodule processes the information received from the iteration submodule and returns the result to the input of the iteration submodule. To facilitate the logical operation of the iterative submodules, a buffer with a threshold voltage of 0.8v is added. The input ends of the buffers are connected with the output signals in the calculation submodules in a one-to-one correspondence mode, the other input ends of the buffers are grounded, and the output ends of the buffers are connected with the input ends of the iteration submodules in a one-to-one correspondence mode. The output signal of the calculation sub-module passes through the buffer OP 1 And performing conversion. Thus, when OT 1 -OT 100 Is greater than 0.8v, O 1 -O 100 1v; when OT 1 -OT 100 Is less than 0.8v, O 1 -O 100 0v. CR (computed radiography) 1 -CR 4 Is four character recognition units, and a character recognition module for simultaneously recognizing four characters is commonly constructed. Character recognition The initial signals of the other modules are controlled by S and R.
As shown in fig. 5, the signal processing module includes an adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The method comprises the steps of carrying out a first treatment on the surface of the Adder unit AD 1 Input of (c) and computing unit CAL 1 Is connected to the output terminal of the adder unit AD 2 Input of (c) and computing unit CAL 2 Is connected to the output terminal of the adder unit AD 3 Input of (c) and computing unit CAL 3 Is connected to the output terminal of the adder unit AD 4 Input of (c) and computing unit CAL 4 Is connected to the output terminal of the adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The output ends of the convergence module are connected with the input end of the convergence module; adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 All include memristance M 1 ，M 2 ，...，M 38 The second amplifier, the third amplifier, the first comparator and the second comparator; memristor M 1 ，M 2 ，...，M 17 The input ends of the first and the second inverters are respectively connected with the 1 st to the 17 th first inverters of each calculation unit in a one-to-one correspondence manner, and the memristor M 1 ，M 2 ，...，M 17 Are all connected with the output end of the second amplifier AM 1 Is connected to the inverting input terminal of the second amplifier AM 1 Through memristance M 37 Is connected with the output end of the second amplifier AM 1 And the output end of the first comparator CP 1 Is connected to the inverting input terminal of the first comparator CP 1 A first comparator CP connected to the positive input terminal of the voltage input signal (+2V) 1 The output end of the convergence module is connected with the input end of the convergence module; memristor M 18 ，M 19 ，...，M 36 The input ends of the first inverters (7 to 25) of each calculation unit are respectively connected with the output ends of the first inverter INV' one by one, and the memristor M 18 ，M 19 ，...，M 36 Are all connected with the output end of the third amplifier AM 2 Is connected to the inverting input terminal of the third amplifier AM 2 Through memristance M 38 And a third amplifier AM 2 Is connected to the output terminal of the third amplifier AM 2 And the output terminal of the second comparator CP 2 Is connected to the inverting input terminal of the second comparator CP 2 A second comparator CP connected to the positive input terminal of the voltage input signal (+2V) 2 The output end of the convergence module is connected with the input end of the convergence module.
Specifically, the memory resistor M in the adder unit 1 -M 17 Respectively and output signal OT 1 -OT 17 Is connected with each other. Second amplifier AM 1 And memristor M 37 Respectively with M 1 -M 17 Is connected to the output terminal of the second amplifier AM 1 Through memristor M 37 And a second amplifier AM 1 Is connected to the output terminal of the second amplifier AM 1 And the output end of the first comparator CP 1 Is correspondingly connected with the inverting input end of the input circuit; similarly, memristance M 18 -M 36 Respectively with the output signal OT 7 -OT 25 And are connected in a one-to-one correspondence. Third amplifier AM 2 And memristor M 38 Respectively with M 18 -M 36 Is connected with the output end of the third amplifier AM 2 Through memristor M 38 And a third amplifier AM 2 Is connected to the output terminal of the third amplifier AM 2 And a third comparator CP 2 Is connected to the inverting input terminal of (c). CP (control program) 1 And CP 2 Is grounded through a 2v voltage, U 1 -U 2 Respectively CP 1 -CP 2 Is provided. Comparator CP 1 And CP 2 For comparison of voltages of 2 v. When U is 1 And U 2 Above 2v, I C1 And I C2 The output signal of (2) is 1v; when U is 1 And U 2 When the voltage is less than 2v, I C1 And I C2 The output signal of (2) is 0v. In AD 1 Two adder circuits are constructed to convert the 25 output signals of the recognized character into 2 output signals that can be accommodated by the convergence module. Circuit of the remaining three adder unitsDesign and AD 1 Similarly.
As shown in fig. 6, the convergence module converts multiple input cases to one output case using a memristor-based neural network. The convergence module consists of a fully-connected neural network circuit based on memristors. The convergence module comprises a second memristor array and a fourth amplifier AM 3 And a fourth inverter INV 1 The method comprises the steps of carrying out a first treatment on the surface of the The input ends of the second memristor array are respectively connected with the first comparator CP 1 Second comparator CP 2 The output end of the second memristor array is connected with the fourth amplifier AM 3 Is connected to the input of a fourth amplifier AM 3 Output end of (a) and fourth inverter INV 1 Is connected with the input end of the fourth inverter INV 1 The output end of the four-character memristor neural network circuit. The second memristor array comprises 64 memristors, and the size of the second memristor array is 8×8; the fourth amplifier AM 3 There are 8, fourth inverter INV 1 8; each column of memristors of the second memristor array is connected with a fourth amplifier AM 3 Fourth amplifier AM 3 Through memristor R 2 And a fourth amplifier AM 3 Is connected to the output terminal of the fourth amplifier AM 3 Output end of (a) and fourth inverter INV 1 And the connection is in one-to-one correspondence.
The horizontal direction of the second memristor array is connected with an input signal, the vertical direction is connected with one input end of eight amplifiers, the other input end of each amplifier is grounded, and the fourth amplifier AM 3 Respectively with the output end of the fourth inverter INV 1 The input ends of the fourth inverter INV are connected in one-to-one correspondence 1 The output end of the convergence module outputs an output signal of the convergence module. I C1 -I C8 For converging the input signal of the module, O C1 -O C8 Is the output signal of the convergence module. M is M 702 -M 765 And forming a second memristor array of 8 multiplied by 8, wherein the horizontal direction of the connected input signals is the memristor array, and the vertical direction is the output signals of the memristor array. AM (AM) 3 The inverting input terminal of the second memristor array is connected with an output signal of the second memristor array. R is R 2 Is one1kΩ resistance. AM (AM) 3 The output signal of INV 1 Obtaining O C1 -O C8 。INV 1 An inverter with a threshold voltage of-0.4 v. When INV 1 When the input signal of (2) is smaller than-0.4 v, O C1 -O C8 1v. When INV 1 When the input voltage is greater than-0.4 v, O C1 -O C8 0v.
As shown in fig. 8, the iterative sub-modules can be divided into two types of initial states of the input signal due to the output states of "1" and "-1". When the output state is "1", the input signal is set to type 1; when the output state is "-1", the input signal is set to type 2. To more clearly show the iterative steps, the delay time is set to 1us, two D flip-flops per ITE unit at CL 1 And CL 2 Under the control of (a) alternately changing the state to complete the iterative operation. For example, if the initial state of the first input is "-1", then at ITE 1 The input signal in the cell is set to type 1. At 0us, CL 1 ＝CL 2 ＝0v，S 1 =1v and R 1 =0v, then the Q terminal output of the second D flip-flop is 0v, op 1 -1v at the output voltage of (c). To ensure CL 1 1v, output state is not affected by S 1 And R is 1 Is a function of (a) and (b). After 1us, S 1 And R is 1 Given 1v. At 2us, CL 1 ＝1v，CL 2 =0v, then Q 1 ＝O 1 . Since the second D flip-flop is not affected by the clock signal at this time, it still outputs-1 v. At 5us, CL 1 ＝0v，CL 2 =1v, then Q 1 And Q 2 Output signal of (2) and O 1 Equal to the previous time of day. At 7us, CL 1 ＝CL 2 =0v, then Q 1 And Q 2 The output signal of (2) remains in the original state. Thus, from 0us to 8us, signal initialization and the first iteration are completed. The output signal of the iteration sub-module is sent to the calculation sub-module for the next processing. While the trigger is at CL 1 And CL 2 Alternately changing their state under control of (a). The iterative principle of type 2 is similar to type 1. Based on this principle, the input signal of the character recognition module may be preset.
As shown in fig. 9, the noisy character image is converted into 4 5×5 matrices, and the element values in each matrix are preset to the respective ITE unit initial value states in fig. 8. "1" and "-1" represent two types of input states in a circuit. When the input state of the element is "-1", the input signal corresponding to the ITE unit is set as type 1; when the input state of the element is "1", the input signal corresponding to the ITE unit is set to type 2. As shown in FIG. 9 (a), if the element value of sequence number 1 is "1", ITE is the same 1 Unit S 1 、R 1 、CL 1 、CL 2 Is of type 2; when the element value of the sequence number 2 is '1', the ITE is set 2 S of units 2 、R 2 、CL 1 、CL 2 Is of type 1; likewise, ITE 3 -ITE 100 The setting type is selected based on the element values of sequence numbers 3-100. Application of ITE in circuits 1 -ITE 100 As input signal for the character recognition module.
Simulation of the character recognition module circuit as shown in fig. 10, simulation of four characters "W", "H", "a", "T" corresponds to fig. 10 (a) - (d), respectively. O (O) T1 -O T100 Representing the output signal of the character recognition module. The output signals are of four types, 1v to 1v, and 1v to 1v, respectively, as shown in fig. 10. Since the initialization process and the first iteration are done at 0 us. The output signal changes only at 5us, remains stable after 5us, indicating that the character recognition module reaches a steady state only after the first iteration. When the output signal is 1v, the state is 1; when the output signal is-1 v, the state is "-1". O is added with T1 -O T100 The state after 5us is compared with the four matrices in fig. 9 (b), and if the comparison result is the same, the four characters are recognized.
As shown in fig. 11, the signal processing module is used to simplify the output signal, and four characters are replaced with four binary digits, so that two signals represent one character. The characteristics of "W", "H", "a", "T" are denoted as "00", "01", "10", "11", respectively. O (O) T1 -O T100 Representing signalsProcessing input signals of the modules, I C1 -I C8 Representing the output signal. The simulation of the signal processing module is shown in fig. 11 (a). Due to O T1 -O T100 Is the influence of I C1 -I C8 Changes also occur. In FIG. 11 (a), I C1 -I C8 The voltage value before 5us was "00001011". I C1 -I C8 The voltage of (2) becomes "00011011" at 5us and remains stable after 5 us.
Final convergence results as shown in fig. 11 (b), the convergence module is used to implement word (wha), I C1 -I C8 Represents the input signal of the convergence module, O C1 -O C8 Representing the output signal. The simulation of the convergence module is shown in fig. 11. 0us-16us, O C1 -O C8 Is "00011011". Due to O C1 -O C8 The stable output signal of (a) is "00011011", which demonstrates that the final convergence result is "W", "H", "a", "T", and the simulation result shows that the circuit can recognize four characters simultaneously and converge to a word (wha).
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (1)
1. The four-character memristor neural network circuit with the recognition and sequencing functions is characterized by comprising a character recognition module, a signal processing module and a convergence module, wherein the input end of the character recognition module is connected with a character input signal and a clock signal respectively, the output end of the character recognition module is connected with the input end of the signal processing module, the output end of the signal processing module is connected with the input end of the convergence module, and the output end of the convergence module outputs an output signal of the four-character memristor neural network circuit; the character recognition module comprises an iteration submodule and a calculation submodule, wherein the input end of the iteration submodule is respectively connected with a character input signal and a clock signal, the output end of the iteration submodule is connected with the input end of the calculation submodule, the output end of the calculation submodule is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier, and the output end of the feedback amplifier is connected with the input end of the iteration submodule;
The computing submodule comprises a computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The method comprises the steps of carrying out a first treatment on the surface of the Calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The input ends of the (a) are connected with the output ends of the iteration submodules, and the computing unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 The output ends of the signal processing modules are connected with the input ends of the signal processing modules; calculation unit CAL 1 Calculation unit CAL 2 Calculation unit CAL 3 And a calculation unit CAL 4 Each including a first memristor array, a first amplifier, and a first inverter; the input end of the first memristor array is connected with the output end of the iteration submodule, the output end of the first memristor array is connected with the input end of the first amplifier, the output end of the first amplifier is connected with the input end of the first inverter, and the output end of the first inverter is respectively connected with the input end of the signal processing module and the input end of the feedback amplifier; the first memristor array comprises 625 memristors, and the size of the first memristor array is 25×25; the number of the first amplifiers is 25, and the number of the first inverters is 25; each column of memristors of the first memristor array is connected with a first amplifier, the first amplifiers are connected with the first inverters in a one-to-one correspondence manner, and the inverting input ends of the first amplifiers are connected with the output ends of the first amplifiers through resistors; the memristor comprises a combined switch and a memristor M, wherein the combined switch comprises a first buffer, an inverter INV ' and a switch K, the common end of the input end of the first buffer and the input end of the inverter INV ' is the input end of the memristor, the output end of the first buffer or the output end of the inverter INV ' is connected with one end of the switch K, the other end of the switch K is connected with one end of the memristor M, and the other end of the memristor M is the output end of the memristor;
The iteration submodule comprises 100 iterator units, and each iterator unit comprises a first D trigger, a second D trigger and a second buffer; the input ends I of the first D trigger and the second D trigger are connected with character input signals, clock terminals of the first D trigger and the second D trigger are connected with clock signals, the input end II of the first D trigger is connected with the output end of the feedback amplifier, the output end of the first D trigger is connected with the input end II of the second D trigger, the output end of the second D trigger is connected with the inverting input end of the second buffer, the non-inverting input end of the second buffer is grounded, and the output end of the second buffer is connected with the first memristor array; the clock signals comprise a first clock signal and a second clock signal, the first clock signal is connected with a clock terminal of the first D trigger, and the second clock signal is connected with a clock terminal of the second D trigger; the first D trigger comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and a second inverter; the input end of the first NAND gate is respectively connected with the output end of the feedback amplifier and the first clock signal, and the output end of the first NAND gate is connected with the input end of the third NAND gate; the input end of the second NAND gate is respectively connected with the first clock signal and the output end of the second inverter, the input end of the second inverter is connected with the output end of the feedback amplifier, and the output end of the second NAND gate is connected with the input end of the fourth NAND gate; the S terminal is arranged on the third NAND gate, the S terminal of the third NAND gate is connected with a character input signal, and the output end of the third NAND gate is respectively connected with the input end of the fourth NAND gate and the input end of the second D trigger; the R terminal is arranged on the fourth NAND gate, the R terminal of the fourth NAND gate is connected with a character input signal, and the output end of the fourth NAND gate is connected with the input end of the third NAND gate; the second D flip-flops comprise a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate and a third inverter; the input end of the fifth NAND gate is connected with the output end of the third NAND gate and the second clock signal respectively, and the output end of the fifth NAND gate is connected with the input end of the seventh NAND gate; the output end of the sixth NAND gate is respectively connected with the second clock signal and the output end of the third inverter, the input end of the third inverter is connected with the output end of the third NAND gate, and the output end of the sixth NAND gate is connected with the input end of the eighth NAND gate; the S terminal is arranged on the seventh NAND gate, the S terminal of the seventh NAND gate is connected with a character input signal, and the output end of the seventh NAND gate is respectively connected with the input end of the eighth NAND gate and the input end of the second buffer; the R terminal is arranged on the eighth NAND gate, the R terminal of the eighth NAND gate is connected with a character input signal, and the output end of the eighth NAND gate is connected with the input end of the seventh NAND gate;
The signal processing module comprises an adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The method comprises the steps of carrying out a first treatment on the surface of the Adder unit AD 1 Input of (c) and computing unit CAL 1 Is connected to the output terminal of the adder unit AD 2 Input of (c) and computing unit CAL 2 Is connected to the output terminal of the adder unit AD 3 Input of (c) and computing unit CAL 3 Is connected to the output terminal of the adder unit AD 4 Input of (c) and computing unit CAL 4 Is connected to the output terminal of the adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 The output ends of the convergence module are connected with the input end of the convergence module; adder unit AD 1 Adder unit AD 2 Adder unit AD 3 And adder unit AD 4 All include memristance M 1 ,M 2 ,…,M 38 The second amplifier, the third amplifier, the first comparator and the second comparator; memristor M 1 ,M 2 ,…,M 17 The input ends of the first and the second inverters are respectively connected with the 1 st to the 17 th first inverters of each calculation unit in a one-to-one correspondence manner, and the memristor M 1 ,M 2 ,…,M 17 The output ends of the second amplifier are connected with the inverting input end of the second amplifier, and the inverting input end of the second amplifier passes through the memristor M 37 Is connected with the output end of the second amplifier, the output end of the second amplifier is connected with the inverting input end of the first comparator, the non-inverting input end of the first comparator is connected with the voltage input signal, and the output end of the first comparator is connected with the convergence module The input end is connected; memristor M 18 ,M 19 ,…,M 36 The input ends of the first inverters from 7 to 25 of each calculation unit are respectively connected in one-to-one correspondence with the output ends of the first inverters, and the memristor M 18 ,M 19 ,…,M 36 The output ends of the third amplifier are connected with the inverting input end of the third amplifier, and the inverting input end of the third amplifier passes through the memristor M 38 The output end of the second comparator is connected with the input end of the convergence module;
the convergence module comprises a second memristor array, a fourth amplifier and a fourth inverter; the input end of the second memristor array is respectively connected with the output end of the first comparator, the output end of the second memristor array is connected with the input end of the fourth amplifier, the output end of the fourth amplifier is connected with the input end of the fourth inverter, and the output end of the fourth inverter outputs an output signal of the four-character memristor neural network circuit; the second memristor array comprises 64 memristors, and the size of the second memristor array is 8×8; the number of the fourth amplifiers is 8, and the number of the fourth inverters is 8; each column of memristors of the second memristor array is connected with a fourth amplifier, and the inverting input end of the fourth amplifier passes through memristor R 2 The output ends of the fourth amplifiers are connected with the input ends of the fourth inverter in a one-to-one correspondence.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
| CN109711537A (en) * | 2018-11-30 | 2019-05-03 | 郑州轻工业学院 | A kind of prediction circuit based on memristor neural network |
| CN110991624A (en) * | 2019-12-31 | 2020-04-10 | 桂林电子科技大学 | Variable pulse width input charge accumulation type memristor neural network circuit |
| WO2020115746A1 (en) * | 2018-12-04 | 2020-06-11 | Technion Research & Development Foundation Limited | Delta-sigma modulation neurons for high-precision training of memristive synapses in deep neural networks |
| CN111507464A (en) * | 2020-04-19 | 2020-08-07 | 华中科技大学 | Equation solver based on memristor array and operation method thereof |
| CN111600583A (en) * | 2020-06-02 | 2020-08-28 | 中北大学 | Random frequency triangular wave generator based on diffusion memristor and current transmitter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9715655B2 (en) * | 2013-12-18 | 2017-07-25 | The United States Of America As Represented By The Secretary Of The Air Force | Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems |
| US11403518B2 (en) * | 2018-04-25 | 2022-08-02 | Denso Corporation | Neural network circuit |
| KR102368962B1 (en) * | 2019-03-22 | 2022-03-03 | 국민대학교산학협력단 | Neural network system including gate circuit for controlling memristor array circuit |
-
2021
- 2021-02-02 CN CN202110143875.7A patent/CN112734022B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
| CN109711537A (en) * | 2018-11-30 | 2019-05-03 | 郑州轻工业学院 | A kind of prediction circuit based on memristor neural network |
| WO2020115746A1 (en) * | 2018-12-04 | 2020-06-11 | Technion Research & Development Foundation Limited | Delta-sigma modulation neurons for high-precision training of memristive synapses in deep neural networks |
| CN110991624A (en) * | 2019-12-31 | 2020-04-10 | 桂林电子科技大学 | Variable pulse width input charge accumulation type memristor neural network circuit |
| CN111507464A (en) * | 2020-04-19 | 2020-08-07 | 华中科技大学 | Equation solver based on memristor array and operation method thereof |
| CN111600583A (en) * | 2020-06-02 | 2020-08-28 | 中北大学 | Random frequency triangular wave generator based on diffusion memristor and current transmitter |
Non-Patent Citations (1)
| Title |
|---|
| 自旋忆阻CPSO-PID神经网络;李小娟;段书凯;王丽丹;;西南大学学报(自然科学版)(第11期);全文 * |
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