CN113285708B - Four-color guessing circuit based on memristor neural network - Google Patents

Abstract

The invention provides a four-color guessing circuit based on a memristive neural network, which is used for solving the problems that the four-color guessing theory is complicated to deduce and the hardware circuit is difficult to realize. The invention comprises an input module, a judging module, a retaining module and a correcting module, wherein the input terminal of the input module is respectively connected with a Q terminal and a digital signal terminal, the output terminal of the input module is respectively connected with the input terminal of the judging module, the input terminal of the retaining module and the input terminal of the correcting module, the output terminal of the judging module is connected with the input terminal of the retaining module, and the output terminal of the retaining module and the output terminal of the correcting module both output signals of the four-color guessing circuit. The invention builds a four-color guess circuit based on memristive neural network, realizes the four-coloring function of five areas, and solves the problem that the four-color guess circuit is difficult to realize by a hardware circuit; the memristive neural network has strong inclusion, and provides reference for more complex circuit design.

Description

Four-color guessing circuit based on memristor neural network

Technical Field

The invention relates to the technical field of digital-analog circuits, in particular to a four-color guessing circuit based on a memristor neural network.

Background

Cai Shaotang of the university of california, berkeley division, usa teaches 1971 that the fourth basic circuit element, memristance, was predicted from a symmetry point of view to define the relationship of charge and magnetic flux. Memristors are novel double-ended passive circuit elements, and the derivation of memristors cannot be achieved by using an RLC network because the characteristics of the memristors are different from resistance, inductance or capacitance. In 2008, scientific researchers in the American Hewlett packard laboratory prepare memristive entities and release results in the Nature journal when conducting very small circuit experiments. In 2012, thomas team at university of bilevel, germany developed memristions with learning ability, and published the research results in journal of physics school in 2013, and analyzed how to convert natural phenomena into technical systems by using computers of the nerve-imitating system for the first time. Memristors are stored and calculated simultaneously in the same physical device, so that the memristor is very suitable for realizing an efficient biological heuristic neural network on hardware, and is researched by vast students. Biological synapses are connected through neurons to form a simple neural network, and the neural network is used for completing specific tasks by updating the synaptic weights.

Four-color guesses were first proposed in 1852 by the university student griss work as one of three problems in recent mathematical history. The four-color hypothesis is also known as the four-color theorem and four-color problem, indicating that on any one map, the countries that will be co-bordered are differently colored with four colors. Explained in numerical language, assuming that each region is labeled with the numbers "1", "2", "3", "4", then adjacent regions are unlikely to appear the same number.

Over a lengthy period of 100 years, countless students have attempted to verify the correctness of four-color guesses using manual logic methods, but all end up with failures. The advent of high-speed calculators provided equipment support for verifying four-color guesses, in 1976, the professor of math Ha Ken in the united states and the professor of aper utilized 3 high-speed electronic computers at the university of illinois, in the united states, and eventually demonstrated a four-color guess problem called one of three major problems over 1200 hours. Although the four-color guess problem has been well-validated by computers far above the human brain, it still has a unique appeal and is attracting a great number of scholars to constantly study. With respect to four-color guesses, problems based on conventional proving methods have been studied by many scholars, but problems of implementing four-color guesses based on hardware circuits have been discussed. Aiming at the problem that a four-color guess hardware circuit is difficult to realize, the invention designs the four-color guess circuit based on the memristor neural network.

Disclosure of Invention

Aiming at the problems that the four-color guess theory is complicated to deduce and the hardware circuit is difficult to realize, the invention provides a four-color guess circuit based on a memristive neural network.

The technical scheme of the invention is realized as follows:

the four-color guess circuit based on memristor neural network comprises an input module, a judging module, a retaining module and a correcting module, wherein an input terminal of the input module is respectively connected with a Q terminal and a digital signal terminal, an output terminal of the input module is respectively connected with an input terminal of the judging module, an input terminal of the retaining module and an input terminal of the correcting module, an output terminal of the judging module is connected with an input terminal of the retaining module, and an output terminal of the retaining module and an output terminal of the correcting module all output signals of the four-color guess circuit.

Preferably, the input module comprises a signal processing unit I, a signal processing unit II, a signal processing unit III, a signal processing unit IV and a signal processing unit V; the input terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V respectively comprise a first input terminal, a second input terminal and a third input terminal, the first input terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are respectively connected with the Q terminal, and the second input terminal of the signal processing unit I is connected with the digital signal terminal A ₀ A third input terminal of the signal processing unit I is connected with the digital signal terminal A ₁ A second input terminal of the signal processing unit II is connected with the digital signal terminal B ₀ Is connected with the third input terminal of the signal processing unit II and the digital signal terminal B ₁ A second input terminal of the signal processing unit III is connected with the digital signal terminal C ₀ Is connected with the third input terminal of the signal processing unit III and the digital signal terminal C ₁ A second input terminal of the signal processing unit IV is connected with the digital signal terminal D ₀ Is connected with the third input terminal of the signal processing unit IV and the digital signal terminal D ₁ A second input terminal of the signal processing unit V is connected with the digital signal terminal E ₀ A third input terminal of the signal processing unit V is connected with the digital signal terminal E ₁ Is connected with each other; the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the judging module, and the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are respectively connected with the input terminal of the judging moduleThe output terminals of the signal processing unit V are connected with the input terminal of the retaining module, and the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are connected with the input terminal of the correction module.

Preferably, the signal processing unit I includes an inverter INV ₁ -INV ₂ AND gate AND ₁ -AND ₄ And switch K ₁ -K ₄ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁ AND gate AND ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₀ Respectively with inverter INV ₁ AND gate AND ₂ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₁ Respectively with inverter INV ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the inverter INV ₁ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₃ Is connected with the input end of the inverter INV ₂ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₂ Is connected with the input end of the power supply; AND gate AND ₁ Output of (d) and switch K ₁ A switch K connected to the first positive terminal ₁ Second positive terminal of (a) and switch K ₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁ Is connected with the first negative terminal of the switch K ₁ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₂ Output of (d) and switch K ₂ A switch K connected to the first positive terminal ₂ Second positive terminal of (a) and switch K ₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂ Is connected with the first negative terminal of the switch K ₂ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₃ Output of (d) and switch K ₃ A switch K connected to the first positive terminal ₃ Second positive terminal of (a) and switch K ₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃ Is connected with the first negative terminal of the switch K ₃ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₄ Output of (d) and switch K ₄ A switch K connected to the first positive terminal ₄ Second positive terminal of (a) and switch K ₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₄ Is connected with the first negative terminal of the switch K ₄ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁ Second positive terminal of (a) switch K ₂ Second positive terminal of (a) switch K ₃ Second positive terminal of (c) and switch K ₄ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₁ And switch K ₁ Is a first negative terminal of switch K ₂ Is a first negative terminal of switch K ₃ Is connected to the first negative terminal of the switch K ₄ Is grounded; output signal O ₁ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected; the voltage of the voltage source I is 1V, the voltage of the voltage source II is 2V, the voltage of the voltage source III is 3V, and the voltage of the voltage source IV is 4V;

the signal processing unit II comprises an inverter INV ₃ -INV ₄ AND gate AND ₅ -AND ₈ And switch K ₅ -K ₈ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₅ AND gate AND ₆ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₀ Respectively with inverter INV ₃ AND gate AND ₆ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₁ Respectively with inverter INV ₄ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the inverter INV ₃ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₇ Is connected with the input end of the inverter INV ₄ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₆ Is connected with the input end of the power supply; AND gate AND ₅ Output of (d) and switch K ₅ A switch K connected to the first positive terminal ₅ Second positive terminal of (a) and switch K ₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₅ Is connected to the first negative terminal of (a)And switch K ₅ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₆ Output of (d) and switch K ₆ A switch K connected to the first positive terminal ₆ Second positive terminal of (a) and switch K ₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₆ Is connected with the first negative terminal of the switch K ₆ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₇ Output of (d) and switch K ₇ A switch K connected to the first positive terminal ₇ Second positive terminal of (a) and switch K ₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₇ Is connected with the first negative terminal of the switch K ₇ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₈ Output of (d) and switch K ₈ A switch K connected to the first positive terminal ₈ Second positive terminal of (a) and switch K ₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₈ Is connected with the first negative terminal of the switch K ₈ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₅ Second positive terminal of (a) switch K ₆ Second positive terminal of (a) switch K ₇ Second positive terminal of (c) and switch K ₈ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₂ And switch K ₅ Is a first negative terminal of switch K ₆ Is a first negative terminal of switch K ₇ Is connected to the first negative terminal of the switch K ₈ Is grounded; output signal O ₂ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit III comprises an inverter INV ₅ -INV ₆ AND gate AND ₉ -AND ₁₂ And switch K ₉ -K ₁₂ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₉ AND gate AND ₁₀ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the digital signal terminal C ₀ Respectively with inverter INV ₅ AND gate AND ₁₀ AND AND gate AND ₁₂ Is connected with the input end of the digital signalSignal terminal C ₁ Respectively with inverter INV ₆ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the inverter INV ₅ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₁ Is connected with the input end of the inverter INV ₆ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₀ Is connected with the input end of the power supply; AND gate AND ₉ Output of (d) and switch K ₉ A switch K connected to the first positive terminal ₉ Second positive terminal of (a) and switch K ₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₉ Is connected with the first negative terminal of the switch K ₉ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₀ Output of (d) and switch K ₁₀ A switch K connected to the first positive terminal ₁₀ Second positive terminal of (a) and switch K ₁₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₀ Is connected with the first negative terminal of the switch K ₁₀ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₁ Output of (d) and switch K ₁₁ A switch K connected to the first positive terminal ₁₁ Second positive terminal of (a) and switch K ₁₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₁ Is connected with the first negative terminal of the switch K ₁₁ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₂ Output of (d) and switch K ₁₂ A switch K connected to the first positive terminal ₁₂ Second positive terminal of (a) and switch K ₁₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₂ Is connected with the first negative terminal of the switch K ₁₂ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₉ Second positive terminal of (a) switch K ₁₀ Second positive terminal of (a) switch K ₁₁ Second positive terminal of (c) and switch K ₁₂ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₃ And switch K ₉ Is a first negative terminal of switch K ₁₀ Is a first negative terminal of switch K ₁₁ Is connected to the first negative terminal of the switch K ₁₂ Is grounded; output signal O ₃ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit IV includes an inverter INV ₇ -INV ₈ AND gate AND ₁₃ -AND ₁₆ And switch K ₁₃ -K ₁₆ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₃ AND gate AND ₁₄ AND gate AND ₁₅ AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₀ Respectively with inverter INV ₇ AND gate AND ₁₄ AND AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₁ Respectively with inverter INV ₈ AND gate AND ₁₅ AND AND gate AND ₁₆ Is connected with the input end of the inverter INV ₇ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₅ Is connected with the input end of the inverter INV ₈ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₄ Is connected with the input end of the power supply; AND gate AND ₁₃ Output of (d) and switch K ₁₃ A switch K connected to the first positive terminal ₁₃ Second positive terminal of (a) and switch K ₁₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₃ Is connected with the first negative terminal of the switch K ₁₃ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₄ Output of (d) and switch K ₁₄ A switch K connected to the first positive terminal ₁₄ Second positive terminal of (a) and switch K ₁₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₄ Is connected with the first negative terminal of the switch K ₁₄ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₅ Output of (d) and switch K ₁₅ A switch K connected to the first positive terminal ₁₅ Second positive terminal of (a) and switch K ₁₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₅ Is connected with the first negative terminal of the switch K ₁₅ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₆ Output of (d) and switch K ₁₆ Is a first positive electrode of (a)Terminals are connected, switch K ₁₆ Second positive terminal of (a) and switch K ₁₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₆ Is connected with the first negative terminal of the switch K ₁₆ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁₃ Second positive terminal of (a) switch K ₁₄ Second positive terminal of (a) switch K ₁₅ Second positive terminal of (c) and switch K ₁₆ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₄ And switch K ₁₃ Is a first negative terminal of switch K ₁₄ Is a first negative terminal of switch K ₁₅ Is connected to the first negative terminal of the switch K ₁₆ Is grounded; output signal O ₄ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit V includes an inverter INV ₉ -INV ₁₀ AND gate AND ₁₇ -AND ₂₀ And switch K ₁₇ -K ₂₀ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₇ AND gate AND ₁₈ AND gate AND ₁₉ AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₀ Respectively with inverter INV ₉ AND gate AND ₁₈ AND AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₁ Respectively with inverter INV ₁₀ AND gate AND ₁₉ AND AND gate AND ₂₀ Is connected with the input end of the inverter INV ₉ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₉ Is connected with the input end of the inverter INV ₁₀ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₈ Is connected with the input end of the power supply; AND gate AND ₁₇ Output of (d) and switch K ₁₇ A switch K connected to the first positive terminal ₁₇ Second positive terminal of (a) and switch K ₁₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₇ Is connected with the first negative terminal of the switch K ₁₇ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₈ Output of (d) and switch K ₁₈ Is connected to the first positive electrode terminal of (a)Is connected with a switch K ₁₈ Second positive terminal of (a) and switch K ₁₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₈ Is connected with the first negative terminal of the switch K ₁₈ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₉ Output of (d) and switch K ₁₉ A switch K connected to the first positive terminal ₁₉ Second positive terminal of (a) and switch K ₁₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₉ Is connected with the first negative terminal of the switch K ₁₉ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₂₀ Output of (d) and switch K ₂₀ A switch K connected to the first positive terminal ₂₀ Second positive terminal of (a) and switch K ₂₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₀ Is connected with the first negative terminal of the switch K ₂₀ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁₇ Second positive terminal of (a) switch K ₁₈ Second positive terminal of (a) switch K ₁₉ Second positive terminal of (c) and switch K ₂₀ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₅ And switch K ₁₇ Is a first negative terminal of switch K ₁₈ Is a first negative terminal of switch K ₁₉ Is connected to the first negative terminal of the switch K ₂₀ Is grounded; output signal O ₅ And the input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected.

Preferably, the judging module comprises a comparator CP ₁ -CP ₂₄ OR gate OR ₁ -OR ₈ AND AND gate AND ₂₁ -AND ₂₄ The method comprises the steps of carrying out a first treatment on the surface of the Output signal O ₁ Respectively with comparator CP ₁ Comparator CP ₂ And comparator CP ₃ Is connected with the positive input terminal of (1) and outputs a signal O ₂ Respectively with comparator CP ₁ Negative input terminal of (1) comparator CP ₄ Positive input terminal of (1) and comparator CP ₆ Is connected with the positive input terminal of (1) and outputs a signal O ₃ Respectively with comparator CP ₂ Negative input terminal of (c) and comparisonCP device ₄ Negative input terminal of (1) comparator CP ₅ Positive input terminal of (1) and comparator CP ₇ Is connected with the positive input terminal of (1) and outputs a signal O ₄ Respectively with comparator CP ₃ Negative input terminal of (1) comparator CP ₅ Negative input terminal of (1) and comparator CP ₈ Is connected with the positive input terminal of (1) and outputs a signal O ₅ Respectively with comparator CP ₆ Comparator CP ₇ And comparator CP ₈ Is connected with the negative input terminal of the circuit board; comparator CP ₁ Respectively with the comparator CP ₉ Positive input terminal of (1) and comparator CP ₁₀ Is connected to the negative input terminal of the comparator CP ₂ Respectively with the comparator CP ₁₁ Positive input terminal of (1) and comparator CP ₁₂ Is connected to the negative input terminal of the comparator CP ₃ Respectively with the comparator CP ₁₃ Positive input terminal of (1) and comparator CP ₁₄ Is connected to the negative input terminal of the comparator CP ₄ Respectively with the comparator CP ₁₅ Positive input terminal of (1) and comparator CP ₁₆ Is connected to the negative input terminal of the comparator CP ₅ Respectively with the comparator CP ₁₇ Positive input terminal of (1) and comparator CP ₁₈ Is connected to the negative input terminal of the comparator CP ₆ Respectively with the comparator CP ₁₉ Positive input terminal of (1) and comparator CP ₂₀ Is connected to the negative input terminal of the comparator CP ₇ Respectively with the comparator CP ₂₁ Positive input terminal of (1) and comparator CP ₂₂ Is connected to the negative input terminal of the comparator CP ₈ Respectively with the comparator CP ₂₃ Positive input terminal of (1) and comparator CP ₂₄ Is connected to the negative input terminal of the comparator CP ₉ Comparator CP ₁₁ Comparator CP ₁₃ Comparator CP ₁₅ Comparator CP ₁₇ Comparator CP ₁₉ Comparator CP ₂₁ And comparator CP ₂₃ The negative input terminals of (a) are all grounded, comparator CP ₁₀ Comparator CP ₁₂ Comparator CP ₁₄ Comparator CP ₁₆ Comparator CP ₁₈ Comparator CP ₂₀ Comparator CP ₂₂ Ratio ofComparator CP ₂₄ The positive input terminals of the voltage transformer are all grounded; comparator CP ₉ And comparator CP ₁₀ The output terminals of (a) are respectively connected with OR gate OR ₁ Is connected to the input terminal of the comparator CP ₁₁ And comparator CP ₁₂ The output terminals of (a) are respectively connected with OR gate OR ₂ Is connected to the input terminal of the comparator CP ₁₃ And comparator CP ₁₄ The output terminals of (a) are respectively connected with OR gate OR ₃ Is connected to the input terminal of the comparator CP ₁₅ And comparator CP ₁₆ The output terminals of (a) are respectively connected with OR gate OR ₄ Is connected to the input terminal of the comparator CP ₁₇ And comparator CP ₁₈ The output terminals of (a) are respectively connected with OR gate OR ₅ Is connected to the input terminal of the comparator CP ₁₉ And comparator CP ₂₀ The output terminals of (a) are respectively connected with OR gate OR ₆ Is connected to the input terminal of the comparator CP ₂₁ And comparator CP ₂₂ The output terminals of (a) are respectively connected with OR gate OR ₇ Is connected to the input terminal of the comparator CP ₂₃ And comparator CP ₂₄ The output terminals of (a) are respectively connected with OR gate OR ₈ Is connected to the input of OR gate ₁ OR gate OR ₂ OR OR AND gate ₃ The output terminals of (a) are AND-gate with AND gate ₂₁ Is connected to the input of OR gate ₄ OR OR AND gate ₅ The output terminals of (a) are AND-gate with AND gate ₂₂ Is connected to the input of OR gate ₆ OR gate OR ₇ OR OR AND gate ₈ The output terminals of (a) are AND-gate with AND gate ₂₃ Is connected to the input of AND gate ₂₁ AND gate AND ₂₂ AND AND gate AND ₂₃ The output terminals of (a) are AND-gate with AND gate ₂₄ Is connected to the input of AND gate ₂₄ Output signal P of output judging module ₁ Output signal P ₁ Is connected with the input terminal of the retention module.

Preferably, the retention module comprises a switch K ₂₁ -K ₂₅ Output signal P ₁ Respectively with switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is connected to the first positive terminal of (a); switch K ₂₁ Second positive terminal of (a) and switch K ₂₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₁ Second negative terminal of (2) and output signal O ₁ Is connected with a switch K ₂₁ The second positive terminal of (2) outputs the output signal V of the retention module ₁ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₂ Second positive terminal of (a) and switch K ₂₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₂ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₂ The second positive terminal of (2) outputs the output signal V of the retention module ₂ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₃ Second positive terminal of (a) and switch K ₂₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₃ Second negative terminal of (2) and output signal O ₃ Is connected with a switch K ₂₃ The second positive terminal of (2) outputs the output signal V of the retention module ₃ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₄ Second positive terminal of (a) and switch K ₂₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₄ Second negative terminal of (2) and output signal O ₄ Is connected with a switch K ₂₄ The second positive terminal of (2) outputs the output signal V of the retention module ₄ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₅ Second positive terminal of (a) and switch K ₂₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₅ Second negative terminal of (2) and output signal O ₅ Is connected with a switch K ₂₅ The second positive terminal of (2) outputs the output signal V of the retention module ₅ The method comprises the steps of carrying out a first treatment on the surface of the And switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is grounded.

Preferably, the correction module comprises a switch K ₂₆ -K ₃₀ Memristor array and amplifier AM ₁ -AM ₅ Inverter INV ₁₁ -INV ₁₅ And buffer BUF ₁ -BUF ₅ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first positive terminals of the switch K are connected with the power supply voltage ₂₆ Second positive terminal of (a) and switch K ₂₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₆ Is a second negative electrode of (2)Terminal and output signal O ₁ Is connected with a switch K ₂₇ Second positive terminal of (a) and switch K ₂₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₇ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₈ Second positive terminal of (a) and switch K ₂₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₈ Second negative terminal of (2) and output signal O ₃ Is connected with a switch K ₂₉ Second positive terminal of (a) and switch K ₂₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₉ Second negative terminal of (2) and output signal O ₄ Is connected with a switch K ₃₀ Second positive terminal of (a) and switch K ₃₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃₀ Second negative terminal of (2) and output signal O ₅ Is connected with each other; switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first negative terminals of (a) are all grounded, switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The second positive terminals of the memristor array are connected with the input end of the memristor array, and the output end of the memristor array is respectively connected with the amplifier AM ₁ -AM ₅ Is connected to the negative input terminal of the amplifier AM ₁ -AM ₅ The positive input terminals of (a) are all grounded, and the amplifier AM ₁ Negative input terminal of (a) and amplifier AM ₁ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₁ Output terminal of (a) and inverter INV ₁₁ Is connected with the input end of the inverter INV ₁₁ Output of (d) and buffer BUF ₁ Is connected with the negative input terminal of the buffer BUF ₁ Output terminal of the output correction module outputs an output signal V ₆ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₂ Negative input terminal of (a) and amplifier AM ₂ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₂ Output terminal of (a) and inverter INV ₁₂ Is connected with the input end of the inverter INV ₁₂ Output of (d) and buffer BUF ₂ Is connected with the negative input terminal of the bufferBUF ₂ Output terminal of the output correction module outputs an output signal V ₇ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₃ Negative input terminal of (a) and amplifier AM ₃ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₃ Output terminal of (a) and inverter INV ₁₃ Is connected with the input end of the inverter INV ₁₃ Output of (d) and buffer BUF ₃ Is connected with the negative input terminal of the buffer BUF ₃ Output terminal of the output correction module outputs an output signal V ₈ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₄ Negative input terminal of (a) and amplifier AM ₄ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₄ Output terminal of (a) and inverter INV ₁₄ Is connected with the input end of the inverter INV ₁₄ Output of (d) and buffer BUF ₄ Is connected with the negative input terminal of the buffer BUF ₄ Output terminal of the output correction module outputs an output signal V ₉ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₅ Negative input terminal of (a) and amplifier AM ₅ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₅ Output terminal of (a) and inverter INV ₁₅ Is connected with the input end of the inverter INV ₁₅ Output of (d) and buffer BUF ₅ Is connected with the negative input terminal of the buffer BUF ₅ Output terminal of the output correction module outputs an output signal V ₁₀ The method comprises the steps of carrying out a first treatment on the surface of the Buffer BUF ₁ -BUF ₅ The positive input terminals of (a) are all grounded.

Preferably, the memristive array includes memristance M ₁ -M ₂₅ Memristor M ₁ Memristor M ₆ Memristor M ₁₁ Memristor M ₁₆ And memristance M ₂₁ The input ends of the (C) are connected with the switch K ₂₆ Is connected with the second positive terminal of the memristor M ₂ Memristor M ₇ Memristor M ₁₂ Memristor M ₁₇ And memristance M ₂₂ The input ends of the (C) are connected with the switch K ₂₇ Is connected with the second positive terminal of the memristor M ₃ Memristor M ₈ Memristor M ₁₃ Memristor M ₁₈ And memristance M ₂₃ The input ends of the (C) are connected with the switch K ₂₈ Is connected with the second positive terminal of the memristor M ₄ Memristor M ₉ Memristor M ₁₄ MemristorM ₁₉ And memristance M ₂₄ The input ends of the (C) are connected with the switch K ₂₉ Is connected with the second positive terminal of the memristor M ₅ Memristor M ₁₀ Memristor M ₁₅ Memristor M ₂₀ And memristance M ₂₅ The input ends of the (C) are connected with the switch K ₃₀ Is connected with the second positive terminal of the memristor M ₁ -M ₅ Are connected with the output end of the amplifier AM ₁ Is connected with the negative input terminal of the memristor M ₆ -M ₁₀ Are connected with the output end of the amplifier AM ₂ Is connected with the negative input terminal of the memristor M ₁₁ -M ₁₅ Are connected with the output end of the amplifier AM ₃ Is connected with the negative input terminal of the memristor M ₁₆ -M ₂₀ Are connected with the output end of the amplifier AM ₄ Is connected with the negative input terminal of the memristor M ₂₁ -M ₂₅ Are connected with the output end of the amplifier AM ₅ Is connected to the negative input terminal of (c).

Compared with the prior art, the invention has the beneficial effects that: the invention constructs an input module circuit, a judging module circuit, a retaining module circuit and a correcting module circuit, builds a four-color guessing circuit based on a memristive neural network, realizes the four-coloring function of five areas, and solves the problem that the four-color guessing circuit is difficult to realize by a hardware circuit; the memristor neural network has strong inclusion, can flexibly build a circuit according to task requirements, and provides reference for more complex circuit design.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of five zones of the present invention.

Fig. 2 is a circuit diagram of an input module of the present invention.

Fig. 3 is a circuit diagram of a judging module according to the present invention.

Fig. 4 is a circuit diagram of a retention module according to the present invention.

FIG. 5 is a circuit diagram of a calibration module according to the present invention.

FIG. 6 is a four-color guess circuit based on memristive neural network of the present disclosure.

Fig. 7 is a diagram of an input signal of the present invention.

Fig. 8 is a simulation diagram of an input module of the present invention.

Fig. 9 is a simulation diagram of the judging module and the retaining module of the present invention.

Fig. 10 is a simulation diagram of a correction module of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 6, the embodiment of the invention provides a four-color guess circuit based on a memristive neural network, which comprises an input module, a judging module, a retaining module and a correcting module, wherein an input terminal of the input module is respectively connected with a Q terminal and a digital signal terminal, an output terminal of the input module is respectively connected with an input terminal of the judging module, an input terminal of the retaining module and an input terminal of the correcting module, an output terminal of the judging module is connected with an input terminal of the retaining module, and an output terminal of the retaining module and an output terminal of the correcting module output signals of the four-color guess circuit. The input module comprises five signal processing units, the output of each signal processing unit represents coloring of an area, the input module converts logic signals into analog voltages of 1-4V, red, yellow, blue and green colors are distinguished by different voltage levels, the judging module judges whether coloring of the five areas accords with four-color guesses (the same coloring cannot occur in countries with the same boundary), if the coloring accords with the four-color guesses, the retaining module directly outputs a correct result, if the coloring does not accord with the four-color guesses, the output result of the retaining module is zero, and the correction module converges all conditions into a correct result.

As shown in fig. 1, the schematic diagram is divided into five areas, the five areas of the common boundary are differently colored by four colors, and the four colors for coloring a certain area are assumed to be red, yellow, blue and green respectively, and are represented by different voltage levels. Let 1V voltage represent red, 2V voltage represent yellow, 3V voltage represent blue, and 4V voltage represent green. Each region is marked with the numbers "1", "2", "3", "4", and adjacent regions are unlikely to be given the same number.

As shown in fig. 2, the input module converts the digital logic signal into a voltage of 1-4V, and distinguishes four different colors with different voltage levels. The input module comprises a signal processing unit I, a signal processing unit II, a signal processing unit III, a signal processing unit IV and a signal processing unit V; the input terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V respectively comprise a first input terminal, a second input terminal and a third input terminal, the first input terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are respectively connected with the Q terminal, and the second input terminal of the signal processing unit I is connected with the digital signal terminal A ₀ A third input terminal of the signal processing unit I is connected with the digital signal terminal A ₁ A second input terminal of the signal processing unit II is connected with the digital signal terminal B ₀ Is connected with the third input terminal of the signal processing unit II and the digital signal terminal B ₁ A second input terminal of the signal processing unit III is connected with the digital signal terminal C ₀ Is connected with the third input terminal of the signal processing unit III and the digital signal terminal C ₁ A second input terminal of the signal processing unit IV is connected with the digital signal terminal D ₀ Is connected with the third input terminal of the signal processing unit IV and the digital signal terminal D ₁ A second input terminal of the signal processing unit V is connected with the digital signalNumber terminal E ₀ A third input terminal of the signal processing unit V is connected with the digital signal terminal E ₁ Is connected with each other; the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the judging module, the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the retaining module, and the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the correcting module.

The signal processing unit I comprises an inverter INV ₁ -INV ₂ AND gate AND ₁ -AND ₄ And switch K ₁ -K ₄ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁ AND gate AND ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₀ Respectively with inverter INV ₁ AND gate AND ₂ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₁ Respectively with inverter INV ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the inverter INV ₁ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₃ Is connected with the input end of the inverter INV ₂ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₂ Is connected with the input end of the power supply; AND gate AND ₁ Output of (d) and switch K ₁ A switch K connected to the first positive terminal ₁ Second positive terminal of (a) and switch K ₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁ Is connected with the first negative terminal of the switch K ₁ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₂ Output of (d) and switch K ₂ A switch K connected to the first positive terminal ₂ Second positive terminal of (a) and switch K ₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂ Is connected with the first negative terminal of the switch K ₂ Is the second one of (2)A voltage source II is connected between the negative terminals; AND gate AND ₃ Output of (d) and switch K ₃ A switch K connected to the first positive terminal ₃ Second positive terminal of (a) and switch K ₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃ Is connected with the first negative terminal of the switch K ₃ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₄ Output of (d) and switch K ₄ A switch K connected to the first positive terminal ₄ Second positive terminal of (a) and switch K ₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₄ Is connected with the first negative terminal of the switch K ₄ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁ Second positive terminal of (a) switch K ₂ Second positive terminal of (a) switch K ₃ Second positive terminal of (c) and switch K ₄ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₁ And switch K ₁ Is a first negative terminal of switch K ₂ Is a first negative terminal of switch K ₃ Is connected to the first negative terminal of the switch K ₄ Is grounded; output signal O ₁ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected; the voltage of the voltage source I is 1V, the voltage of the voltage source II is 2V, the voltage of the voltage source III is 3V, and the voltage of the voltage source IV is 4V.

In the signal processing unit I, A ₁ A ₀ The output signals of (a) are respectively in four cases of '00', '01', '10', '11', and the Q terminal always outputs high voltage. When A is ₁ A ₀ When "00". At this time, AND ₁ And outputting high voltage and the rest is low voltage. At this time switch K ₁ Conduction, K ₁ The output voltage of (2) is 1V, and the other switches are all 0V, the output terminal O ₁ 1V, i.e. the area is coloured red; when A is ₁ A ₀ When the value is "01", AND gate AND is formed at the moment ₂ Outputs high voltage, the rest are low voltage, K ₂ Conduction, K ₂ Output voltage of 2V, output terminal O ₁ Is 2V, i.e. regional colorationYellow; when A is ₁ A ₀ When it is 10, AND gate AND is used ₃ Outputs high voltage, the rest are low voltage, K ₃ Conduction, K ₃ Output voltage of 3V, output terminal O ₁ Is 3V, i.e. the area is coloured blue; when A is ₁ A ₀ When it is "11", AND gate AND is used ₄ Outputs high voltage, the rest are low voltage, K ₄ Conduction, K ₄ Output voltage of 4V, output terminal O ₁ Is 4V, i.e. the area is coloured green. The principle of the remaining four signal processing units is similar to that of the signal processing unit I.

The signal processing unit II comprises an inverter INV ₃ -INV ₄ AND gate AND ₅ -AND ₈ And switch K ₅ -K ₈ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₅ AND gate AND ₆ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₀ Respectively with inverter INV ₃ AND gate AND ₆ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₁ Respectively with inverter INV ₄ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the inverter INV ₃ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₇ Is connected with the input end of the inverter INV ₄ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₆ Is connected with the input end of the power supply; AND gate AND ₅ Output of (d) and switch K ₅ A switch K connected to the first positive terminal ₅ Second positive terminal of (a) and switch K ₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₅ Is connected with the first negative terminal of the switch K ₅ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₆ Output of (d) and switch K ₆ A switch K connected to the first positive terminal ₆ Second positive terminal of (a) and switch K ₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₆ Is connected with the first negative terminal of the switch K ₆ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₇ Output of (d) and switch K ₇ A switch K connected to the first positive terminal ₇ Second positive terminal of (a) and switch K ₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₇ Is connected with the first negative terminal of the switch K ₇ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₈ Output of (d) and switch K ₈ A switch K connected to the first positive terminal ₈ Second positive terminal of (a) and switch K ₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₈ Is connected with the first negative terminal of the switch K ₈ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₅ Second positive terminal of (a) switch K ₆ Second positive terminal of (a) switch K ₇ Second positive terminal of (c) and switch K ₈ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₂ And switch K ₅ Is a first negative terminal of switch K ₆ Is a first negative terminal of switch K ₇ Is connected to the first negative terminal of the switch K ₈ Is grounded; output signal O ₂ And the input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected.

The signal processing unit III comprises an inverter INV ₅ -INV ₆ AND gate AND ₉ -AND ₁₂ And switch K ₉ -K ₁₂ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₉ AND gate AND ₁₀ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the digital signal terminal C ₀ Respectively with inverter INV ₅ AND gate AND ₁₀ AND AND gate AND ₁₂ Is connected with the input end of the digital signal terminal C ₁ Respectively with inverter INV ₆ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the inverter INV ₅ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₁ Is connected with the input end of the inverter INV ₆ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₀ Is connected with the input end of the power supply; AND gate AND ₉ Output of (d) and switch K ₉ A switch K connected to the first positive terminal ₉ Second positive terminal of (a) and switch K ₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₉ Is connected with the first negative terminal of the switch K ₉ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₀ Output of (d) and switch K ₁₀ A switch K connected to the first positive terminal ₁₀ Second positive terminal of (a) and switch K ₁₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₀ Is connected with the first negative terminal of the switch K ₁₀ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₁ Output of (d) and switch K ₁₁ A switch K connected to the first positive terminal ₁₁ Second positive terminal of (a) and switch K ₁₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₁ Is connected with the first negative terminal of the switch K ₁₁ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₂ Output of (d) and switch K ₁₂ A switch K connected to the first positive terminal ₁₂ Second positive terminal of (a) and switch K ₁₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₂ Is connected with the first negative terminal of the switch K ₁₂ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₉ Second positive terminal of (a) switch K ₁₀ Second positive terminal of (a) switch K ₁₁ Second positive terminal of (c) and switch K ₁₂ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₃ And switch K ₉ Is a first negative terminal of switch K ₁₀ Is a first negative terminal of switch K ₁₁ Is connected to the first negative terminal of the switch K ₁₂ Is grounded; output signal O ₃ And the input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected.

The signal processing unit IV includes an inverter INV ₇ -INV ₈ AND gate AND ₁₃ -AND ₁₆ And switch K ₁₃ -K ₁₆ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₃ AND gate AND ₁₄ AND gate AND ₁₅ AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₀ Respectively with inverter INV ₇ AND gate AND ₁₄ AND AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₁ Respectively with inverter INV ₈ AND gate AND ₁₅ AND AND gate AND ₁₆ Is connected with the input end of the inverter INV ₇ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₅ Is connected with the input end of the inverter INV ₈ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₄ Is connected with the input end of the power supply; AND gate AND ₁₃ Output of (d) and switch K ₁₃ A switch K connected to the first positive terminal ₁₃ Second positive terminal of (a) and switch K ₁₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₃ Is connected with the first negative terminal of the switch K ₁₃ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₄ Output of (d) and switch K ₁₄ A switch K connected to the first positive terminal ₁₄ Second positive terminal of (a) and switch K ₁₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₄ Is connected with the first negative terminal of the switch K ₁₄ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₅ Output of (d) and switch K ₁₅ A switch K connected to the first positive terminal ₁₅ Second positive terminal of (a) and switch K ₁₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₅ Is connected with the first negative terminal of the switch K ₁₅ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₆ Output of (d) and switch K ₁₆ A switch K connected to the first positive terminal ₁₆ Second positive terminal of (a) and switch K ₁₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₆ Is connected with the first negative terminal of the switch K ₁₆ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁₃ Second positive terminal of (a) switch K ₁₄ Second positive terminal of (a) switch K ₁₅ Second positive terminal of (c) and switch K ₁₆ Is the first of (2)The two positive terminals are overlapped by a summation element to obtain an output signal O ₄ And switch K ₁₃ Is a first negative terminal of switch K ₁₄ Is a first negative terminal of switch K ₁₅ Is connected to the first negative terminal of the switch K ₁₆ Is grounded; output signal O ₄ And the input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected.

The signal processing unit V includes an inverter INV ₉ -INV ₁₀ AND gate AND ₁₇ -AND ₂₀ And switch K ₁₇ -K ₂₀ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₇ AND gate AND ₁₈ AND gate AND ₁₉ AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₀ Respectively with inverter INV ₉ AND gate AND ₁₈ AND AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₁ Respectively with inverter INV ₁₀ AND gate AND ₁₉ AND AND gate AND ₂₀ Is connected with the input end of the inverter INV ₉ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₉ Is connected with the input end of the inverter INV ₁₀ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₈ Is connected with the input end of the power supply; AND gate AND ₁₇ Output of (d) and switch K ₁₇ A switch K connected to the first positive terminal ₁₇ Second positive terminal of (a) and switch K ₁₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₇ Is connected with the first negative terminal of the switch K ₁₇ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₈ Output of (d) and switch K ₁₈ A switch K connected to the first positive terminal ₁₈ Second positive terminal of (a) and switch K ₁₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₈ Is connected with the first negative terminal of the switch K ₁₈ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₉ Output of (d) and switch K ₁₉ A switch K connected to the first positive terminal ₁₉ Second positive terminal of (a) and switch K ₁₉ Is the first of (1)A resistor R is connected between the negative terminals ₁ Switch K ₁₉ Is connected with the first negative terminal of the switch K ₁₉ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₂₀ Output of (d) and switch K ₂₀ A switch K connected to the first positive terminal ₂₀ Second positive terminal of (a) and switch K ₂₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₀ Is connected with the first negative terminal of the switch K ₂₀ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁₇ Second positive terminal of (a) switch K ₁₈ Second positive terminal of (a) switch K ₁₉ Second positive terminal of (c) and switch K ₂₀ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₅ And switch K ₁₇ Is a first negative terminal of switch K ₁₈ Is a first negative terminal of switch K ₁₉ Is connected to the first negative terminal of the switch K ₂₀ Is grounded; output signal O ₅ And the input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected.

As shown in fig. 3, the input signal of the judgment module circuit is the output signal of the input module, the output signal is P ₁ And (3) representing. The judging module judges whether the four-color conjecture is met by comparing whether adjacent coloring is consistent, if the four-color conjecture is met, the judging module outputs a high level, if the four-color conjecture is not met, the judging module outputs a low level, the judging module is provided with five input terminals and one output terminal, five input signals of the judging module are five output signals of the input module, the judging module consists of twenty-four comparators, eight OR gates and four AND gates, and in order to realize that each two adjacent areas can be compared once, and the judging module needs to make eight comparisons by combining position information. The judging module comprises a comparator CP ₁ -CP ₂₄ OR gate OR ₁ -OR ₈ AND AND gate AND ₂₁ -AND ₂₄ The method comprises the steps of carrying out a first treatment on the surface of the Output signal O ₁ Respectively with comparator CP ₁ Comparator CP ₂ And comparator CP ₃ Is connected with the positive input terminal of (1) and outputs a signal O ₂ Respectively with comparator CP ₁ Is the negative input of (2)Input terminal, comparator CP ₄ Positive input terminal of (1) and comparator CP ₆ Is connected with the positive input terminal of (1) and outputs a signal O ₃ Respectively with comparator CP ₂ Negative input terminal of (1) comparator CP ₄ Negative input terminal of (1) comparator CP ₅ Positive input terminal of (1) and comparator CP ₇ Is connected with the positive input terminal of (1) and outputs a signal O ₄ Respectively with comparator CP ₃ Negative input terminal of (1) comparator CP ₅ Negative input terminal of (1) and comparator CP ₈ Is connected with the positive input terminal of (1) and outputs a signal O ₅ Respectively with comparator CP ₆ Comparator CP ₇ And comparator CP ₈ Is connected with the negative input terminal of the circuit board; comparator CP ₁ Respectively with the comparator CP ₉ Positive input terminal of (1) and comparator CP ₁₀ Is connected to the negative input terminal of the comparator CP ₂ Respectively with the comparator CP ₁₁ Positive input terminal of (1) and comparator CP ₁₂ Is connected to the negative input terminal of the comparator CP ₃ Respectively with the comparator CP ₁₃ Positive input terminal of (1) and comparator CP ₁₄ Is connected to the negative input terminal of the comparator CP ₄ Respectively with the comparator CP ₁₅ Positive input terminal of (1) and comparator CP ₁₆ Is connected to the negative input terminal of the comparator CP ₅ Respectively with the comparator CP ₁₇ Positive input terminal of (1) and comparator CP ₁₈ Is connected to the negative input terminal of the comparator CP ₆ Respectively with the comparator CP ₁₉ Positive input terminal of (1) and comparator CP ₂₀ Is connected to the negative input terminal of the comparator CP ₇ Respectively with the comparator CP ₂₁ Positive input terminal of (1) and comparator CP ₂₂ Is connected to the negative input terminal of the comparator CP ₈ Respectively with the comparator CP ₂₃ Positive input terminal of (1) and comparator CP ₂₄ Is connected to the negative input terminal of the comparator CP ₉ Comparator CP ₁₁ Comparator CP ₁₃ Comparator CP ₁₅ Comparator CP ₁₇ Comparator CP ₁₉ Comparator CP ₂₁ And comparator CP ₂₃ The negative input terminals of (2) are all groundedComparator CP ₁₀ Comparator CP ₁₂ Comparator CP ₁₄ Comparator CP ₁₆ Comparator CP ₁₈ Comparator CP ₂₀ Comparator CP ₂₂ Comparator CP ₂₄ The positive input terminals of the voltage transformer are all grounded; comparator CP ₉ And comparator CP ₁₀ The output terminals of (a) are respectively connected with OR gate OR ₁ Is connected to the input terminal of the comparator CP ₁₁ And comparator CP ₁₂ The output terminals of (a) are respectively connected with OR gate OR ₂ Is connected to the input terminal of the comparator CP ₁₃ And comparator CP ₁₄ The output terminals of (a) are respectively connected with OR gate OR ₃ Is connected to the input terminal of the comparator CP ₁₅ And comparator CP ₁₆ The output terminals of (a) are respectively connected with OR gate OR ₄ Is connected to the input terminal of the comparator CP ₁₇ And comparator CP ₁₈ The output terminals of (a) are respectively connected with OR gate OR ₅ Is connected to the input terminal of the comparator CP ₁₉ And comparator CP ₂₀ The output terminals of (a) are respectively connected with OR gate OR ₆ Is connected to the input terminal of the comparator CP ₂₁ And comparator CP ₂₂ The output terminals of (a) are respectively connected with OR gate OR ₇ Is connected to the input terminal of the comparator CP ₂₃ And comparator CP ₂₄ The output terminals of (a) are respectively connected with OR gate OR ₈ Is connected to the input of OR gate ₁ OR gate OR ₂ OR OR AND gate ₃ The output terminals of (a) are AND-gate with AND gate ₂₁ Is connected to the input of OR gate ₄ OR OR AND gate ₅ The output terminals of (a) are AND-gate with AND gate ₂₂ Is connected to the input of OR gate ₆ OR gate OR ₇ OR OR AND gate ₈ The output terminals of (a) are AND-gate with AND gate ₂₃ Is connected to the input of AND gate ₂₁ AND gate AND ₂₂ AND AND gate AND ₂₃ The output terminals of (a) are AND-gate with AND gate ₂₄ Is connected to the input of AND gate ₂₄ Output signal P of output judging module ₁ Output signal P ₁ Is connected with the input terminal of the retention module. If P ₁ Outputting high voltage, and indicating that the repeated coloring of the adjacent areas does not occur; if P ₁ And outputting low voltage to show that the adjacent areas are repeatedly colored.

As shown in FIG. 4, the reservation module can accurately screen out fiveThe area meets the result of four-color guess, the implementation of the reservation module needs to be based on a judgment module, in the judgment module, only the four-color guess is met, the high level can be output, the condition of the action of the switching element is that a high level is input to the left positive electrode to form a differential pressure, based on the principle, the judgment module judges whether the coloring of five areas meets the four-color guess, if the coloring meets the four-color guess, the reservation module directly outputs the correct result, and if the coloring does not meet the four-color guess, the output result of the reservation module is zero. The retention module comprises a switch K ₂₁ -K ₂₅ Output signal P ₁ Respectively with switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is connected to the first positive terminal of (a); switch K ₂₁ Second positive terminal of (a) and switch K ₂₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₁ Second negative terminal of (2) and output signal O ₁ Is connected with a switch K ₂₁ The second positive terminal of (2) outputs the output signal V of the retention module ₁ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₂ Second positive terminal of (a) and switch K ₂₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₂ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₂ The second positive terminal of (2) outputs the output signal V of the retention module ₂ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₃ Second positive terminal of (a) and switch K ₂₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₃ Second negative terminal of (2) and output signal O ₃ Is connected with a switch K ₂₃ The second positive terminal of (2) outputs the output signal V of the retention module ₃ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₄ Second positive terminal of (a) and switch K ₂₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₄ Second negative terminal of (2) and output signal O ₄ Is connected with a switch K ₂₄ The second positive terminal of (2) outputs the output signal V of the retention module ₄ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₅ Second positive terminal of (a) and switch K ₂₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₅ Second negative terminal of (2) and output signal O ₅ Is connected with a switch K ₂₅ The second positive terminal of (2) outputs the output signal V of the retention module ₅ The method comprises the steps of carrying out a first treatment on the surface of the And switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is grounded. The implementation of the judgment module is the basis for the design of the reserved module. When P ₁ At high voltage, switch K ₂₁ -K ₂₅ On, when four colors are hypothesized to be satisfied, O ₁ -O ₅ Can be accessed, the original signal can be preserved, and the output signal V ₁ -V ₅ And input signal O ₁ -O ₅ The same applies. Conversely, when P ₁ At low voltage, switch K ₂₁ -K ₂₅ Is not conductive and outputs a signal V ₁ -V ₅ The output of (2) is 0V.

As shown in FIG. 5, when the map of five areas is colored, if each area is marked with the number 1-4, only 72 cases of satisfying the four-color guess are needed, and most cases do not satisfy the four-color guess. The correction module is designed to modify cases that do not meet the four-color guess specifications, so that the cases can meet the four-color guess after correction. The correction module comprises a switch K ₂₆ -K ₃₀ Memristor array and amplifier AM ₁ -AM ₅ Inverter INV ₁₁ -INV ₁₅ And buffer BUF ₁ -BUF ₅ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first positive terminals of the switch K are connected with the power supply voltage ₂₆ Second positive terminal of (a) and switch K ₂₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₆ Second negative terminal of (2) and output signal O ₁ Is connected with a switch K ₂₇ Second positive terminal of (a) and switch K ₂₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₇ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₈ Second positive terminal of (a) and switch K ₂₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₈ Is connected with the second negative terminal of the batteryOutput signal O ₃ Is connected with a switch K ₂₉ Second positive terminal of (a) and switch K ₂₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₉ Second negative terminal of (2) and output signal O ₄ Is connected with a switch K ₃₀ Second positive terminal of (a) and switch K ₃₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃₀ Second negative terminal of (2) and output signal O ₅ Is connected with each other; switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first negative terminals of (a) are all grounded, switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The second positive terminals of the memristor array are connected with the input end of the memristor array, and the output end of the memristor array is respectively connected with the amplifier AM ₁ -AM ₅ Is connected to the negative input terminal of the amplifier AM ₁ -AM ₅ The positive input terminals of (a) are all grounded, and the amplifier AM ₁ Negative input terminal of (a) and amplifier AM ₁ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₁ Output terminal of (a) and inverter INV ₁₁ Is connected with the input end of the inverter INV ₁₁ Output of (d) and buffer BUF ₁ Is connected with the negative input terminal of the buffer BUF ₁ Output terminal of the output correction module outputs an output signal V ₆ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₂ Negative input terminal of (a) and amplifier AM ₂ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₂ Output terminal of (a) and inverter INV ₁₂ Is connected with the input end of the inverter INV ₁₂ Output of (d) and buffer BUF ₂ Is connected with the negative input terminal of the buffer BUF ₂ Output terminal of the output correction module outputs an output signal V ₇ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₃ Negative input terminal of (a) and amplifier AM ₃ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₃ Output terminal of (a) and inverter INV ₁₃ Is connected with the input end of the inverter INV ₁₃ Output of (d) and buffer BUF ₃ Is connected with the negative input terminal of the buffer BUF ₃ Output terminal of (2)Output signal V of sub-output correction module ₈ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₄ Negative input terminal of (a) and amplifier AM ₄ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₄ Output terminal of (a) and inverter INV ₁₄ Is connected with the input end of the inverter INV ₁₄ Output of (d) and buffer BUF ₄ Is connected with the negative input terminal of the buffer BUF ₄ Output terminal of the output correction module outputs an output signal V ₉ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₅ Negative input terminal of (a) and amplifier AM ₅ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₅ Output terminal of (a) and inverter INV ₁₅ Is connected with the input end of the inverter INV ₁₅ Output of (d) and buffer BUF ₅ Is connected with the negative input terminal of the buffer BUF ₅ Output terminal of the output correction module outputs an output signal V ₁₀ The method comprises the steps of carrying out a first treatment on the surface of the Buffer BUF ₁ -BUF ₅ The positive input terminals of (a) are all grounded.

The memristive array includes memristances M ₁ -M ₂₅ Memristor M ₁ Memristor M ₆ Memristor M ₁₁ Memristor M ₁₆ And memristance M ₂₁ The input ends of the (C) are connected with the switch K ₂₆ Is connected with the second positive terminal of the memristor M ₂ Memristor M ₇ Memristor M ₁₂ Memristor M ₁₇ And memristance M ₂₂ The input ends of the (C) are connected with the switch K ₂₇ Is connected with the second positive terminal of the memristor M ₃ Memristor M ₈ Memristor M ₁₃ Memristor M ₁₈ And memristance M ₂₃ The input ends of the (C) are connected with the switch K ₂₈ Is connected with the second positive terminal of the memristor M ₄ Memristor M ₉ Memristor M ₁₄ Memristor M ₁₉ And memristance M ₂₄ The input ends of the (C) are connected with the switch K ₂₉ Is connected with the second positive terminal of the memristor M ₅ Memristor M ₁₀ Memristor M ₁₅ Memristor M ₂₀ And memristance M ₂₅ The input ends of the (C) are connected with the switch K ₃₀ Is connected with the second positive terminal of the memristor M ₁ -M ₅ Are connected with the output end of the amplifier AM ₁ Is connected with the negative input terminal of the memristor M ₆ -M ₁₀ Are connected with the output end of the amplifier AM ₂ Is connected with the negative input terminal of the memristor M ₁₁ -M ₁₅ Are connected with the output end of the amplifier AM ₃ Is connected with the negative input terminal of the memristor M ₁₆ -M ₂₀ Are connected with the output end of the amplifier AM ₄ Is connected with the negative input terminal of the memristor M ₂₁ -M ₂₅ Are connected with the output end of the amplifier AM ₅ Is connected to the negative input terminal of (c).

As shown in FIG. 6, the input signal of the four-color guess complete circuit based on the memristive neural network is the input signal of the input module, and the output signal is V ₁ -V ₁₀ . The input signal is firstly converted into an analog signal by the input module, and each signal processing unit can obtain 1-4V voltage so as to represent four colors of red, yellow, blue and green. The judging module receives the output signal of the input module to judge, and if the output of the judging module is high voltage, the judging module accords with the four-color conjecture; if the output is low, the four-color guess is not met. The input signals of the retaining module are in one-to-one correspondence connection with the output signals of the judging module, and when the judging module outputs high voltage, the retaining module retains the original output signals of the input module. When the judging module outputs low voltage, the output signals of the retaining module are all zero. The correction module is able to translate all of the input signals to the correct condition of the four-color hypothesis.

As shown in FIG. 7, the logic signals of the input module are 2 in total ² ×2 ² ×2 ² ×2 ² ×2 ² Since 1024 cases cannot be listed in total in the present invention, only some cases are listed in the simulation. The input signals of the input module represent an input condition every second. In FIG. 7, Q is always high voltage, A ₁ A ₀ ，B ₁ B ₀ ，C ₁ C ₀ ，D ₁ D ₀ ，E ₁ E ₀ Respectively, logical input signals controlling the coloring of the five regions. For example, at 0-1s, A ₁ A ₀ The input signal of the terminal is '00', and the output of the prediction signal processing unit I is 1V, and the color of the area I is red; b (B) ₁ B ₀ The input signal of the terminal is '01'The output of the second prediction signal processing unit is 2V, and the color of the second region is yellow; c (C) ₁ C ₀ The input signal of the terminal is 10, the three outputs of the prediction signal processing unit are 3V, and the three colors of the region are blue; d (D) ₁ D ₀ The input signal of the terminal is '01', the output of the prediction signal processing unit is 2V, and the color of the area four is yellow; e (E) ₁ E ₀ The input signal of the terminal is "11", and the prediction signal processing unit five outputs 4V, and the region five colors are green. At 1-36s, the principle is similar.

As shown in FIG. 8, the input modules described, at 0-36s, total 36 cases. At 0-1s, O ₁ The output signal of (2) is 1V, indicating that the coloration of region 1 is red. O (O) ₂ The output signal of (2) is 2V, indicating that the coloration of region 2 is yellow. O (O) ₃ The output signal of (2) is 3V, indicating that the coloration of region 3 is blue. O (O) ₄ The output signal of (2) is 2V, indicating that the coloration of region 4 is yellow. O (O) ₅ The output signal of (2) is 4V, indicating that the coloration of region 5 is green, so at 0-1s, five regions are colored red-yellow-blue-yellow-green, the same as the predicted result and satisfying the four-color hypothesis. At 1-36s, the analysis principle is similar to that, and there are 35 cases.

As shown in fig. 9, in the judging module and the reserving module, P ₁ For judging the output signal of the module, P is determined when the simulation result is 0-31s ₁ The output signal of (2) is always high, indicating that the input conditions of 0-31s all meet four-color guesses. And at 31-36s P ₁ The output signal of (2) is always low, indicating that none of the 31-36s input conditions meet the four-color hypothesis. Retaining simulation results of modules, e.g. V ₁ -V ₅ As shown, the simulation results show that the output signal has a voltage value when in the range of 0-31s, and the output analog voltage meeting the four-color guess is reserved. At 31-36s, the output signals are all zero, indicating that the retention module does not retain the output analog voltages that do not meet the four-color guess.

As shown in FIG. 10, a four-color guess circuit based on memristive neural network is characterized in that the simulation result of the correction module is that, because of the more input conditions of five-area coloring, only 72 conditions of four-color guess are satisfied, and the correction module is designed for correcting the conditions that the four-color guess is not satisfied. Simulation results of the correction module show that there are voltage outputs at 0-36s and are converged to four results of "42324", "42321", "12324" and "12321", for example, 0-6s,8-15s,16-19s,20-26s,28-31s and 35-36s are converged to "42324", i.e., five areas are colored to "green-yellow-blue-yellow-green"; the colors at 6-7s,15-16s,19-20s and 32-33s all converged to "12321", i.e., five areas were colored "red Huang Lanhuang red"; the color of five areas is "red, yellow, blue, yellow and green" after the convergence of "12324" at 7-8s,26-28s and 34-35 s; the color of five areas is "green yellow blue yellow red" which converges to "42321" at 31-32s and 33-34 s. All four conditions conform to a four-color hypothesis.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims (1)

1. The four-color guess circuit based on the memristive neural network is characterized by comprising an input module, a judging module, a retaining module and a correcting module, wherein an input terminal of the input module is respectively connected with a Q terminal and a digital signal terminal, an output terminal of the input module is respectively connected with an input terminal of the judging module, an input terminal of the retaining module and an input terminal of the correcting module, an output terminal of the judging module is connected with an input terminal of the retaining module, and an output terminal of the retaining module and an output terminal of the correcting module output signals of the four-color guess circuit;

the input module comprises a signal processing unit I, a signal processing unit II, a signal processing unit III, a signal processing unit IV and a signal processing unit V; the input terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V comprise a first input terminal, a second input terminal and a third input terminal, and the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V The first input terminals of the units V are connected with the Q terminal, the second input terminal of the signal processing unit I is connected with the digital signal terminal A ₀ A third input terminal of the signal processing unit I is connected with the digital signal terminal A ₁ A second input terminal of the signal processing unit II is connected with the digital signal terminal B ₀ Is connected with the third input terminal of the signal processing unit II and the digital signal terminal B ₁ A second input terminal of the signal processing unit III is connected with the digital signal terminal C ₀ Is connected with the third input terminal of the signal processing unit III and the digital signal terminal C ₁ A second input terminal of the signal processing unit IV is connected with the digital signal terminal D ₀ Is connected with the third input terminal of the signal processing unit IV and the digital signal terminal D ₁ A second input terminal of the signal processing unit V is connected with the digital signal terminal E ₀ A third input terminal of the signal processing unit V is connected with the digital signal terminal E ₁ Is connected with each other; the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the judging module, the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the retaining module, and the output terminals of the signal processing unit I, the signal processing unit II, the signal processing unit III, the signal processing unit IV and the signal processing unit V are all connected with the input terminal of the correcting module;

The signal processing unit I comprises an inverter INV ₁ -INV ₂ AND gate AND ₁ -AND ₄ And switch K ₁ -K ₄ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁ AND gate AND ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₀ Respectively with inverter INV ₁ AND gate AND ₂ AND AND gate AND ₄ Is connected with the input end of the digital signal terminal A ₁ Respectively with inverter INV ₂ AND gate AND ₃ AND AND gate AND ₄ Is connected with the input end of the inverter INV ₁ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₃ Is connected with the input end of the inverter INV ₂ Respectively AND the output ends of (a) with AND gates ₁ AND gate AND ₂ Is connected with the input end of the power supply; AND gate AND ₁ Output of (d) and switch K ₁ A switch K connected to the first positive terminal ₁ Second positive terminal of (a) and switch K ₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁ Is connected with the first negative terminal of the switch K ₁ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₂ Output of (d) and switch K ₂ A switch K connected to the first positive terminal ₂ Second positive terminal of (a) and switch K ₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂ Is connected with the first negative terminal of the switch K ₂ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₃ Output of (d) and switch K ₃ A switch K connected to the first positive terminal ₃ Second positive terminal of (a) and switch K ₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃ Is connected with the first negative terminal of the switch K ₃ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₄ Output of (d) and switch K ₄ A switch K connected to the first positive terminal ₄ Second positive terminal of (a) and switch K ₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₄ Is connected with the first negative terminal of the switch K ₄ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁ Second positive terminal of (a) switch K ₂ Second positive terminal of (a) switch K ₃ Second positive terminal of (c) and switch K ₄ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₁ And switch K ₁ Is a first negative terminal of switch K ₂ Is a first negative terminal of switch K ₃ Is connected to the first negative terminal of the switch K ₄ Is grounded; output signal O ₁ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected; wherein the voltage source IIs 1V, the voltage of the voltage source II is 2V, the voltage of the voltage source III is 3V, and the voltage of the voltage source IV is 4V;

the signal processing unit II comprises an inverter INV ₃ -INV ₄ AND gate AND ₅ -AND ₈ And switch K ₅ -K ₈ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₅ AND gate AND ₆ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₀ Respectively with inverter INV ₃ AND gate AND ₆ AND AND gate AND ₈ Is connected with the input end of the digital signal terminal B ₁ Respectively with inverter INV ₄ AND gate AND ₇ AND AND gate AND ₈ Is connected with the input end of the inverter INV ₃ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₇ Is connected with the input end of the inverter INV ₄ Respectively AND the output ends of (a) with AND gates ₅ AND gate AND ₆ Is connected with the input end of the power supply; AND gate AND ₅ Output of (d) and switch K ₅ A switch K connected to the first positive terminal ₅ Second positive terminal of (a) and switch K ₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₅ Is connected with the first negative terminal of the switch K ₅ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₆ Output of (d) and switch K ₆ A switch K connected to the first positive terminal ₆ Second positive terminal of (a) and switch K ₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₆ Is connected with the first negative terminal of the switch K ₆ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₇ Output of (d) and switch K ₇ A switch K connected to the first positive terminal ₇ Second positive terminal of (a) and switch K ₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₇ Is connected with the first negative terminal of the switch K ₇ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₈ Output of (d) and switch K ₈ A switch K connected to the first positive terminal ₈ Second positive terminal of (a) and switch K ₈ Is connected to the first negative terminal of (a)The resistor R is connected between the sub- ₁ Switch K ₈ Is connected with the first negative terminal of the switch K ₈ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₅ Second positive terminal of (a) switch K ₆ Second positive terminal of (a) switch K ₇ Second positive terminal of (c) and switch K ₈ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₂ And switch K ₅ Is a first negative terminal of switch K ₆ Is a first negative terminal of switch K ₇ Is connected to the first negative terminal of the switch K ₈ Is grounded; output signal O ₂ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit III comprises an inverter INV ₅ -INV ₆ AND gate AND ₉ -AND ₁₂ And switch K ₉ -K ₁₂ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₉ AND gate AND ₁₀ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the digital signal terminal C ₀ Respectively with inverter INV ₅ AND gate AND ₁₀ AND AND gate AND ₁₂ Is connected with the input end of the digital signal terminal C ₁ Respectively with inverter INV ₆ AND gate AND ₁₁ AND AND gate AND ₁₂ Is connected with the input end of the inverter INV ₅ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₁ Is connected with the input end of the inverter INV ₆ Respectively AND the output ends of (a) with AND gates ₉ AND gate AND ₁₀ Is connected with the input end of the power supply; AND gate AND ₉ Output of (d) and switch K ₉ A switch K connected to the first positive terminal ₉ Second positive terminal of (a) and switch K ₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₉ Is connected with the first negative terminal of the switch K ₉ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₀ Output of (d) and switch K ₁₀ A switch K connected to the first positive terminal ₁₀ Second positive terminal of (a) and switch K ₁₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₀ Is connected with the first negative terminal of the switch K ₁₀ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₁ Output of (d) and switch K ₁₁ A switch K connected to the first positive terminal ₁₁ Second positive terminal of (a) and switch K ₁₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₁ Is connected with the first negative terminal of the switch K ₁₁ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₂ Output of (d) and switch K ₁₂ A switch K connected to the first positive terminal ₁₂ Second positive terminal of (a) and switch K ₁₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₂ Is connected with the first negative terminal of the switch K ₁₂ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₉ Second positive terminal of (a) switch K ₁₀ Second positive terminal of (a) switch K ₁₁ Second positive terminal of (c) and switch K ₁₂ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₃ And switch K ₉ Is a first negative terminal of switch K ₁₀ Is a first negative terminal of switch K ₁₁ Is connected to the first negative terminal of the switch K ₁₂ Is grounded; output signal O ₃ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit IV includes an inverter INV ₇ -INV ₈ AND gate AND ₁₃ -AND ₁₆ And switch K ₁₃ -K ₁₆ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₃ AND gate AND ₁₄ AND gate AND ₁₅ AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₀ Respectively with inverter INV ₇ AND gate AND ₁₄ AND AND gate AND ₁₆ Is connected with the input end of the digital signal terminal D ₁ Respectively with inverter INV ₈ AND gate AND ₁₅ AND AND gate AND ₁₆ Is connected with the input end of the inverter INV ₇ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₅ Is connected with the input end ofInverter INV ₈ Respectively AND the output ends of (a) with AND gates ₁₃ AND gate AND ₁₄ Is connected with the input end of the power supply; AND gate AND ₁₃ Output of (d) and switch K ₁₃ A switch K connected to the first positive terminal ₁₃ Second positive terminal of (a) and switch K ₁₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₃ Is connected with the first negative terminal of the switch K ₁₃ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₄ Output of (d) and switch K ₁₄ A switch K connected to the first positive terminal ₁₄ Second positive terminal of (a) and switch K ₁₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₄ Is connected with the first negative terminal of the switch K ₁₄ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₅ Output of (d) and switch K ₁₅ A switch K connected to the first positive terminal ₁₅ Second positive terminal of (a) and switch K ₁₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₅ Is connected with the first negative terminal of the switch K ₁₅ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₁₆ Output of (d) and switch K ₁₆ A switch K connected to the first positive terminal ₁₆ Second positive terminal of (a) and switch K ₁₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₆ Is connected with the first negative terminal of the switch K ₁₆ A voltage source IV is connected between the second negative terminals of the first and second electrodes; switch K ₁₃ Second positive terminal of (a) switch K ₁₄ Second positive terminal of (a) switch K ₁₅ Second positive terminal of (c) and switch K ₁₆ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₄ And switch K ₁₃ Is a first negative terminal of switch K ₁₄ Is a first negative terminal of switch K ₁₅ Is connected to the first negative terminal of the switch K ₁₆ Is grounded; output signal O ₄ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the signal processing unit V comprises an inverterINV (electronic magnetic field) device ₉ -INV ₁₀ AND gate AND ₁₇ -AND ₂₀ And switch K ₁₇ -K ₂₀ The method comprises the steps of carrying out a first treatment on the surface of the The Q terminal is respectively AND-gate with AND gate ₁₇ AND gate AND ₁₈ AND gate AND ₁₉ AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₀ Respectively with inverter INV ₉ AND gate AND ₁₈ AND AND gate AND ₂₀ Is connected with the input end of the digital signal terminal E ₁ Respectively with inverter INV ₁₀ AND gate AND ₁₉ AND AND gate AND ₂₀ Is connected with the input end of the inverter INV ₉ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₉ Is connected with the input end of the inverter INV ₁₀ Respectively AND the output ends of (a) with AND gates ₁₇ AND gate AND ₁₈ Is connected with the input end of the power supply; AND gate AND ₁₇ Output of (d) and switch K ₁₇ A switch K connected to the first positive terminal ₁₇ Second positive terminal of (a) and switch K ₁₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₇ Is connected with the first negative terminal of the switch K ₁₇ A voltage source I is connected between the second negative terminals of the battery; AND gate AND ₁₈ Output of (d) and switch K ₁₈ A switch K connected to the first positive terminal ₁₈ Second positive terminal of (a) and switch K ₁₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₈ Is connected with the first negative terminal of the switch K ₁₈ A voltage source II is connected between the second negative terminals of the battery; AND gate AND ₁₉ Output of (d) and switch K ₁₉ A switch K connected to the first positive terminal ₁₉ Second positive terminal of (a) and switch K ₁₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₁₉ Is connected with the first negative terminal of the switch K ₁₉ A voltage source III is connected between the second negative terminals of the first and second electrodes; AND gate AND ₂₀ Output of (d) and switch K ₂₀ A switch K connected to the first positive terminal ₂₀ Second positive terminal of (a) and switch K ₂₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₀ Is connected with the first negative terminal of the switch K ₂₀ Is connected between the second negative terminals of (a)The voltage source IV is connected; switch K ₁₇ Second positive terminal of (a) switch K ₁₈ Second positive terminal of (a) switch K ₁₉ Second positive terminal of (c) and switch K ₂₀ The second positive terminal of (2) is superimposed by a summing element to obtain an output signal O ₅ And switch K ₁₇ Is a first negative terminal of switch K ₁₈ Is a first negative terminal of switch K ₁₉ Is connected to the first negative terminal of the switch K ₂₀ Is grounded; output signal O ₅ The input terminal of the judgment module, the input terminal of the retention module and the input terminal of the correction module are respectively connected;

the judging module comprises a comparator CP ₁ -CP ₂₄ OR gate OR ₁ -OR ₈ AND AND gate AND ₂₁ -AND ₂₄ The method comprises the steps of carrying out a first treatment on the surface of the Output signal O ₁ Respectively with comparator CP ₁ Comparator CP ₂ And comparator CP ₃ Is connected with the positive input terminal of (1) and outputs a signal O ₂ Respectively with comparator CP ₁ Negative input terminal of (1) comparator CP ₄ Positive input terminal of (1) and comparator CP ₆ Is connected with the positive input terminal of (1) and outputs a signal O ₃ Respectively with comparator CP ₂ Negative input terminal of (1) comparator CP ₄ Negative input terminal of (1) comparator CP ₅ Positive input terminal of (1) and comparator CP ₇ Is connected with the positive input terminal of (1) and outputs a signal O ₄ Respectively with comparator CP ₃ Negative input terminal of (1) comparator CP ₅ Negative input terminal of (1) and comparator CP ₈ Is connected with the positive input terminal of (1) and outputs a signal O ₅ Respectively with comparator CP ₆ Comparator CP ₇ And comparator CP ₈ Is connected with the negative input terminal of the circuit board; comparator CP ₁ Respectively with the comparator CP ₉ Positive input terminal of (1) and comparator CP ₁₀ Is connected to the negative input terminal of the comparator CP ₂ Respectively with the comparator CP ₁₁ Positive input terminal of (1) and comparator CP ₁₂ Is connected to the negative input terminal of the comparator CP ₃ Respectively with the comparator CP ₁₃ Positive input terminal of (1) and comparator CP ₁₄ Is connected with the negative input terminal of the comparatorCP ₄ Respectively with the comparator CP ₁₅ Positive input terminal of (1) and comparator CP ₁₆ Is connected to the negative input terminal of the comparator CP ₅ Respectively with the comparator CP ₁₇ Positive input terminal of (1) and comparator CP ₁₈ Is connected to the negative input terminal of the comparator CP ₆ Respectively with the comparator CP ₁₉ Positive input terminal of (1) and comparator CP ₂₀ Is connected to the negative input terminal of the comparator CP ₇ Respectively with the comparator CP ₂₁ Positive input terminal of (1) and comparator CP ₂₂ Is connected to the negative input terminal of the comparator CP ₈ Respectively with the comparator CP ₂₃ Positive input terminal of (1) and comparator CP ₂₄ Is connected to the negative input terminal of the comparator CP ₉ Comparator CP ₁₁ Comparator CP ₁₃ Comparator CP ₁₅ Comparator CP ₁₇ Comparator CP ₁₉ Comparator CP ₂₁ And comparator CP ₂₃ The negative input terminals of (a) are all grounded, comparator CP ₁₀ Comparator CP ₁₂ Comparator CP ₁₄ Comparator CP ₁₆ Comparator CP ₁₈ Comparator CP ₂₀ Comparator CP ₂₂ Comparator CP ₂₄ The positive input terminals of the voltage transformer are all grounded; comparator CP ₉ And comparator CP ₁₀ The output terminals of (a) are respectively connected with OR gate OR ₁ Is connected to the input terminal of the comparator CP ₁₁ And comparator CP ₁₂ The output terminals of (a) are respectively connected with OR gate OR ₂ Is connected to the input terminal of the comparator CP ₁₃ And comparator CP ₁₄ The output terminals of (a) are respectively connected with OR gate OR ₃ Is connected to the input terminal of the comparator CP ₁₅ And comparator CP ₁₆ The output terminals of (a) are respectively connected with OR gate OR ₄ Is connected to the input terminal of the comparator CP ₁₇ And comparator CP ₁₈ The output terminals of (a) are respectively connected with OR gate OR ₅ Is connected to the input terminal of the comparator CP ₁₉ And comparator CP ₂₀ The output terminals of (a) are respectively connected with OR gate OR ₆ Is connected to the input terminal of the comparator CP ₂₁ And comparator CP ₂₂ The output terminals of (a) are respectively connected with OR gate OR ₇ Is connected to the input terminal of the comparator CP ₂₃ And comparisonCP device ₂₄ The output terminals of (a) are respectively connected with OR gate OR ₈ Is connected to the input of OR gate ₁ OR gate OR ₂ OR OR AND gate ₃ The output terminals of (a) are AND-gate with AND gate ₂₁ Is connected to the input of OR gate ₄ OR OR AND gate ₅ The output terminals of (a) are AND-gate with AND gate ₂₂ Is connected to the input of OR gate ₆ OR gate OR ₇ OR OR AND gate ₈ The output terminals of (a) are AND-gate with AND gate ₂₃ Is connected to the input of AND gate ₂₁ AND gate AND ₂₂ AND AND gate AND ₂₃ The output terminals of (a) are AND-gate with AND gate ₂₄ Is connected to the input of AND gate ₂₄ Output signal P of output judging module ₁ Output signal P ₁ The input terminal of the retention module is connected with the input terminal of the retention module;

the retention module comprises a switch K ₂₁ -K ₂₅ Output signal P ₁ Respectively with switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is connected to the first positive terminal of (a); switch K ₂₁ Second positive terminal of (a) and switch K ₂₁ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₁ Second negative terminal of (2) and output signal O ₁ Is connected with a switch K ₂₁ The second positive terminal of (2) outputs the output signal V of the retention module ₁ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₂ Second positive terminal of (a) and switch K ₂₂ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₂ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₂ The second positive terminal of (2) outputs the output signal V of the retention module ₂ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₃ Second positive terminal of (a) and switch K ₂₃ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₃ Second negative terminal of (2) and output signal O ₃ Is connected with a switch K ₂₃ The second positive terminal of (2) outputs the output signal V of the retention module ₃ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₄ Second positive terminal of (a) and switch K ₂₄ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₄ Second negative terminal and output of (a)Signal O ₄ Is connected with a switch K ₂₄ The second positive terminal of (2) outputs the output signal V of the retention module ₄ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₅ Second positive terminal of (a) and switch K ₂₅ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₅ Second negative terminal of (2) and output signal O ₅ Is connected with a switch K ₂₅ The second positive terminal of (2) outputs the output signal V of the retention module ₅ The method comprises the steps of carrying out a first treatment on the surface of the And switch K ₂₁ Switch K ₂₂ Switch K ₂₃ Switch K ₂₄ And switch K ₂₅ Is grounded;

the correction module comprises a switch K ₂₆ -K ₃₀ Memristor array and amplifier AM ₁ -AM ₅ Inverter INV ₁₁ -INV ₁₅ And buffer BUF ₁ -BUF ₅ The method comprises the steps of carrying out a first treatment on the surface of the Switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first positive terminals of the switch K are connected with the power supply voltage ₂₆ Second positive terminal of (a) and switch K ₂₆ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₆ Second negative terminal of (2) and output signal O ₁ Is connected with a switch K ₂₇ Second positive terminal of (a) and switch K ₂₇ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₇ Second negative terminal of (2) and output signal O ₂ Is connected with a switch K ₂₈ Second positive terminal of (a) and switch K ₂₈ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₈ Second negative terminal of (2) and output signal O ₃ Is connected with a switch K ₂₉ Second positive terminal of (a) and switch K ₂₉ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₂₉ Second negative terminal of (2) and output signal O ₄ Is connected with a switch K ₃₀ Second positive terminal of (a) and switch K ₃₀ A resistor R is connected between the first negative terminals of (a) ₁ Switch K ₃₀ Second negative terminal of (2) and output signal O ₅ Is connected with each other; switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The first negative terminals of (a) are all grounded, switch K ₂₆ Switch K ₂₇ Switch K ₂₈ Switch K ₂₉ And switch K ₃₀ The second positive terminals of the memristor array are connected with the input end of the memristor array, and the output end of the memristor array is respectively connected with the amplifier AM ₁ -AM ₅ Is connected to the negative input terminal of the amplifier AM ₁ -AM ₅ The positive input terminals of (a) are all grounded, and the amplifier AM ₁ Negative input terminal of (a) and amplifier AM ₁ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₁ Output terminal of (a) and inverter INV ₁₁ Is connected with the input end of the inverter INV ₁₁ Output of (d) and buffer BUF ₁ Is connected with the negative input terminal of the buffer BUF ₁ Output terminal of the output correction module outputs an output signal V ₆ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₂ Negative input terminal of (a) and amplifier AM ₂ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₂ Output terminal of (a) and inverter INV ₁₂ Is connected with the input end of the inverter INV ₁₂ Output of (d) and buffer BUF ₂ Is connected with the negative input terminal of the buffer BUF ₂ Output terminal of the output correction module outputs an output signal V ₇ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₃ Negative input terminal of (a) and amplifier AM ₃ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₃ Output terminal of (a) and inverter INV ₁₃ Is connected with the input end of the inverter INV ₁₃ Output of (d) and buffer BUF ₃ Is connected with the negative input terminal of the buffer BUF ₃ Output terminal of the output correction module outputs an output signal V ₈ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₄ Negative input terminal of (a) and amplifier AM ₄ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₄ Output terminal of (a) and inverter INV ₁₄ Is connected with the input end of the inverter INV ₁₄ Output of (d) and buffer BUF ₄ Is connected with the negative input terminal of the buffer BUF ₄ Output terminal of the output correction module outputs an output signal V ₉ The method comprises the steps of carrying out a first treatment on the surface of the Amplifier AM ₅ Negative input terminal of (a) and amplifier AM ₅ A resistor R is connected between the output terminals of (a) ₁ Amplifier AM ₅ Output terminal of (a) and inverter INV ₁₅ Is connected with the input end of the inverter INV ₁₅ Output of (d) and buffer BUF ₅ Is connected with the negative input terminal of the buffer BUF ₅ Output terminal of the output correction module outputs an output signal V ₁₀ The method comprises the steps of carrying out a first treatment on the surface of the Buffer BUF ₁ -BUF ₅ The positive input terminals of the voltage transformer are all grounded;

the memristive array includes memristances M ₁ -M ₂₅ Memristor M ₁ Memristor M ₆ Memristor M ₁₁ Memristor M ₁₆ And memristance M ₂₁ The input ends of the (C) are connected with the switch K ₂₆ Is connected with the second positive terminal of the memristor M ₂ Memristor M ₇ Memristor M ₁₂ Memristor M ₁₇ And memristance M ₂₂ The input ends of the (C) are connected with the switch K ₂₇ Is connected with the second positive terminal of the memristor M ₃ Memristor M ₈ Memristor M ₁₃ Memristor M ₁₈ And memristance M ₂₃ The input ends of the (C) are connected with the switch K ₂₈ Is connected with the second positive terminal of the memristor M ₄ Memristor M ₉ Memristor M ₁₄ Memristor M ₁₉ And memristance M ₂₄ The input ends of the (C) are connected with the switch K ₂₉ Is connected with the second positive terminal of the memristor M ₅ Memristor M ₁₀ Memristor M ₁₅ Memristor M ₂₀ And memristance M ₂₅ The input ends of the (C) are connected with the switch K ₃₀ Is connected with the second positive terminal of the memristor M ₁ -M ₅ Are connected with the output end of the amplifier AM ₁ Is connected with the negative input terminal of the memristor M ₆ -M ₁₀ Are connected with the output end of the amplifier AM ₂ Is connected with the negative input terminal of the memristor M ₁₁ -M ₁₅ Are connected with the output end of the amplifier AM ₃ Is connected with the negative input terminal of the memristor M ₁₆ -M ₂₀ Are connected with the output end of the amplifier AM ₄ Is connected with the negative input terminal of the memristor M ₂₁ -M ₂₅ Are connected with the output end of the amplifier AM ₅ Is connected to the negative input terminal of (c).