CN104579631A - AES (Advanced Encryption Standard) secret key generation structure and method based on latch type voltage sensitive amplifier PUF (Physical Unclonable Function) - Google Patents

Abstract

The invention discloses an AES (Advanced Encryption Standard) secret key generation structure and method based on a latch type voltage sensitive amplifier PUF (Physical Unclonable Function). The AES secret key generation structure comprises a core unit and a peripheral circuit, wherein an SAPUF structure of the core unit utilizes a differential structure of the StrongARM type latch sensitive amplifier as a PUF structure; the peripheral circuit comprises a SRAM (Static Random Access Memory). After the SAPUF structure is powered on, positive bias voltage is applied to the SAPUF structure to obtain code values of N*N stored in the SRAM; negative bias voltage is applied to the SAPUF structure, the code values pre-stored in the StrongARM are read at the same time and are subjected to same or comparative operation with new code values, and the result is written into the SRAM; if the result is 1, the selected SAPUF structure is stable; if the result is 0, the structure is unstable to be marked and stored as a reliable PUF address; zero bias voltage is applied to the AES secret key generation structure, and the corresponding number of code values are read by a controller from a SAPUF array in reference with the reliable PUF address pre-stored in the SRAM and are used as a secret key to be outputted. According to the AES secret key generation structure and method, the secret key is provided for an AES encryption and decryption circuit, and the uniqueness, the unduplicatedness and the reliability of the secret key are ensured.

Description

AES key based on latch-type pressure sensitive amplifier PUF produces structure and method

Technical field

The present invention uses a kind of StrongARM type to latch sense amplifier as PUF (Physical Unclonable Function, physics can not replicated architecture), devising can be the structure of AES (Advanced Encryption Standard, Advanced Encryption Standardalgorithm) encryption/decryption module generation key.

Background technology

21 century is epoch of information, and on the one hand, information technology and related industry high speed development, present flourishing as never before scene; On the other hand, the event of harm information security constantly occurs, and threatens national security and social stability, therefore, must take measures to guarantee the information security of China ^[1].Information security be unable to do without cryptography, and as the key technology of information security, cryptography can provide the confidentiality of information, integrality, availability and anti-supporting property.Cryptography is primarily of cryptography and cryptoanalysis two parts composition, and both cryptography and cryptoanalysis are separate, interdependence again, thus the fast development having promoted cryptography self.

AES full name is Advanced Encryption Standard, i.e. Advanced Encryption Standardalgorithm, it is a kind of block encryption standard that Federal Government adopts, this standard is used for alternative original DES (Date Encryption Standard) algorithm, this algorithm is published on FIPS PUB 197 by National Institute of Standards and Technology (NIST) November 26 calendar year 2001, and become effective standard on May 26th, 2002, by 2006, AES became one of most popular algorithm in symmetric key encryption already ^[2,3].AES obtains a wide range of applications at present, become the cryptographic algorithm of Virtual Private Network, SONET (Synchronous Optical Network), RAS (RAS), high-speed atm/Ethernet router, mobile communication, satellite communication, electronic banking business etc., and replace the use of DES in IP-See, SSL and ATM gradually.In addition, have benefited from the high speed development of cryptographic technique, government and military communication more adopt senior cryptographic algorithm, and network security system, and the aspect AES encryption algorithms such as finance is maintained secrecy, game secret are obtained for be applied widely.

PUF full name is Physical Unclonable Function, and namely physics can not replicated architecture ^[4], to utilize in various circuit structure amplification circuit production process because of the various deviations that the reasons such as technique cause, form the circuit structure of stable, unique, unpredictable result ^[5].

[list of references]

[1] Shen Changxiang, Zhang Huanguo, Feng Dengguo etc.; Summary of Information Safety [J], Chinese science E collects: information science, and 2007,37 (2): 129-150.

[2] Yang Fan; DPA attack technology based on AES crypto chip analyzes [J], high-speed railway mobile communication signal coverage optimization simplify, 2014:105.

[3] Liu Shangli, Zhao Jingqiang, Nie's duties; The modeling and analysis [J] of AES differential fault attack, computer engineering, 2010,36 (1): 189-190.

[4]Suh G E,Devadas S.Physical unclonable functions for device authentication and secret key generation[C]//Proceedings of the 44th annual Design Automation Conference.ACM,2007:9-14。

[5]Bhargava M,Mai K.An efficient reliable PUF-based cryptographic key generator in 65nm CMOS[C]//Proceedings of the conference on Design,Automation&Test in Europe.European Design and Automation Association,2014:70。

Summary of the invention

For prior art Problems existing, the invention provides a kind of AES key based on latch-type pressure sensitive amplifier PUF and produce structure, for AES decipher circuit provides the key needed for encryption and decryption, can need to provide 128,192 and 256 keys respectively according to difference, ensure the uniqueness of key, non-reproduction and reliability.

In order to solve the problems of the technologies described above, a kind of AES key based on latch-type pressure sensitive amplifier PUF that the present invention proposes produces structure, comprise core cell and peripheral circuit, described core cell is SAPUF structure, and described SAPUF structure is that a kind of StrongARM type that utilizes latches the structure of sense amplifier as PUF; Described peripheral circuit comprises a SRAM memory; It is differential configuration that described StrongARM type latches sense amplifier, comprises seven field effect transistor N1 pipes, N2 pipe, N3 pipe, N4 pipe, N5 pipe, P1 pipe and P2 pipe, and wherein, N3 pipe and N4 pipe form MOS to pipe, and the grid of described N3 pipe and N4 pipe connects bit line; N5 pipe is enable pipe, and the grid of N5 pipe meets enable control signal EN, opening and shutting off of this enable control signal EN control amplifier; N1 pipe, N2 pipe, P1 pipe and P2 pipe form the latch structure of positive feedback, and this latch structure is load relative to described MOS to pipe; The grid of N1 pipe and P1 pipe is the output OUT of amplifier, and the source electrode of described P1 pipe and P2 pipe is the power end of amplifier.

A kind of AES key production method based on latch-type pressure sensitive amplifier PUF proposed in the present invention, is adopt above-mentioned AES key to produce structure, and comprises the following steps:

Step one, StrongARM type is utilized to latch the output characteristic of sense amplifier under bit line zero pressure difference as PUF structure:

When StrongARM type latches sense amplifier two input BL and BLA voltage difference is zero, wherein, as MOS to the N3 pipe of pipe and N4 pipe mismatch, make the output voltage of StrongARM type latch sense amplifier non-vanishing, the input this output end voltage being converted StrongARM type latch sense amplifier is input offset voltage V _oFFSET:

$V_{\mathrm{OFFSET}}=(V_{\mathrm{th}1}-V_{\mathrm{th}2})+\sqrt{I}(\frac{1}{\sqrt{K_1}}-\frac{1}{\sqrt{K_2}})+\frac{1}{2}\sqrt{\frac{1}{K}}\frac{{\mathrm{\ΔR}}_0}{R_0}$

$K_1=\frac{1}{2}\mathrm{\μc}\frac{W_1}{L_1}$

$K_2=\frac{1}{2}\mathrm{\μc}\frac{W_2}{L_2}$

$K=\frac{1}{2}(K_1+K_2)$

In formula, V _th1for the threshold voltage of N3 pipe, unit is V, V _th2for the threshold voltage of N4 pipe, unit is V, I is the electric current flowing through N5 pipe, and unit is A, R ₀for by the equivalent resistance of entering viewed from N1 and N2 pipe source electrode, unit is Ω, μ is device surface mobility, and unit is cm ²/ Vs, c are device unit are gate oxide capacitance, and unit is F/cm ², W ₁/ L ₁the breadth length ratio of N3 pipe, W ₂/ L ₂it is the breadth length ratio of N4 pipe.

Drawn by above formula, offset voltage V _oFFSETby MOS, the mismatch of the difference of the cut-in voltage of pipe and K Summing Factor load resistance is determined, and relevant with the root of bias current I, utilize the output characteristic of this StrongARM type latch sense amplifier under bit line zero pressure difference as a kind of PUF structure thus form SAPUF structure;

Step 2, the SAPUF structure determined for step one are screened:

First apply certain+Δ V and-Δ V to SAPUF before use, by judging whether the output of SAPUF structure stablizes, selecting stable SAPUF structure, formed and then use, single SAPUF screening process is as follows:

Step 2-1: to SAPUF structure applying+Δ V voltage, the output of recording SAPUF structure is this moment OUT1;

Step 2-2: to SAPUF structure applying-Δ V voltage, the output of recording SAPUF structure is this moment OUT2;

Step 2-3: OUT1 and OUT2 is compared, if numerical value is the same, then this SAPUF structure is stable at bias voltage Δ V, can use;

Step 2-4: repeat above-mentioned steps 1 ~ 3, until select abundant SAPUF structure, is used for producing the key of fixing figure place;

Step 2-5: the SAPUF structure that record is selected, when needing key, applies the high level of zero-bias to selected SAPUF, reads the output of SAPUF;

Step 3, the SAPUF structure construction AES key using step 2 to filter out produce structure

After the SAPUF structure screened step 2 powers on, first controller controls diverter switch to SAPUF applying+Δ V voltage, obtain the code value of N*N, this code value is stored in the middle of SRAM memory by controller, then diverter switch is controlled to SAPUF applying-Δ V voltage by controller, meanwhile, the code value be pre-stored in the middle of SRAM memory is read out, then same or compare operation is carried out with the code value newly obtained, comparative result is write in the middle of SRAM memory, if same or comparative result is 1, then selected SAPUF Stability Analysis of Structures, if same or comparative result is 0, then selected SAPUF structural instability, address mark in this, as reliable PUF stores,

Produce structure to AES key and apply zero-bias, namely Δ V is 0, then, controller, with reference to the address being stored in advance in the reliable PUF in the middle of SRAM, reads the code value of respective number, exports as key from SAPUF array, and according to key length, determine the key taking out corresponding length.

Compared with prior art, the invention has the beneficial effects as follows:

Utilize StrongARM type to latch sense amplifier as PUF structure (hereinafter referred to as SAPUF) in the present invention, form AES key in the present invention and produce the core cell of structure.

Disclosed in the encryption flow of AES and algorithm are; the core of protection aes algorithm is the safety of Protective Key (Key); and in recent years; get more and more for the cipher key attacks be pre-stored in AES decipher circuit; in order to ensure the safety of key; part researcher is studied in circuit enhancing, and some is studied how producing in not reproducible unique key.Through the retrieval of pertinent literature and patent, existing part researcher proposes to produce structure based on the key of variety classes PUF at present, but needs to carry out ECC (Error Correcting Code, error checking and correction) operation.Utilize key of the present invention to produce structure and can produce unique, not reproducible and reliable AES encryption and decryption key, this structure is simple and easy to use, and stable output, 128,192,256 keys can be produced as required, can use as IP kernel.Because the present invention utilizes SAPUF structure (StrongARM type latches sensitive amplifier structure as PUF structure), without the need to carrying out ECC operation; In addition, produce structure compared to other structures key of the present invention minimum for the demand of peripheral circuit, only need optional equipment SRAM (Static RAM, static random access memory).

Accompanying drawing explanation

Fig. 1 is that StrongARM type latches sensitive amplifier structure schematic diagram;

Fig. 2 is that the AES key be made up of SAPUF produces structure.

Embodiment

Below in conjunction with the drawings and specific embodiments, technical solution of the present invention is described in further detail.

A kind of AES key based on latch-type pressure sensitive amplifier PUF that the present invention proposes produce structure be with SAPUF array for core, add that associated peripheral circuits is formed.As shown in Figure 2, this AES key produces structure and comprises core cell and peripheral circuit, and described core cell is SAPUF structure, and described SAPUF structure is that a kind of StrongARM type that utilizes latches the structure of sense amplifier as PUF; Described peripheral circuit comprises a SRAM memory.

As shown in Figure 1, it is the structure chart that StrongARM type latches sense amplifier (hereinafter referred to as SA sense amplifier), this amplifier is differential configuration, comprise seven field effect transistor: N1 pipes, N2 pipe, N3 pipe, N4 manages, N5 manages, P1 manages and P2 pipe, wherein, N3 pipe and N4 pipe form MOS to pipe, and N3 pipe and N4 pipe are Differential Input pipe, sense amplifier offset voltage V _oFFSETsize and N3 manages and the square root of N4 pipe area is inversely proportional to, and its grid connects bit line; N5 pipe is enable pipe, and the grid of N5 pipe meets enable control signal EN, opening and shutting off of this enable control signal EN control amplifier, and the breadth length ratio of enable pipe is maximum for the rate of amplifier; N1 pipe, N2, P1 and P2 form the latch structure of positive feedback, and this latch structure can be considered as load relative to described MOS to pipe; The grid of N1 pipe and P1 pipe is the output OUT of amplifier, and the source electrode of described P1 pipe and P2 pipe is the power end of amplifier.

Composition graphs 1 illustrates the SA sense amplifier operation principle ideally in the present invention:

When enable signal EN is low level, N5 pipe turns off, and amplifier does not work, and output port OUT is charged to high level by pre-washing pipe; Ideally, if there is voltage difference between two bit lines, when enable signal EN becomes high level, enable pipe N5 opens, and amplifier is started working, and the voltage difference between two bit lines is amplified.Suppose that BL terminal voltage is greater than BLA terminal voltage, the electric current flowing through N3 can be made to be greater than the electric current flowing through N4, cause b point current potential to decline than a point current potential fast, when b point current potential drops to VDD-|V _th| time, P1 opens and starts to charge to a point, when the charging current flowing through P1 is greater than the discharging current flowing through N1, a point current potential rises, and then impel b point current potential to continue to decline, start positive feedback, until a point exports as high level " 1 ", now b point is low level " 0 ", and amplifier exports " 1 ".On the contrary, if BL terminal voltage is less than BLA terminal voltage, final b point is high level " 1 ", and amplifier exports " 0 ".

Composition graphs 1 illustrates the operation principle under the SA sense amplifier actual conditions in the present invention:

Ideally, free voltage difference between two bit lines can be amplified by amplifier, SA sense amplifier correctly can amplify the voltage difference between two bit lines, be strongly depend on the coupling of N3/N4 pipe, and in reality, due to the factor such as matching problem, process deviation of metal-oxide-semiconductor, cause N3/N4 to manage and do not mate.In actual processing, the machining deviation of metal-oxide-semiconductor, is mainly reflected in the change of breadth length ratio, according to formula (1):

$I_D={\mathrm{\μ}}_n{C}_{\mathrm{OX}}\frac{W}{L}[(V_{\mathrm{GS}}-V_{\mathrm{TH}})V_{\mathrm{DS}}-\frac{1}{2}{V}_{\mathrm{DS}}^2]---\left(1\right)$

In formula (1), I _dfor flowing through the electric current of metal-oxide-semiconductor, unit is ampere, μ _nfor the surface mobility of device, unit is cm ²/ Vs, C _oxfor device unit are gate oxide capacitance, unit is F/cm ², W/L is the breadth length ratio of device, V _gSthat device grids and source voltage are poor, V _tHthe threshold voltage of device, V _dSit is the drain source voltage of device.Flow through the size of current of a metal-oxide-semiconductor, depend on process constant μ _nc _ox, the size W of device and L and grid and drain electrode relative to source electrode current potential between relation.The change of breadth length ratio can cause N3 pipe, N4 tube current varies in size, and exports non-vanishing under finally causing input zero-voltage difference situation.Such as, two bit-line voltages are set to identical high level, allow N3 manage and N4 conducting, suppose process constant μ _nc _oxstable, because N3 pipe and N4 exist the matching problem of size in the course of processing, namely breadth length ratio W/L is different, can cause flowing through N3 pipe different with the electric current of N4, if N3 tube current is greater than N4 tube current, OUT finally can export " 1 ", if N3 tube current is greater than N4 tube current, OUT finally can export " 0 ".

The implementation method of the AES key generation structure based on latch-type pressure sensitive amplifier PUF shown in Fig. 1 is adopted mainly to consider the following aspects:

SA sense amplifier is utilized to form SAPUT as PUF structure:

In actual use, when SA sense amplifier two input terminal voltage difference is zero, because N3, N4 are to the mismatch of pipe, make output voltage non-vanishing, this voltage is converted input and is just called input offset voltage V _oFFSET, according to formula (2):

$V_{\mathrm{OFFSET}}=(V_{\mathrm{th}1}-V_{\mathrm{th}2})+\sqrt{I}(\frac{1}{\sqrt{K_1}}-\frac{1}{\sqrt{K_2}})+\frac{1}{2}\sqrt{\frac{1}{K}}\frac{{\mathrm{\ΔR}}_0}{R_0}---\left(2\right)$

In formula (2), V _th1for the threshold voltage of N3 pipe, unit is V, V _th2for the threshold voltage of N4 pipe, unit is V, I is the electric current flowing through N5 pipe, and unit is A, R ₀for by the equivalent resistance of entering viewed from N1 and N2 pipe source electrode, to be Ω, K be and the closely-related factor of influence of metal-oxide-semiconductor in unit.Offset voltage V _oFFSETby MOS, the mismatch of the difference of the cut-in voltage of pipe N3, N4 pipe and K Summing Factor load resistance is determined, and relevant with the root of bias current.Only between two bit lines, voltage difference is greater than certain offset voltage V _oFFSETtime, the voltage difference between the amplification bit line that amplifier can be correct.Such as, if BL is set to high level, BLA is set to low level, but between two bit lines, voltage difference is less than V _oFFSET, the N3 pipe caused by voltage difference and N4 tube current deficient change to offset the size of current difference brought because breadth length ratio is different, then there will be and export the constant situation of OUT.Due to the matching problem existed in the course of processing, there is very strong randomness, cause the output of OUT not by manual control, therefore utilize the output characteristic of amplifier under bit line zero pressure difference, as a kind of PUF structure.

SAPUF stability in actual use:

Utilize SA sense amplifier as PUF, need the stability problem considering that it exports, offset voltage V in actual use _oFFSETthe impact of ambient temperature and load end resistance etc. can be subject to, V _oFFSETlarger, the stability of SAPUF is higher, therefore can weigh the stability of SAPUF structure under certain bias voltage Δ V.To preset BL and BLA voltage difference be Δ V, BL voltage higher than BLA be+Δ V, BL voltage is-Δ V lower than BLA.Situation of dividing below discusses the course of work of SAPUF in reality.

1) N3 is larger than N4 breadth length ratio, amplifier operation offset voltage voltage V _oFFSET, Δ V<V _oFFSET.

First consider applying+Δ V situation, EN signal is from after low level becomes high level, and amplifier is started working, and because N3 is larger than N4 breadth length ratio, and BL voltage is higher than BLA voltage, so flow through N3 tube current to be greater than N4 tube current, finally causes exporting for " 1 "; Next considers applying-Δ V situation, and EN signal is from after low level becomes high level, and amplifier is started working, due to Δ V<V _oFFSET, can not offset the curent change because N3 causes greatly than N4 breadth length ratio, final result remains and flows through N3 tube current and be greater than N4 tube current, finally causes exporting as " 1 ".In this case, when using as PUF, can stablize and ensure that PUF exports as " 1 ".

2) N3 is larger than N4 breadth length ratio, amplifier operation offset voltage V _oFFSET, Δ V>V _oFFSET.

First consider applying+Δ V situation, EN signal is from after low level becomes high level, and amplifier is started working, and because N3 is larger than N4 breadth length ratio, and BL voltage is higher than BLA voltage, so flow through N3 tube current to be greater than N4 tube current, finally causes exporting for " 1 "; Next considers applying-Δ V situation, and EN signal is from after low level becomes high level, and amplifier is started working, although N3 is larger than N4 breadth length ratio, and Δ V>V _oFFSET, the electric current flowing through N3 pipe can be caused to be less than the electric current flowing through N4 pipe, finally to cause exporting as " 0 ".In this case, when using as PUF, because its output can not keep a stable numerical value, therefore be unstable.

Through above-mentioned 1), 2) discussion, can drawing, in order to ensure SAPUF stability in the course of the work, needing offset voltage V _oFFSETlarger, to ensure the stability of PUF, simultaneously owing in use needing the PUF structure that can ensure some to use, therefore need to choose suitable Δ V, the SAPUF unit selecting sufficient amount should be guaranteed, ensure that the SAPUF unit selected is reliable again.

The screening process of reliable SAPUF

In actual use, we can choose a lot of PUF, and common formation AES key produces structure, due to the randomness of the course of processing, and the offset voltage V of different PUF itself _oFFSETalso different, so need the characteristic utilizing PUF itself, a screening is carried out for PUF structure, namely first certain+Δ V and-Δ V is applied to PUF before use, by judging whether the output of PUF structure stablizes, select stable PUF structure, and then use, single PUF screening process is as follows:

Step 1: to PUF structure applying+Δ V voltage, record the output of PUF structure this moment, OUT1

Step 2: to PUF structure applying-Δ V voltage, record the output of PUF structure this moment, OUT2

Step 3: compared by OUT1 and OUT2, if numerical value is the same, then this PUF structure is stable at bias voltage Δ V, can use

Step 4: repeat step 1 ~ 3, until select abundant PUF structure, is used for producing the key of fixing figure place

Step 5: the PUF structure that record is selected, needs the high level only needing during key to apply zero-bias to selected PUF, reads the output of PUF.

SAPUF structure construction AES key is used to produce structure

As shown in Figure 2, be utilize the AES key of SAPUF Structure composing to produce structured flowchart.

Before the use, first need to produce structure to this key to correct, namely PUF core array is wherein screened, after this structure is powered on, first controller controls diverter switch to SAPUF applying+Δ V voltage, the code value of N*N can be obtained, this code value is stored in the middle of SRAM memory by controller, then diverter switch is controlled to SAPUF applying-Δ V voltage by controller, meanwhile, by the digital independent that is pre-stored in the middle of SRAM memory out, then same or compare operation is carried out with the code value newly obtained, comparative result is write in the middle of SRAM memory, if selected SAPUF Stability Analysis of Structures, then same or comparative result is 1, if selected SAPUF structural instability, same or comparative result is 0, can store as the address mark of reliable PUF using this.

In normal use, structure is produced to AES key and applies zero-bias, namely Δ V is 0, then controller is with reference to the address being stored in advance in the reliable PUF in the middle of SRAM, according to system requirements, reads the code value of respective number from SAPUF array, export as key, in use, generally according to key length, the key taking out corresponding length can be determined.

Although invention has been described by reference to the accompanying drawings above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present invention; when not departing from present inventive concept, can also make a lot of distortion, these all belong within protection of the present invention.

Claims (2)

1. the AES key based on latch-type pressure sensitive amplifier PUF produces structure, it is characterized in that, comprise core cell and peripheral circuit, described core cell is SAPUF structure, and described SAPUF structure is that a kind of StrongARM type that utilizes latches the structure of sense amplifier as PUF; Described peripheral circuit comprises a SRAM memory;

It is differential configuration that described StrongARM type latches sense amplifier, and comprise seven field effect transistor: N1 pipes, N2 manages, N3 pipe, N4 pipe, N5 pipe, P1 manage and P2 manages, wherein, N3 pipe and N4 pipe form MOS to pipe, and the grid of described N3 pipe and N4 pipe connects bit line; N5 pipe is enable pipe, and the grid of N5 pipe meets enable control signal EN, opening and shutting off of this enable control signal EN control amplifier; N1 pipe, N2 pipe, P1 pipe and P2 pipe form the latch structure of positive feedback, and this latch structure is load relative to described MOS to pipe; The grid of N1 pipe and P1 pipe is the output OUT of amplifier, and the source electrode of described P1 pipe and P2 pipe is the power end of amplifier.

2. based on an AES key production method of latch-type pressure sensitive amplifier PUF, it is characterized in that, adopt and produce structure based on the AES key of latch-type pressure sensitive amplifier PUF as claimed in claim 1, and comprise the following steps:

Step one, StrongARM type is utilized to latch the output characteristic of sense amplifier under bit line zero pressure difference as PUF structure:

When StrongARM type latches sense amplifier two input BL and BLA voltage difference is zero, wherein, as MOS to the N3 pipe of pipe and N4 pipe mismatch, make the output voltage of StrongARM type latch sense amplifier non-vanishing, the input this output end voltage being converted StrongARM type latch sense amplifier is input offset voltage V _oFFSET:

$V_{\mathrm{OFFSET}}=(V_{\mathrm{th}1}-V_{\mathrm{th}2})+\sqrt{I}(\frac{1}{\sqrt{K_1}}-\frac{1}{\sqrt{K_2}})+\frac{1}{2}\sqrt{\frac{1}{K}}\frac{{\mathrm{\&Delta;R}}_0}{R_0}$

$K_1=\frac{1}{2}\mathrm{\&mu;c}\frac{W_1}{L_1}$

$K_2=\frac{1}{2}\mathrm{\&mu;c}\frac{W_2}{L_2}$

$K=\frac{1}{2}(K_1+K_2)$

In above formula, V _th1for the threshold voltage of N3 pipe, unit is V, V _th2for the threshold voltage of N4 pipe, unit is V, I is the electric current flowing through N5 pipe, and unit is A, R ₀for by the equivalent resistance of entering viewed from N1 and N2 pipe source electrode, unit is Ω, μ is device surface mobility, and unit is cm ²/ Vs, c are device unit are gate oxide capacitance, and unit is F/cm ², W ₁/ L ₁the breadth length ratio of N3 pipe, W ₂/ L ₂it is the breadth length ratio of N4 pipe;

Drawn by above formula, offset voltage V _oFFSETby MOS, the mismatch of the difference of the cut-in voltage of pipe and K Summing Factor load resistance is determined, and relevant with the root of bias current I, utilize the output characteristic of this StrongARM type latch sense amplifier under bit line zero pressure difference as a kind of PUF structure thus form SAPUF structure;

Step 2, the SAPUF structure determined for step one are screened:

First apply certain+Δ V and-Δ V to SAPUF before use, by judging whether the output of SAPUF structure stablizes, selecting stable SAPUF structure, formed and then use, single SAPUF screening process is as follows:

Step 2-1: to SAPUF structure applying+Δ V voltage, the output of recording SAPUF structure is this moment OUT1;

Step 2-2: to SAPUF structure applying-Δ V voltage, the output of recording SAPUF structure is this moment OUT2;

Step 2-3: OUT1 and OUT2 is compared, if numerical value is the same, then this SAPUF structure is stable at bias voltage Δ V, can use;

Step 2-4: repeat above-mentioned steps 1 ~ 3, until select abundant SAPUF structure, is used for producing the key of fixing figure place;

Step 2-5: the SAPUF structure that record is selected, when needing key, applies the high level of zero-bias to selected SAPUF, reads the output of SAPUF;

Step 3, the SAPUF structure construction AES key using step 2 to filter out produce structure

After the SAPUF structure screened step 2 powers on, first controller controls diverter switch to SAPUF applying+Δ V voltage, obtain the code value of N*N, this code value is stored in the middle of SRAM memory by controller, then diverter switch is controlled to SAPUF applying-Δ V voltage by controller, meanwhile, the code value be pre-stored in the middle of SRAM memory is read out, then same or compare operation is carried out with the code value newly obtained, comparative result is write in the middle of SRAM memory, if same or comparative result is 1, then selected SAPUF Stability Analysis of Structures, if same or comparative result is 0, then selected SAPUF structural instability, address mark in this, as reliable PUF stores,

Produce structure to AES key and apply zero-bias, namely Δ V is 0, then, controller, with reference to the address being stored in advance in the reliable PUF in the middle of SRAM, reads the code value of respective number, exports as key from SAPUF array, and according to key length, determine the key taking out corresponding length.