JPH03180890A - Data driver of matrix type display device - Google Patents

Abstract

PURPOSE:To select and switch sampling modes and to make the data driver economical by applying a specific shift clock signal to plural shift registers. CONSTITUTION:The shift registers 5-1 - 5-n apply sampling pulses to a sample holding circuit 4. The circuit 4 samples display data corresponding to a data bus 1 and applies a data voltage to the bus 1. A selecting circuit 6 selects a simultaneous sampling mode or sequential sampling mode. The simultaneous sampling mode is selected by applying the in-phase shift clock signals to the shift registers 5-1 - 5-n respectively. Further, the sequential sampling mode is selected by applying out-of-phase shift clock signals. Thus, the modes can be switched by selecting the shift clocks to obtain the economical data driver.

Description

[Detailed Description of the Invention] [Summary] An economical data driver that enables switching between simultaneous sampling mode and sequential sampling mode, regarding a data driver for a matrix type display device that applies a data voltage to a data bus of a display panel. In a data driver of a matrix type display device that applies a data voltage to the data bus of a matrix type display panel in which a data bus and a scan canvas are arranged orthogonally,
Sampling the display data corresponding to the data bus,
A sample-and-hold circuit that applies a data voltage to the data bus, a plurality of shift registers that apply sampling pulses to the sample-and-hold circuit, and shift clock signals of the same phase are applied to each of the plurality of shift registers at the same time. The present invention includes a selection circuit for selecting whether to set the sampling mode or to set the sampling mode sequentially by adding shift clock signals of different phases.

[Industrial application field]

The present invention relates to a data driver for a matrix display device that applies a data voltage to a data bus of a display panel.

A matrix type display panel is one in which a data bus and a scan canvas are arranged orthogonally, and a liquid crystal display panel in which a liquid crystal is interposed at the intersection of the data bus and the scan canvas is generally used as a display medium.

There is also an active matrix type in which a switching element such as a thin film transistor is installed at the intersection of the data bus and the scan canvas, and a simple matrix type in which such a switching element is not installed.Also, a color filter is installed to enable full color display. T! The precepts are also known.

This type of matrix display panel is thin, so
It is applied to display devices such as small color television receivers and Birzl computers. Development is also progressing as a full-color video projector.

Therefore, a data driver for driving a matrix display panel is required to be compatible with various uses.

[Prior Art] For example, as shown in FIG. 8, a data driver of a conventional matrix type display device includes a sample and hold circuit 54.
The sample and hold circuit 54 includes a sampling switch 56, a sampling capacitor 57, and a buffer amplifier 58.

The matrix display panel 53 is constructed by interposing a display medium such as a liquid crystal at the intersection of a data bus 51 and a scan canvas 52 arranged orthogonally, and a scan voltage is sequentially applied to the scan canvas 52 from a scan driver 59. .

Also, a case is shown in which R (red), G (green), and B (blue) signals are input as display data, and shift data S is added to the shift register 55 in synchronization with the display data synchronization signal. The signals are sequentially shifted by the shift clock signal CLK and output from each stage of the shift register 55 as sampling pulses. The sampling switch 56 is turned on by this sampling pulse, and the display data is applied to the sampling capacitor 57 and sampled and held. This sampled and held voltage is applied as a data voltage to the data bus 51 via the buffer amplifier 58.

Images and characters are displayed by the combination of display cells at the intersections of the data bus 51 to which the data voltage is applied and the scan canvas 52 to which the scan voltage is applied.

FIG. 9 is an explanatory diagram of the sampling operation, in which analog R, G signals are separated from a composite video signal such as a color video signal.
, B signal is sequentially sampled, °“l”
The shift data SI of 31.degree. S2゜33, . . . become "1°゛, so R, G.

The level of the circle mark of the B signal will be sampled and held.

Figure 10 shows synchronization signals SYN, R, G,
The R, G, and B signals are shown to be at the same level, but the level corresponds to the brightness. Furthermore, when R, G, and B signals of the same level are obtained at the same time, that is, when indicated by R10+B, white is displayed. When sequentially sampling such R, G, and B signals, a correct sample-and-hold output signal may not be obtained due to waveform transmission distortion.

For example, as shown in FIG. 11, the signals shown in RGB are
The output signals si, s2, and S3 of the shift register 55 cause the time t1. t2. When sampling at t3,
Although it is possible to obtain sample-and-hold output signals at predetermined levels for each, RGB
If waveform distortion occurs as shown in the waveform shown by ', time L
The level of the sample-and-hold output signal at No. 1 is lower than that of an RGB signal in which waveform rounding does not occur. For example, when sampling and holding an R signal at time t1, a G signal at time t2, and a B signal at time t3, the level of the sample and hold output signal of the R signal becomes low, and correct color display cannot be performed.

Therefore, conventionally, a configuration has been used in which R, G, and B signals are sampled simultaneously. That is, for a signal such as an RGB° signal in which a waveform is rounded, the R, G, and B signals are simultaneously sampled and held at a time when the signal reaches a predetermined level, such as time t2.

[Problem that the invention seeks to solve]

Data drivers for conventional matrix-type display devices have either a sequential sampling or simultaneous sampling configuration, and as mentioned above, in sequential sampling type data drivers, waveform It is difficult to obtain accurate sample and hold output signals due to the accent, and the sampling interval becomes long in data drivers that use simultaneous sampling, so the resolution is low when displaying two colors such as black and white. There is a drawback.

Furthermore, as the display capacity of the matrix display panel 53 increases, the number of data buses 51 increases, and it is necessary to increase the frequency of the shift clock signal CLK of the shift register 55. However, since there is a limit to increasing the frequency, there is a drawback that there is also a limit to the display capacity of the matrix type display panel that can be driven by the data driver.

An object of the present invention is to provide an economical data driver that allows switching between simultaneous sampling mode and sequential sampling mode.

[Means to solve the problem]

A data driver for a matrix type display device according to the present invention is provided with a plurality of shift registers, and will be explained with reference to FIG.

In the data driver of the matrix type display device that applies a data voltage to the data bus l of the matrix type display panel 3 in which the data bus 1 and the scan canvas 2 are arranged orthogonally, display data is sampled in correspondence with the data bus 1. a sample hold circuit 4 that applies a data voltage to the data bus l; and a plurality of shift registers 5-1 to 5-n that apply sample pulses to the sample hold circuit 4.
Then, whether to apply shift clock signals of the same phase to the plural shift registers 5-1 to 5-n to set the simultaneous sampling mode, or to set the sequential sampling mode by adding shift clock signals of different phases to each of the plurality of shift registers 5-1 to 5-n. , and 7 is a scan driver that sequentially selects the scan canvas 2 and applies a scan voltage.

[Effect]

The selection circuit 6 selects a plurality of shift registers 5-1 to 5-.
Shift clock signals of the same phase or different phases are selected and added to n, and the output signals of each stage of the plurality of shift registers 5-1 to 5-n are sent to the sample and hold circuit 4 as sampling pulses. The display data is sampled, and the hold output signal is applied to the data bus 1 of the matrix display panel 3 as a data voltage.
is applied to

Each of the shift registers 5-1 to 5-n only needs to operate with a shift clock signal having a frequency of 1/n compared to the conventional example using one shift register.
A data driver for the matrix type display panel 3 having a large display capacity can be easily configured.

Furthermore, if shift clock signals of the same phase are applied to a plurality of shift registers 5-1 to 5-n, the output signals of each stage of the plurality of shift registers 5-1 to 5-n will have the same phase. , display data can be sampled simultaneously in the sample and hold circuit 4. That is, simultaneous sampling mode can be used. Furthermore, when shift clock signals of different phases are applied to the plurality of shift registers 5-1 to 5-n, the shift registers 5-1 to 5-n
Since the output signals of the stages -1 to 5-n have different phases, the sample and hold circuit 4 can sequentially sample the display data.

That is, the mode becomes sequential sampling mode. Therefore, by selecting the shift clock signal by the selection circuit 6 and applying it to the plurality of shift registers 5-1 to 5-n, display data can be sampled in either the simultaneous sampling mode or the sequential sampling mode. Thus, a data voltage can be applied to the data bus 1.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention, and 1
1 is a data bus, 12 is a scan canvas, 13 is a matrix type display panel, 14 is a sample hold circuit, 15-
1 to 15-3 are shift registers, 16 is a selection circuit for selecting shift clock signals CLKI to CLK3, 17 is a scan driver, SWI to SWm are sampling switches made of transistors, etc., 01 to Cm are sampling capacitors, and BFI to BFm are It is a buffer amplifier.

This embodiment shows a case where shift registers 15-1 to 15-3 are provided for R, G, and B signals, and each shift register 15-1 to 15-3 has an m/3 stage configuration. be. The matrix type display panel 13 is composed of m data buses 11 and scan canvases 12, and is configured with mXk display cells and is, for example, an active matrix liquid crystal display panel provided with R, G, and B color filters. It can be a display panel.

The scan driver 17 has a configuration that sequentially selects the scan canvases 12 of the book in synchronization with the synchronization signal of the display data and applies a scan voltage. A data voltage corresponding to display data is simultaneously applied to the data bus 11.

This sample hold circuit 14 includes a shift register 15
-1 to 15-3, a sampling switch SW1-3Wm consisting of a transistor or the like driven by the output signal;
Sampling capacitor C1 for sample and hold
-Cm and a buffer amplifier BFI that outputs the data voltage.
~BFm.

In addition, the shift registers 15-1 to 15-3 shift the shift data Sl synchronized with the synchronization signal of the display data according to the shift clock signal, and use the output signals of each stage as sampling pulses to pass through the sampling switches SWI to SWm of the sample and hold circuit 14. For example,
The output signal of the first stage of the shift register 15-1 is the sampling switch SW1. The output signal of the second stage is the sampling switch SW4. The output signal of the third stage is the sampling switch SW7 (not shown),..., the final stage. The output signal of the m/3rd stage of the shift register 15-2 is applied to the sampling switch SWm-2, the output signal of the first stage of the shift register 15-2 is applied to the sampling switch SW2, and the output signal of the second stage is applied to the sampling switch SW5 (not shown). omitted),・
...The output signals of the m/3rd stage of the final stage are respectively applied to the sampling switch SWm-1. Also, the output signal of the first stage of the shift register 15-3 is sent to the sampling switch S.
W3. ..., the output signals of the m/3rd stage of the final stage are respectively applied to the sampling switch SWm.

In addition, shift clock signals CLK1 to CLK3 having different phases are input to the selection circuit 16, and when one of them, for example, shift clock signal CLK1, is selected and added to each shift register 15-1 to 15-3, each shift clock signal CLK1 to CLK3 is inputted to the selection circuit 16. The output signals of the corresponding stages of registers 15-l to 15-3 have the same phase, for example, the first shift clock signal CL.
K1 causes the output signal of the first stage of each shift register 15-1-15-3 to be sent to the sampling switches SWI, SW.
2. It is added to SW3 and turns on at the same time, R2O, B
When the signals are simultaneously sampled and held by the sampling capacitors C1, C2, and C3, and the next shift clock signal CLK1 is applied, the output signal of the second stage of each shift register 15-1-15-3 is output to the sampling switch. SW4, SW5. It is added to SW6 (not shown) and turned on at the same time. Therefore, it becomes a simultaneous sampling mode.

In addition, the selection circuit 16 selects shift clock signals CLK1 to CLK1 to CLK1.
When LK3 is added to each of the shift registers 15-1 to 15-3, the output signals of the corresponding stages of each shift register 15-1 to 15-3 have different phases. For example, the first shift clock signals CLKI to CLK3 are When applied to the sequential shift registers 15-l to 15-3, the output signals of the first stage of the sequential shift registers 15-1 to 15-3 are applied to the sampling switches SWI to SW3, and the R signal is sampled by the sampling switch SW1. Then, the G signal is sampled by the sampling switch SW2, and then the B signal is sampled by the sampling switch SW2.
3, and each sample is sequentially sampled at a different phase. That is, the mode becomes sequential sampling mode.

FIG. 3 is an explanatory diagram of the simultaneous sampling mode, (a
) is display data, (b) is shift data S I , (C
) to (e) show shift clock signals applied to shift registers 15-1 to 15-3, and (f) to (b) show sample and hold output signals. Each shift register 15-1~
Shift clock signals of the same phase shown in (C) to (e) are added to 15-3, and the shift data 31 shown in (b) is
are sequentially shifted to each shift register 15-l to 15-1.
R, G by the output signals of each stage of -3.

Simultaneous sampling of B is performed, and sample-and-hold output signals shown in (f) to (h) are obtained.

FIG. 4 is an explanatory diagram of the sequential sampling mode, (a
) is display data, (b) is shift data S I , (C
) to (e) indicate shift clock signals applied to shift registers 15-1 to 15-3, and (f) to Q1) indicate sample and hold output signals. Each shift register 15-1 to 15
Since the shift clock signals having different phases shown in (C) to (e) are applied to shift register 1
The output signals of each stage of 5-1 to 15-3 also have different phases, R, G, B, R.

It will be sampled in the order of G, B, . . . That is, the mode becomes sequential sampling mode.

Therefore, by selecting the shift clock signal by the selection circuit 16, it is possible to apply the present invention to either the simultaneous sampling mode or the sequential sampling mode. In addition, since the shift clock signal can be used at 1/3 the frequency of the conventional example, if a shift register with the same operating speed as the conventional example is used, the number of data buses 11 will be reduced to 3.
This means that it is possible to easily drive a matrix type display panel that is twice as large.

FIG. 5 is a block diagram of main parts of another embodiment of the present invention,
21 is a data bus, 22 is a scan canvas, 23 is a matrix type display panel, 24.34 is a sample hold circuit, 25-1 to 25-3, 35-1 to 35-3 are shift registers, and 26.36 is a selection circuit. , 27 is a scan driver.

Assuming that the data bus 21 is 21-1 to 21-m from the left,
Odd numbered data buses 21-1, 21-3°, . . . are connected to the sample and hold circuit 24, and even numbered data buses 21-2, 21-4, . ... are connected to the sample and hold circuit 34.

In addition, shift clock signals CLKI to CLK3. which are input to the selection circuits 26.36. CLKI' to CLK3'' have different phases, and in the case of simultaneous sampling mode, the shift registers 25-1.25-3.3
The selection circuit 26.36 selects the shift clock signals so that the shift clock signals applied to the shift registers 5-2 and 5-2 have the same phase, and the shift clock signals applied to the shift registers 25-2.35-1.35-3 have the same phase. A selection is made. In that case, the display data input to the sample-and-hold circuit 24.34 is transferred to, for example, the data bus 21-1.
R, G corresponding to 21-2.21-3.

B signals are simultaneously sampled and then the data bus 21
-4.21-5.21-6 corresponding R,G.

The B signal is sampled at the same time. In addition, in the case of sequential sampling mode, shift registers 25-1 to 25-
3. The selection circuits 26 and 36 are arranged so that the shift clock signals applied to 35-1 to 35-3 all have different phases.
The shift clock signal is selected by.

FIG. 6 is an explanatory diagram of the simultaneous sampling mode, (a
) is display data, (b) is shift data S I , (C
) to (e) are from the selection circuit 26 to the shift register 25-1.
Shift black signal applied to ~25-3, (f) ~
(h) is a sample-and-hold output signal from the sample-and-hold circuit 24, (1) to (g) are shift clock signals applied from the selection circuit 36 to shift registers 35-1 to 35-3, and (f) to (n) are Sample hold circuit 34
shows the sample-and-hold output signal.

The display data RGB 1 shown in (a) D is (c), (
The shift data Sl is shifted by the shift clock signals shown in e) and (j), and the shift registers 25-1.
25-3. Since it is sampled by the output signal of the first stage of 35-2, R1 of (f), 01), (m),
B1. The sample and hold output signal is shown as G1, and (
d).

The shift data Sl is shifted by the shift clock signals shown in (i) and (k), and the shift register 25-2
．． 35-1.Since it is sampled by the first stage output signal of 35-3, G2°R2 of (g), 1), and (b)
, B2.

FIG. 7 is an explanatory diagram of the sequential sampling mode, (a
) is display data, (b) is shift data S I , (C
) to (e) are from the selection circuit 24 to the shift register 25-1.
Shift clock signal applied to ~25-3, (f) ~
Φ) is a sample-and-hold output signal from the sample-and-hold circuit 24, (i) to (g) are shift clock signals applied from the selection circuit 36 to shift registers 35-1 to 35-3, and (1) to (n) are sample-and-hold signals. A sample and hold output signal by circuit 34 is shown.

As shown in (C) to (e) and (i) to (k), the shift clock signals applied to shift registers 25-1 to 25-3.35-1 to 35-3 have different phases. Yes, shift register 25-1.25-3.35
The display data Rt, Gt, B+ signals shown in (a) are sequentially sampled by the first stage output signal of -2, and (
The sample and hold output signals shown in f), (i,), and (g) are obtained. Also shift register 25-2.35-1.35
The display data Rt, Gz, and Bx signals shown in (a) are sequentially sampled by the first stage output signal of -3, and (
The sample and hold output signals are as shown in (e), (h), and (n).

Therefore, by selecting the shift clock signal using the selection circuits 26 and 36, it is possible to select either the simultaneous sampling mode or the sequential sampling mode.

The present invention is not limited to the above-described embodiments, and can be modified in various ways. For example, by doubling the number of shift registers, the frequency of the shift clock signal can be further halved. You can also.

Furthermore, since the shift register does not shift display data, but only shifts 1-bit shift data Sl, it can be constructed with a relatively simple structure.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of shift registers 5-1 to 5-n, and each shift register 5-1 to 5-n.
When a shift clock signal of the same phase is added to -n, the output signals of each stage of each shift register 5-1 to 5-n have the same phase, so a simultaneous sampling mode is established, and each shift register 5-1 to 5-n -n, each shift register 5-1 to 5
Since the output signals of each stage of −n have different phases, the sequential sampling mode is set. Such a mode can be switched by selecting the aforementioned shift clock signal using the selection circuit 6.

Therefore, if the frequency of the shift clock signal is the same as that of the conventional example, it is possible to drive the matrix display panel 3 having data buses 1 times the number of shift registers 5-1 to 5-n. It is possible to cope with an increase in display capacity. Furthermore, since the data driver having the same configuration can be applied to both simultaneous sampling mode and sequential sampling mode, there is an advantage that costs can be reduced through mass production.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of essential parts of an embodiment of the present invention, FIG. 3 is an explanatory diagram of simultaneous sampling mode, and FIG. 4 is an explanatory diagram of sequential sampling mode.
Fig. 5 is a block diagram of main parts of another embodiment of the present invention, Fig. 6 is an explanatory diagram of simultaneous sampling mode, Fig. 7 is an explanatory diagram of sequential sampling mode, and Fig. 8 is a block diagram of main parts of a conventional example. , Fig. 9 is an explanatory diagram of sampling operation, Fig. 1O is R
An explanatory diagram of the GB signal, and FIG. 11 is an explanatory diagram of sequential sampling of the ROB signal. 1 is a data bus, 2 is a scan canvas, 3 is a matrix type display panel, 4 is a sample hold circuit, 5-1 to 5-
n is a shift register, 6 is a selection circuit, and 7 is a scan driver.

Claims (1)

[Claims] Data of a matrix type display device that applies a data voltage to the data bus (1) of a matrix type display panel (3) in which a data bus (1) and a scan canvas (2) are arranged orthogonally. a sample and hold circuit (4) in the driver that samples display data corresponding to the data bus (1) and applies a data voltage to the data bus (1);
A plurality of shift registers (5-1 to 5-n) apply sampling pulses to the sample hold circuit (4), and a plurality of shift registers (5-1 to 5-n) each having the same phase. A matrix type display device comprising a selection circuit (6) for selecting whether to set a simultaneous sampling mode by adding a shift clock signal or to set a sequential sampling mode by adding shift clock signals of different phases. data driver.