JPH0675204A - Active matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To make a large-capacity and large-screen display of excellent picture quality at high yield. CONSTITUTION:Shift registers SRA, SRB,... which constitute a driver 3 driving source bus lines S1-SN are provided by as many as K systems and L switch means 32 are controlled simultaneously with one output of the shift registers SRA, SRB,... of the respective systems to generate clock signals PHIA and PHIBbar, and PHIB and PHIBbar which shift in period by L times as long as a sampling period and have periods 2KL times as long as the sampling period. The L switch means 32 which are controlled simultaneously are connected to video signal lines 31a and 31b of different L systems. Then L kind of video signals Video1, Video2... generated by sampling a source video signal in cycles L times as long as the sampling period while the sampling phase is shifted by the sampling period are applied to video signal lines 31 and 3lb.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit-embedded active matrix type liquid crystal display device in which a drive circuit is composed of, for example, polycrystalline silicon (hereinafter referred to as "polysilicon").

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device integrated with a drive circuit, it is necessary to form a drive circuit such as a source driver or a gate driver on a transparent insulating substrate such as glass or quartz integrally with a display section. There is usually a polysilicon thin film MOS transistor (hereinafter,
A driving circuit is configured by “polysilicon TFT”. However, compared to a drive circuit using single crystal silicon, the polysilicon TFT has a drawback that the operation speed is very slow. In particular, in the source driver for driving the source bus line of the display unit, when a large screen and large capacity display is performed, the shift register constituting the source driver lacks the operation speed, so that it is configured with a polysilicon TFT. Various methods for driving the shift register within a range not exceeding the operating speed have been studied.

FIG. 5 shows an active matrix type liquid crystal display device with a built-in drive circuit, which uses two systems of shift registers, which is an example of a method of reducing the operation speed required for the shift registers. The structure of a conventional active matrix type liquid crystal display device with a built-in drive circuit will be described with reference to FIG.

As shown in the figure, in this liquid crystal display device, source bus lines S1 _{1 to} S1 _N and gate bus lines G1 _{1 to} G1 _M are vertically and horizontally arranged on a transparent insulating substrate 101 to form a display section 102. ing. On the substrate 101 to the display unit 102 is formed, on the one end of the source bus lines S1 ₁ ~S1 _N, a source driver 103 for driving the source bus lines S1 ₁ ~S1 _N is formed, the gate bus lines G1 ₁
At one end of the ~G1 _M, the gate driver 104 for driving the gate bus lines G1 ₁ ~G1 _M is formed.

In the display section 102, the source bus line S1 _n (1 ≦ n ≦ N) and the gate bus line G1 _m (1 ≦ m ≦
The element surrounded by M) and is a unit of display.
Becomes

FIG. 6 shows an equivalent circuit of an example of one picture element 120. As shown in the figure, the pixel 120 is a thin film transistor 1 that functions as a switching element formed at the intersection of the source bus line S1 _n and the gate bus line G1 _m.
20a and the video signal potential D1 ₁ applied from the source bus line S1 _n, D1 _2, and the pixel electrode 120b for driving the liquid crystal capacitor by applying a ..., charge holding capacitor provided in parallel with the pixel electrode 120b And 120c.

As shown in FIG. 5, the source driver 103 is a video signal (hereinafter referred to as "original video signal") Vid which is an original signal applied to the source bus lines S1 _{1 to} S1 _N.
A video signal line 131 for inputting eo, an analog switch 132 and a sampling capacitor 133 formed between the video signal line 131 and each source bus line S1 _{1 to} S1 _N, and an operation of the analog switch 132 are controlled. Two shift registers SRA1 and SRB
It is composed of 1 and 1. The analog switch 132 is for sampling the video signal Video from the video signal line 131. Sampling capacitors 133, sampled video signal potentials D1 _1, D
1 _2, common ... and the source bus lines S1 ₁ ~S1 _N electrode 134
It is for holding between and. Shift register S
RA1 is connected to the odd-numbered source bus lines S1 _{1 to} S1 _N−1 , and the shift register SRB1 is connected to the even-numbered source bus lines S1 _{2 to} S1 _N. The outputs of the shift registers SRA1 and SRB1 of each system control the operation (opening / closing) of the analog switch 132 corresponding to each source bus line S1 _{1 to} S1 _N. Each of the above parts constituting the source driver 103 is formed of a polysilicon thin film or the like on the same substrate 101.

FIG. 7 shows the source driver 10 shown in FIG.
3 shows a timing chart at the time of driving No. 3. The operation of the source driver 103 will be described with reference to FIGS.

Two systems of shift registers SRA1 and SRB
1 is controlled by the start signal SP1 shown in FIG. The shift register SRA1 has clock signals ΦA1, Φ
The shift register SRB1 is controlled by ABar1 and is controlled by clock signals ΦB1 and ΦBBar1. As the clock signal ΦA1 and the clock signal ΦB1, signals whose phases are shifted by ¼ cycle (sampling period t ₀ ) are input. These clock signals ΦA1, ΦABar1, ΦB1, Φ
Two shift registers SRA1 and SR by BBar1
For example, as shown in SRA1 ₁ and SRB1 ₁ shown in FIG. 7, B1 sequentially outputs waveforms whose phases are shifted by the sampling period t ₀ to the analog switch 132. The analog switch 132 is a shift register SRA.
1, the outputs of SRB1 are made conductive during the period of high level, and these shift registers SRA1, SR
The output of B1 causes the analog switch 132 to conduct for a period of 4t ₀ . While the analog switch 132 is conducting, the original video signal V is supplied to the sampling capacitor 133.
Video is sampled and the source bus lines S1 _{1 to} S1 _N are sequentially driven. Here, the analog switch 132 is 4t
_It has been conducting for a period of ₀ , but the previous source bus line S1
Analog switches 132 and 3 connected to _{1 to} S1 _N
Since the period t ₀ is overlapped and conductive, the result is that the original video signal sampled during the last period t ₀ (a period that does not overlap the previous source bus lines S1 _{1 to} S1 _N ). Video will be sampled by the sampling capacitor 133. That is, by driving the two systems of shift registers SRA1 and SRB1 in parallel, the original video signal Video shifted by the sampling period t ₀ is sequentially sampled in the sampling capacitor 133,
The sampled video signal potentials D1 ₁ , D1 ₂ , ...
The voltage is applied to the corresponding source bus lines S1 _{1 to} S1 _N. Since each shift register SRA1 and SRB1 is driven at a cycle four times as long as the sampling period t ₀ , the operation speed of each shift register SRA1 and SRB1 can be reduced to ¼.

The above-mentioned active matrix type liquid crystal display device integrated with a drive circuit is a case where two systems of shift registers are driven in parallel. When a K (K is an integer) system of shift registers is driven in parallel, the shift is performed. The operation speed of the register can be reduced to 1 / 2K.

[0011]

As described above, the operating speed of the shift register can be reduced by driving the shift registers of a plurality of systems in parallel, but the true sampling period for sampling the original video signal Video. There is no change in t ₀ . As a result, in the case of driving a large-capacity / large-screen liquid crystal display device, the analog switch is required to operate at high speed in order to take a sufficient sampling period t ₀ , and the display period is short due to the shortage of the sampling period t _0. There is a problem of deterioration in display quality such as a decrease in resolution, a decrease in contrast, and display unevenness.

Further, even if a plurality of systems of shift registers are driven in parallel, the total number of outputs of the shift registers is required to be the number of source bus lines, and as the number of shift registers driven in parallel increases, the number of input signal lines increases. (Clock signal ΦA
There is a problem that the number of wirings such as 1 and ΦABar1) increases and the area of the shift register portion increases and the yield decreases.

The present invention has been made to solve the above-mentioned problems of the prior art, and aims to improve the image quality by reducing the operation speed of the shift register and by taking the sampling period of the video signal sufficiently long. Not only is it possible to reduce the number of shift register outputs (the number of transistors that make up the shift register) and the number of wiring lines, but also to reduce the area occupied by the shift register.
It is an object of the present invention to provide an active matrix type liquid crystal display device capable of displaying a large capacity and a large screen with high yield.

[0014]

An active matrix type liquid crystal display device according to the present invention has a plurality of gate bus lines and a plurality of source bus lines arranged on a substrate so as to be orthogonal to each other. A pixel is formed in a region surrounded by the gate bus line and two adjacent source bus lines, and a gate driver that drives the gate bus line and a source driver that drives the source bus line are formed. In the active matrix type liquid crystal display device, a sample and hold circuit is formed in each of the source bus lines, and each sample and hold circuit has one L (integer of 2 or more) adjacent to each other. Of the sample and hold circuits are sequentially connected to each of the L system video signal lines, and A shift register for controlling the switch means provided in the hold circuit is provided in a K (integer of 2 or more) system, and one set of switch means is made to correspond to one system of shift registers. The source driver is configured to be driven by a shift register of another system, and the sampling phase is shifted to each of the video signal lines of the L system by a sampling period obtained by dividing the effective horizontal scanning period by the number of effective source bus lines. Then, L kinds of video signals obtained by sampling the video signal which is the original signal at a cycle of L times the sampling period are applied with the phases aligned, and the shift register is L times longer than the sampling period for each system. A clock signal whose period is shifted and whose period is 2KL times the sampling period is given. The purpose is achieved.

The output signal level difference is detected by the correction circuit which detects the output signal level difference between the L type video signals and performs the gain correction and the offset correction based on the output signal level difference. And the offset may be 20 mV or less.

The pixel may include a charge holding capacitor, and the capacitance of the sample-and-hold circuit may be 10 times or more the charge holding capacitor.

A thin film transistor may be provided as a switching element for driving the picture element, and the thin film transistor, the gate driver and the source driver may be made of polycrystalline silicon.

[0018]

In the present invention, there are provided K systems of shift registers constituting a source driver for driving the source bus lines, and L outputs are simultaneously controlled by one output of the shift registers of each system so that the shift registers of the shift registers can be controlled simultaneously. A clock signal having a period L times as long as the sampling period and a period 2KL times as long as the sampling period is given to each system. As a result, the switch means is brought into the conductive state for a period of 2KL, and the conductive period is shifted by L times the sampling period between the adjacent switch means.

The L switch means controlled at the same time are connected to video signal lines of different L systems respectively, and the video signal lines are shifted in sampling phase by a sampling period to obtain L times the sampling period. The L kinds of video signals obtained by sampling the original video signal in the cycle are applied with their phases aligned. As a result, a signal obtained by sampling the original video signal in the sampling period is applied to the source bus line.

[0020]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows an active matrix type liquid crystal display device with a built-in drive circuit using two lines of shift registers, which is an embodiment of the present invention. The structure of an active matrix type liquid crystal display device with a built-in drive circuit according to the present embodiment will be described with reference to FIG.

[0022] As illustrated, the liquid crystal display device on the transparent insulating substrate 1, the source bus lines S ₁ to S _N and the gate bus line G ₁ ~G _M are wired vertically and horizontally to the display portion 2 ing. On the substrate 1 on which the display unit 2 is formed, one of the source bus lines S _{1 to SN} is connected to the source bus line S 1.
₁ to S _N source driver 3 for driving the formed, at one end of the gate bus lines G ₁ ~G _M, the gate driver 4 for driving the gate bus lines G ₁ ~G _M is formed .

In the display unit 2, the source bus line S _n
(1 ≦ n ≦ N) and gate bus line G _m (1 ≦ m ≦ M)
The portion surrounded by and becomes the picture element 20 which is one unit of display. The picture element 20 has the same configuration as the picture element shown in FIG. 6, and includes a thin film transistor 20a functioning as a switching element formed at the intersection of the source bus line S _n and the gate bus line G _m , and the source bus line S. It is composed of a picture element electrode 20b for driving the liquid crystal capacity by applying video signal potentials D ₁ , D ₂ , ... _Applied from _n, and a charge holding capacity 20c provided in parallel with the picture element electrode 20b.

As shown in FIG. 1, the source driver 3 has a video signal V applied to the source bus lines S _{1 to} S _N.
Video signal lines 31a and 31b of two systems for inputting video1 and video2, and video signal lines 31a and 3
Analog switch 32 and sampling capacitor 33 formed between 1b and each source bus line S _{1 to SN.}
Sample-and-hold circuit consisting of two shift registers SR for controlling the operation of the analog switch 32
It is composed of A and SRB. The odd-numbered source bus lines S _{1 to} S _N-1 are connected to the video signal line 31a and the video signal Video1 is applied. Even-numbered source bus line S ₂ to S _N is connected to the video signal line 31b, the video signal Video2 is applied. The analog switch 32 is for sampling the video signals Video1 and Video2 from the video signal lines 31a and 31b. The sampling capacitor 33 holds the sampled video signal potentials D ₁ , D ₂ , ... Between the source bus lines S _{1 to SN} and the common electrode 34. Two lines of shift registers SRA and SRB
Are alternately connected to two source bus lines S _{1 to} S _N. The outputs of the shift registers SRA and SRB of each system control the operation (opening / closing) of the analog switch 32 corresponding to each two source bus lines S _{1 to SN} . Each part of the above source driver 3 is formed on the same substrate 1 by a polysilicon thin film or the like.

In this embodiment, the drive circuits such as the source driver 3 and the gate driver 4 are integrally formed on the same substrate 1 as the display unit 2. However, the drive circuits are formed separately from the display unit 2 and the display unit 2 is formed. It may be configured to be attached to No. 2.

FIG. 2 shows a timing chart when the source driver 3 shown in FIG. 1 is driven. The operation when the source driver 3 is driven will be described based on FIGS. 1 and 2.

The activation of the two shift registers SRA and SRB is controlled by the start signal SP shown in FIG. The shift register SRA is controlled by clock signals ΦA and ΦABar, and the shift register SRB is clock signal Φ.
B, controlled by ΦBBar. As the clock signal ΦA and the clock signal ΦB, signals whose phases are shifted by ¼ cycle (twice the sampling period t ₀ which is a value obtained by dividing the effective horizontal scanning period by the number of effective source bus lines) are input. It
Due to these clock signals ΦA, ΦABar, ΦB, ΦBBar, the two systems of shift registers SRA and SRB are, for example, as shown in SRA ₁ and SRB ₁ shown in FIG.
Waveforms whose phases are shifted by the sampling period 2t ₀ are sequentially output to the analog switch 32.

Two systems of video signal lines 31a and 31b
Are video signals Video1 and Vid obtained by sampling the original video signal Video by shifting the phase for the period t ₀ , respectively.
A signal for outputting eo2 at the same timing for a period of 2t ₀ is input. A method of creating the video signals Video 1 and Video 2 will be described later.

Here, two analog switches 32 controlled by one output of the shift registers SRA and SRB.
Are different video signal lines 31a and 31b, respectively.
, And simultaneously sample video signal potentials D ₁ , D ₂ , ... Having different phases like the video signals Video 1 and Video 2 shown in FIG. The analog switch 32 is made conductive during the period when the outputs of the shift registers SRA and SRB are at the high level, and one output of the shift registers SRA and SRB simultaneously makes the two analog switches 32 conductive for the period 8t ₀ . To do. While the analog switch 32 is conducting, the video signal Vid
EO1, sampling the Video2 in the sampling capacitor 33, sequentially driving two by two source bus lines S ₁ to S _N. The analog switch 32 is connected to the source bus lines S _{1 to} S _N two lines before.
Because it is connected the same video signal line 31a, and 31b and conducts overlap period of the analog switch 32 and 6t ₀ connected to the two previous source bus lines S ₁ to S _N. As a result, the video signals Video1 and Video2 sampled during the last period 2t ₀ (a period not overlapping the two source bus lines S _{1 to} S _N two lines before) are sampled by the sampling capacitor 33.

By driving as described above, the video signal potentials D ₁ , D ₂ , ... Which are shifted by the sampling period t ₀ are applied to the source bus lines S _{1 to SN} , and the display image of the display image is displayed. The resolution does not decrease. Moreover, the shift registers SRA and SRB of each system are set to the sampling period t _0.
Since it is driven at a cycle of 8 times,
The operation speed of A and SRB can be reduced to 1/8, and the true sampling period assigned to one analog switch 32 becomes as long as 2t ₀ .

Also, two systems of video signals Video1 and Vid
When eo2 is used, the total number of outputs of the shift registers SRA and SRB is ₁ of the total number of source bus lines S _{1 to SN.}
It becomes possible to drive with the shift register SR
The area occupied by A and SRB on the substrate 1 can be reduced to about 1/2. As a result, the source driver 3 can be manufactured with high yield.

FIG. 3 shows an example of a video signal generating circuit for converting the original video signal Video into the two systems of video signals Video1 and Video2 of this embodiment. Referring to FIG.
The configuration of this video signal generation circuit will be described.

As shown in the figure, the original video signal Video is input, the input original video signal Video is A / D converted, and A is sampled in the sampling period t _0.
The gamma correction circuit 42 is connected to the output side of the / D conversion circuit 41. The gamma correction circuit 42 is a circuit that performs non-linear conversion of the output from the A / D conversion circuit 41 so as to correct the luminance of the original video signal Video in the liquid crystal display device. On the output side of the gamma correction circuit 42, there are two systems of data latch circuits 43b and 43 for latching the output signal of the gamma correction circuit.
c is connected. A buffer amplifier circuit 45b is connected to the output side of the data latch circuit 43b via a D / A conversion circuit 44b, and a buffer amplifier circuit 45b is connected to the output side of the data latch circuit 43c via a D / A conversion circuit 44c. The circuit 45c is connected. Video signals Video1 and Vid output from the buffer amplifier circuits 45b and 45c
Based on eo2, two video signals Video1 and Vid
A gain / offset correction circuit 46 for correcting the level difference of eo2 is provided.

FIG. 4 is a timing chart showing the operation of the video signal generating circuit. The operation of this video signal generating circuit will be described with reference to FIG.

First, the original video signal Video is input to the A / D conversion circuit 41, and the input original video signal Video is A / D converted by the A / D conversion circuit 41, as shown in FIG. Sampling is performed in the sampling period t ₀ , and video signal potentials D ₁ , D ₂ , ... Are output. The output from the A / D conversion circuit 41 is input to the gamma correction circuit 42 and gamma corrected.

Next, the output of the gamma correction circuit 42 is input to the two systems of data latch circuits 43b and 43c. Two
In the data latch circuit 43b, 43c of the system, the clock signal CKb and CKc has only the phase shift sampling period t _0, the video signal potential D _1, D _2, ... is twice the period latch sampling period t _0. At this time, the odd-numbered video signal potentials D ₁ , D ₃ , ... Are latched in the data latch circuit 43b as shown in the figure, and the even-numbered video signal potential D ₂ in the data latch circuit 43c as shown in the figure. , D ₄ , ... Are latched. The outputs of the two systems of data latch circuits 43b and 43c are input to the corresponding D / A conversion circuits 44b and 44c, respectively. D / A conversion circuit 4
4b and 44c are driven by the clock signal CKd,
As a result, between the two D / A conversion circuits 44b and 44c, the video signal potentials D ₁ , D ₂ , ..., Which are out of phase by the sampling period t ₀ , have the same timing, and the corresponding buffer amplifier circuits 45b and 45c, respectively. Is output to.

As described above, the above-mentioned two systems of video signals Video1 and Video2 are obtained.

Generally, two systems of video signals Video1 and V2 are used.
A difference in output signal level occurs between the video signals 2 due to variations in the characteristics of the D / A conversion circuits 44b and 44c and the buffer amplifier circuits 45b and 45c. Due to the level difference between the video signals Video 1 and Video 2, display unevenness occurs in the liquid crystal display device.

From an experiment conducted on a large number of subjects, if the level difference between the video signals Video1 and Video2 is 0.5% or less in the gain and the offset is about 20 mV or less, the display unevenness does not practically occur. I knew there was no problem.

Based on the result of this experiment, the level difference between the two video signals Video 1 and Video 2 is detected, and the gain / offset correction circuit 46 detects the video signal Video.
The gain and offset of Video 1 and Video 2 are corrected, and the level difference between the video signals Video 1 and Video 2 is adjusted so that the gain is 0.5% or less and the offset is 20 mV or less.

In the liquid crystal display device of this embodiment, the gains and offsets of the video signals Video1 and Video2 are corrected as described above, so that the display unevenness of the liquid crystal display device is eliminated.

The above two systems of video signals Video1
Video 2 can also be obtained by using an analog sample and hold circuit or the like. Also in this case, if necessary, the gain and offset are corrected to adjust the level difference between the video signals Video1 and Video2 so that the gain is 0.5% or less and the offset is 20 mV or less. The display unevenness of the device can be eliminated.

[0043] In addition, the sample and hold circuit capacitance (source bus lines S ₁ comprises a parasitic capacitance of to S _N) to the source bus lines S ₁ to S _N and the gate of the display portion 2 consisting of the analog switch 32 and the sampling capacitor 33 by the ratio of the capacitance of the charge holding capacitor 20c formed at each intersection of the bus lines G ₁ ~G _M, display unevenness of the liquid crystal display device has been known to occur. It is considered that this is because in the manufacturing process, variations in the pattern occur when patterning each portion by photolithography, which changes the charge transfer efficiency.

The display unevenness caused by the variation of the pattern is experimentally determined so that the capacity of the sample-and-hold circuit (including the parasitic capacity of the source bus lines S _{1 to SN} ) is equal to that of the charge holding capacity 20c of the display section 2. 10 compared to capacity
It has been found that the problem can be solved by setting the amount to be more than twice, preferably 50 times or more.

Therefore, in this embodiment, the capacity of the sample-and-hold circuit (including the parasitic capacity of the source bus lines S _{1 to SN} ) is set to 50 times the capacity of the charge holding capacity 20c of the display section 2. did. As a result, a uniform display without display unevenness was obtained.

In the above embodiment, the shift register S of two systems is used.
RA and SRB are driven in parallel and two systems of video signals Vid
In the case of inputting eo1 and Video2, the shift register of K (integer of 2 or more) system is driven in parallel and L
If the source bus line is driven by inputting a video signal of (integer of 2 or more) system and simultaneously controlling the switch means constituting the L sample and hold circuits, the operating speed of the shift register is 1. / 2KL
Can be reduced to Since the sampling period of the original video signal Video at this time is t ₀ , the resolution of the display image does not decrease, and the true sampling period assigned to the switch means is L times the sampling period t ₀ .

Further, the total number of outputs of the shift register can be driven by 1 / L of the total number of source bus lines, and the area occupied by the shift register on the substrate can be reduced to about 1 / L. As a result, the source driver can be manufactured with higher yield.

[0048]

As is apparent from the above description, according to the active matrix type liquid crystal display device of the present invention, the operation speed of the shift register constituting the source driver is reduced more than the sampling period of the original video signal. At the same time, the sampling period of the original video signal remains the same as before, and the sampling period can be set sufficiently long in the sample-and-hold circuit that constitutes the source driver, so that the display image quality is improved and the operation speed of the switching means is improved. It can be reduced.

Further, since the number of outputs of the shift register and the area occupied by the shift register can be reduced, not only the source driver can be formed with a high yield but also the transistor of the single crystal silicon can be formed. It is possible to construct a large-capacity, large-screen drive circuit integrated active matrix display device by using a material such as a polysilicon thin film having a slow operation speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an active matrix type liquid crystal display device which is an embodiment of the present invention.

FIG. 2 is a timing chart when the source driver shown in FIG. 1 operates.

FIG. 3 is a block diagram of an example of a two-system video signal generation circuit of the present invention.

FIG. 4 is a timing chart during operation of the circuit shown in FIG.

FIG. 5 is a circuit diagram of a conventional active matrix type liquid crystal display device.

6 is an example of an equivalent circuit of the picture element shown in FIG.

FIG. 7 is a timing chart when the source driver shown in FIG. 5 operates.

[Explanation of symbols]

1 substrate 2 display section 3 a source driver 4 gate driver 20 picture elements 31a, 31b video signal line 32 an analog switching 33 sampling capacitor 34 the common electrode S ₁ to S _N source bus lines G ₁ ~G _M gate bus lines SRA, SRB shift register video original video signal Video1, Video2 video signal D _1, D _2, ... the video signal potential (data) ΦA, ΦABar, ΦB, ΦBBar clock signal

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor ▲ Taka ▼ Yu Fuji Fuji 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Corporation (72) Inventor Osamu Sasaki 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka No. Sharp Co., Ltd.

Claims (4)

[Claims] 1. A plurality of gate bus lines and a plurality of source bus lines are arranged on a substrate so as to be orthogonal to each other, and picture elements are formed at respective intersections of the gate bus lines and the source bus lines. In an active matrix type liquid crystal display device in which a gate driver for driving the gate bus line and a source driver for driving the source bus line are formed, sample and hold circuits are formed on the source bus lines, and The sample-and-hold circuits are adjacent to each other (L is an integer of 2 or more), and each sample-and-hold circuit in each set is sequentially connected to one of the L-system video signal lines. A K (integer of 2 or more) system is provided for the shift register for controlling the switch means provided in the AND-hold circuit. The source driver is configured such that each pair of switch means adjacent to each other is driven by the shift register of another system in a state where one set of switch means is associated with one system of shift register, For each of the video signal lines, shift the sampling phase by the sampling period obtained by dividing the effective horizontal scanning period by the number of effective source bus lines,
An L-type video signal obtained by sampling a video signal as an original signal with a period L times the sampling period is applied with the phases aligned, and a period L times the sampling period is applied to the shift register for each system. An active matrix liquid crystal display device to which a clock signal having a shift and a period of 2 KL times the sampling period is applied. 2. A correction circuit that detects an output signal level difference between the L types of video signals and performs a gain correction and an offset correction based on the output signal level difference has a gain of 0.5. %, And the offset is 20 mV or less, The active matrix type liquid crystal display device according to claim 1. 3. The active matrix liquid crystal display device according to claim 1, wherein the picture element includes a charge holding capacitor, and the capacitance of the sample-and-hold circuit is 10 times or more the charge holding capacitor. 4. The active matrix liquid crystal display device according to claim 1, wherein a thin film transistor is provided as a switching element for driving the picture element, and the thin film transistor, the gate driver and the source driver are made of polycrystalline silicon. .