JPH02214818A - Liquid crystal display device and its driving method - Google Patents

Abstract

PURPOSE:To obtain an active matrix type liquid crystal display device where the influence of gate pulse delay is eliminated by applying driving pulses to plural gate lines at the same time. CONSTITUTION:Gate pulses are applied to 1st, 2nd...(k)th gate lines of the active matrix type liquid crystal display device to turn on TFTs of the 1st, 2nd...(k)th lines, and data are written in picture elements in the 1st, 2nd...(k)th lines through data lines. For example, when k=2, the gate pulses are applied to two gate lines G1 and G2 at the same time to turn on the TFTs 13 connected to those gate lines at the same time. At this time, data are written in respective picture elements in the 1st line through odd-ordered data lines D1, D3...D2n-1 and picture elements in the 2nd line through even-numbered data lines D2, D4...D2n. Consequently, trouble caused by the shortening of a signal write time due to gate pulse propagation delay by the high resistance and parasitic capacity of gate wiring is eliminated to obtain excellent and stable image quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix liquid crystal display device and a method for driving the same, and particularly to a liquid crystal display device and a method for driving the same suitable for realizing good image quality.

[Conventional technology]

An active matrix helix type liquid crystal display device is described, for example, in Japanese Patent Application Laid-Open No. 1983-1989, No. B&IIIG.

FIG. 2 is a circuit diagram of an example of an active matrix liquid crystal display device.

In FIG. 2, 21 is a liquid crystal cell, 22 is a charge storage capacitor, and 23 is a thin film transistor (hereinafter referred to as TPT) connected to one electrode of the liquid crystal cell 21, and these constitute one pixel. .

Further, 24 is a plurality of n data lines D1 to Dn commonly connected to the TFTs in each column of the active matrix, and 25 is a plurality of data lines D1 to Dn commonly connected to the TFTs in each row of the active matrix.
Main gate line 61~Gm, 26 is gate line G~Gm
27 is a scanning circuit (hereinafter referred to as a cheater driver) that applies image signals for horizontal scanning in parallel to the data lines D1 to Dn; It is a transparent common electrode that is commonly connected to the other electrode of the liquid crystal cell 21 formed on the substrate;

Next, driving of the active matrix liquid crystal display device will be explained.

FIG. 3 is a diagram schematically showing an example of a drive waveform.

In FIG. 3, the voltage required to turn on the TPT is applied to the first gate line G1. , pulse ■G with voltage of l
In synchronization with the addition of i, the image signal voltage Vs,+ is applied to the j-th data line DJ. As a result, pixel C
Charge is accumulated in the liquid crystal capacitor and storage capacitor of the IJ, and image signals are written. For this write, the gate voltage is V
The process is completed between t1 and t1+Δt. Thereafter, the voltage of pixel CIJ is t after one field period T.
It is held at V S J until the signal is written again at t+T, and the gate voltage is VOFF. In line sequential scanning, all TPTs connected to the first gate line G+ are turned on at the same time, and the above Similar signal writing is performed. At the same time as the i-th write ends, a pulse V is applied to the i+1-th gate line Gi+1.
GI+1 is added, all TPTs connected to the i-1001th gate line are turned on at the same time, and signals are written in the same way.

By sequentially applying voltages to the gate lines as described above, the TPTs are sequentially turned on, line sequential scanning is performed, and pixels are driven.

[Problem to be solved by the invention]

The active principle of the active matrix liquid crystal display device is as explained above, but in actual driving, the propagation delay of the gate voltage pulse must be taken into consideration.

FIG. 4 is a diagram showing a gate pulse and a delayed propagation delay gate pulse.

As shown in FIG. 4, even if the gate pulse voltage applied to the gate line is a square wave, the waveform is delayed due to the gate line capacitance and wiring resistance, and at the end opposite to the gate driver 26, the rise delay tr and falling delay tf occur, distorting the waveform. Therefore, in the characteristics shown in FIG. 4, the actual writing time is effectively Δt-tr, which is 8t.
Since the length becomes shorter, there is a problem that the image signal cannot be written sufficiently.

The above problem is caused by using polysilicon (polysilicon) as the gate line.
This is particularly important when using -8i). That is, since polysilicon has a higher resistance than metal, the above-mentioned propagation delay increases, and the effective writing time becomes shorter and shorter. This makes it difficult to use polysilicon, which is advantageous in device formation, as the gate line, resulting in an increase in manufacturing man-hours and costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide an active matrix liquid crystal display device that eliminates the influence of the gate pulse delay and a method for driving the same.

[Means to solve the problem]

In order to achieve the above object, the present invention is constructed as described in the claims.

That is, in the present invention, the TPT on time can be almost doubled by applying II pulses to multiple (k) gate lines at the same time, instead of applying them sequentially to each gate line in the past. This is what I did.

Note that claim 1 indicates the basic configuration of the present invention, and corresponds to, for example, the embodiment shown in FIG. 1 described later.

Furthermore, the second claim corresponds to, for example, the embodiments shown in FIGS. 6 and 13 described later.

Further, claim 3 corresponds to, for example, the embodiment shown in FIG. 7, which will be described later.

Further, claim 4 indicates a driving method of the present invention, and corresponds to, for example, what will be explained later with reference to FIGS. 1 and 5.

Further, claim 5 is a driving method for interlaced scanning, which corresponds to the driving method described later in the embodiment shown in FIG. 12, for example.

[For production]

In the present invention, gate pulses are simultaneously applied to the first, second, ..., k-th gate lines, and the TP over the rows is
By turning on T, the first
,2. ...Writes to the pixel in the k-th row.

Once these rows have been written, the next row is simultaneously pulsed. By writing the 1 (row) signals at the same time in this way, it is possible to take twice as much time to write as compared to the conventional method.As a result, in the present invention, the time allowed for writing is Δt-tr
Therefore, it becomes possible to solve the problem associated with shortening the write time due to propagation delay, which was a drawback in conventional devices.

〔Example〕

Embodiment 1 FIG. 1 is a diagram showing an embodiment of the basic configuration of the present invention, and is a circuit diagram of an ACTITSUMA 1 to RIX type liquid crystal display device. Note that this embodiment exemplifies a case where the number of gate lines driven simultaneously is two (k=2).

In FIG. 1, 11 is a liquid crystal cell arranged in a matrix, 12 is a charge storage capacitor, 13 is a TPT connected to one electrode of each liquid crystal cell 11, and 14 is a TP
Data lines D□ to D2 commonly connected to each data electrode of T
11.15 are gate lines 01-G commonly connected to each gate electrode of the TFT. Further, 16 is a gate driver that sequentially applies scanning pulses to gate lines, 17 is a data driver that has a function of applying image signals to data lines in parallel, and 18 is a substrate that faces the substrate on which TPT is formed with the liquid crystal interposed therebetween. A transparent common electrode is formed on top of the transparent common electrode.

In addition, in FIG. 1, odd-numbered gate lines G□, G
3. . . . The data electrodes of the TPT connected to G11-□ are connected to odd-numbered data lines D1, D3, .・・・
D2n-□, even-numbered gate lines G2. G.
, ・The data electrodes of the TPT connected to GIl are connected to the even-numbered data lines D2 . D.

...Connected to D2n. Therefore, the number of data lines connected in one column is two, and the number of data lines is twice that of the circuit shown in FIG. 2.

Note that in this embodiment, to simplify the explanation, a configuration is shown in which simultaneous writing is performed on two gate lines (k = 2), but the number of gate lines that are simultaneously written may be 2 or more. do not have. However, in the present invention, it is necessary to provide twice as many data lines as in the conventional configuration, that is, twice when k=2, and three times when k=3.

In this embodiment, two adjacent gate lines G□ and G
, simultaneously, and the TPTs connected to those gate lines are turned on simultaneously. At this time, the odd numbered data liner.

D3...D2n-□ writes to each pixel in the first row (corresponding to G-type), and similarly writes to the even-numbered data line D2. D4...D23 write to each pixel in the second row (corresponding to G2).

When the writing of the first and second rows is completed as described above, the gate line G3. Apply a gate pulse to G4, and the following pair of gate lines (GS, G,,), (G7°G8)
Gate pulses are added sequentially for each...

By writing signals in two rows at the same time in this way, it becomes possible to spend twice as much time on writing as compared to the conventional case of writing one row at a time. This corresponds to effectively doubling the time for applying the pulse voltage to the gate.

Next, FIG. 5 is a diagram showing the drive circuit and drive signal waveforms in the embodiment of FIG. 1, in which (a) is a block diagram of the drive circuit of the active matrix liquid crystal display device of FIG. 1, and (b) ) is the drive signal timing chart 1-1 (C
) is a voltage waveform diagram of a gate pulse and a propagation-delayed gate pulse.

First, in FIG. 5(a), the liquid crystal panel 51
This is a panel consisting of a large number of liquid crystal pixels arranged in a matrix as shown in the figure. Further, 52 is a gate driver (corresponding to 16 in FIG. 1) for the liquid crystal panel 51, and when driving two gate lines at the same time, it can be configured with a shift register having half the number of stages as the number of gate lines. - Inside the shell, when driving k lines at the same time, 1/1 of the number of gate lines is required.
It can be configured with a number of stages of shift 1 registers.

In the case of this embodiment, the shift register is controlled by, for example, a two-phase clock pulse φ2. A pulse shift operation is performed by φ2, and a scanning pulse SH is output to each gate line. Also, 53
1 is a data driver (corresponding to 17 in FIG. 1) composed of a shift register, a line switch, a line memory, etc.; 54 is a video signal input; and 55 is a synchronization signal control section.

The operation will be explained below based on the timing chart of FIG. 5(b).

For example, by using a shift register operated by two-phase clock pulses φ□ and φ1 and a vertical synchronizing pulse Sv, 2
Image signals for rows are stored in a line memory within the data driver 53. The image signals for two rows stored in the line memory are transferred to the odd data lines D□, D3...D2n-1 by the line switch pulse SL, and the other one
Data lines with even numbered rows 3. D4・D. is output to. In this way, the image signals for two rows are transferred to the two data lines D.
By simultaneously writing to the pixels through 2n-t+D2n, it is possible to use the writing time 2Δt for two lines.

FIG. 5(c) is a diagram showing the gate pulse and propagation delay gate pulse in the above operation.

As shown in the figure, since the write time of the gate pulse becomes 2Δt, the actual write time becomes 2Δt−tr, and the write time increases by Δt compared to the case of writing one book at a time.

Therefore, it is possible to solve the problem associated with shortening the writing time due to the propagation delay of the gate pulse.

In the embodiments shown in FIGS. 1 and 5, the number of lines to be simultaneously written is two, but in the same way, the number of lines to be simultaneously written is 3, 4, etc. . . . It is also possible to have k numbers, and it is possible to almost double the writing time (k·Δt) compared to the conventional method.

Example 2 Next, FIG. 6 is a diagram showing a second example of the present invention,
(a) is a block diagram of an active matrix liquid crystal display device, and (b) is a drive voltage waveform diagram thereof. In this embodiment, a gate driver that outputs gate pulses for driving odd-numbered gate lines and a gate driver that outputs gate pulses for driving even-numbered gate lines are provided separately.

In FIG. 6, 61 is a liquid crystal pixel composed of a liquid crystal cell, a charge storage capacitor, a TPT, and a pixel electrode, and 62 is a data driver. Also, 63 and 64
are gate drivers that independently drive the gate lines to be written simultaneously, and the gate driver 63 is connected to drive the odd-numbered gate lines, and the gate driver 64 is connected to drive the even-numbered gate I lines. .

As shown in FIG. 6(b), the above circuit consists of line memory switch pulses S+SL2, two-phase clock pulses φ2□, φ2□, and φ2°, φ2□, gate pulse S
It is driven by a drive pulse composed of H□ and SR2. That is, at the same time as the gate driver 63 outputs a signal for driving the gate line in the first row, the gate driver 64 outputs a signal for driving the gate line in the second row. Driving is performed.

In this embodiment, as in the case of FIG. 1, it is possible to solve the problem of shortening the data writing time due to the propagation delay of the gate pulse.

Note that in the above description, the gate drivers 63 and 6
4 outputs gate pulses at the same time, that is, performs substantially the same operation as in FIG. 1, but the circuit in FIG. Therefore, it is more effective for other types of control, such as interlaced control as described in the embodiment shown in Section 12.13 below.

In this embodiment, the case where k=2 is illustrated, but if k gate lines are to be driven at the same time, it is possible to provide a configuration in which k gate drivers are provided and each is driven independently. Of course.

Embodiment 3 Next, FIG. 7 is a diagram showing a third embodiment of the present invention, and shows a block diagram of an active matrix liquid crystal display device. In this embodiment, in addition to the embodiment shown in FIG. 6, a data driver that drives pixels connected to odd-numbered gate lines and a data driver that drives pixels connected to even-numbered gate lines are added. is provided separately.

In FIG. 7, 71 is the same liquid crystal pixel as described above, and 74 and 75 are gate drivers (corresponding to 63 and 64 in FIG. 6). In addition, two data drivers 72.7 consisting of a line memory for storing image signals, a shift register, etc.
3 is independently connected for odd-numbered days and for even-numbered days, corresponding to each gate driver 74 and 75, when pulses are applied to the gate lines at the same time to write signals. Note that if the number of gate lines to be simultaneously driven is equal to the number of gate lines, this data driver may be provided for k lines, that is, k data drivers. In this embodiment, a case of two wires (k=2) will be shown to simplify the explanation.

With the above configuration, the gate driver 74.
It becomes possible to simultaneously write image signals through each gate line driven by the gate line.

It is also possible to write signals by providing the shift 1 register constituting the data driver as a common function, and providing only the line memory as an independent function.

Embodiment 4 FIG. 8 is a signal waveform diagram showing a fourth embodiment of the present invention.

In the circuit shown in FIG. 7, the drive waveform is compared to SL□ by comparing the line switch pulse SL2 with SL□ as shown in FIG.
By delaying by o, it is possible to shift the entire write by to. This to can be set arbitrarily, so by setting to to an appropriate time, screen flickering can be improved compared to the case of simultaneous writing.

Example 5 FIG. 9 is a diagram showing a fifth embodiment of the present invention.

In this embodiment, the two gate lines which are driven simultaneously in the embodiment shown in FIG. 1 are combined into one and driven by one output of the gate driver. In this embodiment, two books are combined into one, but when k books are driven at the same time, the books can be combined into one.

In FIG. 9, 91 is the same liquid crystal pixel as described above, 92 is a data driver (corresponding to 17 in FIG. 1), and 93 is a gate driver.

Example 6 FIG. 10 is a diagram showing a sixth embodiment of the present invention.

In the embodiments so far, the case where =2 has been described to simplify the explanation, but it is also possible to set it to =3, 4, 5, etc., as described above. 10th
The illustrated embodiment shows, as an example, the case where k=4.

Note that 101 is a pixel (corresponding to 11 in FIG. 1), 102 is a data driver, and 103 is a gate driver.

Furthermore, D□l D2! D31...D4n are data lines, and in this embodiment, four times as many data lines as in FIG. 2 are required.

Further, FIG. 11 is a plan view showing a specific structure of the element of the embodiment shown in FIG. 10.

This plan view shows the liquid crystal pixel, TPT, in the case of k=4.
, indicates the arrangement of lines g□ to g9 and data lines (vertical lines), and shows the so-called triangular arrangement in which green G, blue B, and red R pixels for color display are arranged in a triangle. It shows.

Note that the TPT is indicated by a black circle in the figure.

Further, the goo1 to goo lines divided into ■ to ■ are driven simultaneously (eg, g□ to g4 at the same time).

Example 7 FIG. 12 is a diagram showing a seventh embodiment of the present invention.

In the operation of the present invention described so far, interlaced scanning has not been mentioned. Let's also consider interlaced scanning here.

In FIG. 12, a pair of odd-numbered G1~ lines (Gl
, G3) at the same time to complete writing, the same goes for every other pair of gate lines (a
A gate pulse is sequentially applied to s , a 7) and (G 9 , a□□) to form a first field.

Next, a gate pulse is applied to a pair of even-numbered gate lines (G2°G4) to form a second field in the same manner as the first field, thereby making interlace scanning possible.

In this case, the pixels connected to the 1st, 2nd, 5th, 6th, 9th, 10th, . Pixels connected to the 12th gate line are connected to the same data line.

Example 8 FIG. 13 is a diagram showing an eighth embodiment of the present invention.

In this embodiment, in the circuit shown in FIG. 12, odd-numbered gate lines G, , G, , G5 . . . G2n-□ and even-numbered gate lines G2 . G4. G6.・・・・・・
- Two gate drivers 123 and 124 are provided so that G2n can be moved independently, and the first and second fields can be formed independently.

Furthermore, if the data driver is configured like the circuit shown in FIG. 7, when forming the first and second fields,
A screen can be constructed by sequentially applying gate pulses to both fields simultaneously from above. In this way, 1
Since two fields can be formed simultaneously in the time it takes to form a field, the writing time can be doubled.

Example 9 FIG. 14 is a diagram showing a ninth embodiment of the present invention.

In this embodiment, the gate pulse application method is the same as that shown in FIG.
are switched by the switch 134 for each field, and the gate line pair (G3, G4) is similarly changed thereafter.

(as, G6)... Switch. With this configuration, the gate driver 133 only needs to have half the number of stages of shift registers as the number of gate lines. k
When driving two gate lines at the same time, the number of stages of gate drivers 133 can be reduced to 1/k.

〔Effect of the invention〕

According to the present invention, in an active matrix liquid crystal display device, the writing time can be significantly extended compared to the conventional method. Therefore, it is possible to solve the problem of shortening signal writing time caused by gate pulse propagation delay caused by high wiring resistance and parasitic capacitance, resulting in the excellent effect of achieving good and stable image quality. .

Furthermore, in the present invention, since the effective writing time can be significantly increased, it is possible to use polysilicon gate lines, which has been difficult in the past, and therefore the number of manufacturing steps and costs can be reduced.

In the present invention, the number of data lines is increased compared to the conventional one, but as liquid crystal display devices become larger and have higher definition, the number of gate lines increases, and it is difficult to take enough writing time per gate line. In such cases, the present invention has great effects even if the number of data lines increases. That is, the present invention is particularly effective in large-screen, high-definition active matrix liquid crystal display devices that are accompanied by an increase in the number of lines, an increase in wiring resistance, and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of an active matrix panel of the present invention, FIG. 2 is a circuit diagram of an example of a conventional active matrix panel, FIG. 3 is a signal waveform diagram in a conventional panel driving method, and FIG. The figure is a signal waveform diagram for explaining propagation delay, FIG. 5 is a diagram showing a drive circuit and drive signal waveform in an embodiment of the present invention, and FIG. 6 is a block diagram and signal waveform of a second embodiment of the present invention. Waveform diagram, FIG. 7 is a block diagram of the third embodiment of the present invention, FIG. 8 is a signal waveform diagram of the fourth embodiment of the present invention, and FIG. 9 is a block diagram of the fifth embodiment of the present invention. 1O is a block diagram of a sixth embodiment of the present invention, FIG. 1J is a plan view showing an embodiment of a specific configuration of a display element of the present invention, and FIG. 12 is a block diagram of a sixth embodiment of the present invention. FIG. 13 is a block diagram of an eighth embodiment of the present invention, and FIG. 14 is a block diagram of a ninth embodiment of the present invention. <Explanation of symbols> 11, 21...Liquid crystal cell 12, 22・Charge storage capacitor 13, 23...TPT 14, 24...Data line 15, 25...Gate line 16, 26.52... Gate driver 17, 27.53...Data driver 51...Liquid crystal panel 54...Image signal human power 55...Synchronization signal control section

Claims (1)

[Claims] 1. A device comprising a plurality of gate lines arranged in the row direction, a plurality of data lines arranged perpendicularly to the gate lines in the column direction, and a thin film transistor formed at each intersection of the matrix. , a first substrate whose intersection points serve as pixels, and a second substrate formed with a transparent conductor, and a liquid crystal display device in which a liquid crystal is sealed between the two substrates, wherein the plurality of gate lines are connected to each other. It is divided into k data lines (k is a positive integer of 2 or more), and one data line is connected to each pixel in each of the above sections for each column, that is, k data lines are connected to each column and each section. , and means for applying the same driving pulse to the k divided gate lines. 2. The liquid crystal display device according to claim 1, characterized in that drive pulses to be applied to the k gate lines in each of the sections are applied from k gate line scanning circuits that are independent from each other. Device. 3. In the liquid crystal display device according to claim 1 or 2, k scanning circuits for driving data lines or line memories in the scanning circuits are provided and connected to k gate lines to be driven simultaneously. 1. A liquid crystal display device characterized in that an image signal is written to k rows of pixels in each row independently and simultaneously. 4. A plurality of gate lines lined up in the row direction, a plurality of data lines lined up perpendicularly to the gate lines lined up in the column direction, and a thin film transistor formed at each intersection of the matrix, each intersection being used as a pixel. A liquid crystal display device having a first substrate formed with a transparent conductor and a second substrate formed with a transparent conductor, and a liquid crystal sealed between the two substrates, wherein A method for driving a liquid crystal display device, characterized in that the operations of k pixels simultaneously driven for each column are controlled by data lines connected to each pixel. 5. In the driving method described in claim 4, when the odd-numbered pair of gate lines (G_1, G_3) is driven at the same time and writing is completed, the same applies to every other pair of gate lines (G_1, G_3). Lines (G_5, G_7), (G_9, G_1
_1), . A method for driving a liquid crystal display device, characterized in that interlaced scanning is performed by forming a second field in the same manner as in the above.