JPH03175546A - Instruction cache memory - Google Patents

Abstract

PURPOSE:To test the data part of an instruction cache memory in a short time by selecting a set as the write object due to instruction fetch out of sets which are not in the test start in a control register. CONSTITUTION:Information from a control register 11 where information indicating which sets are in the test state is stored is inputted besides signals required for normal rewrite control to select a set to be written from sets which are not in the test state. Consequently, the set selected as the write object in accordance with contents of the control register 11 by execution of a write instruction of the instruction cache is removed from the object of substitution due to instruction fetch to operate only sets other than sets, which are in the test state, as the instruction cache. Thus, a data memory 3 in the instruction cache memory is tested at a high speed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an instruction cache memory.

2. Description of the Related Art In recent years, microprocessors have come to be equipped with large-capacity instruction cache memories consisting of multiple sets. It is necessary to test in advance whether such an instruction cache operates normally.

FIG. 2 shows the configuration of a conventional instruction cache.

In FIG. 2, 1 is a decoder, 2 and 3 are data memories, 4.5 are tag memories, 6 and 7 are comparators, 8 is a read control circuit, 9 is a write control circuit, 10 is a replacement limiting circuit, and 11 is a control register, 12 is a data bus, 13 is an address bus, 14 is an enable signal, 15 is a read request signal, 16 is a write request signal, 17 is a control signal, 18.19 is a hit signal, 20.21 is a read signal, 22.23 is a write signal, 24 is a selection signal,
Reference numerals 25 and 26 indicate human output signals of the data memory, 27 and 28 indicate output signals of the tag memory, and 29 indicate a miss signal, respectively.

Reading data memories 2 and 3 by instruction fetch is as follows:
Tag memories 4, 5 selected by address bus 13
This is done by comparing the contents of the address with the tag part of the address by the comparators 6 and 7, respectively, and reading out the contents of the data memory of the matched set. Furthermore, writing into the data memories 2 and 3 by fetching an instruction is performed by writing the fetched instruction into a set of data memories selected by the replacement control circuit 10 upon completion of access to the external memory.

Here, data memory 2.3 in the instruction cache memory
Reading by the read command is performed by selecting a set to be read from the selection signal 24 output from the control register 11 and reading the data memory of the set. Writing to data memory 2.3 in the instruction cache memory by a write command is performed by selecting a set to be written from the selection signal 24 and writing it into a block of the data memory.

The data memory in the instruction cache memory is tested by writing to and reading from each set of data memories 2 and 3 in the instruction cache memory using such instruction cache memory write or read instructions. be able to.

Problems to be Solved by the Invention However, in the above conventional instruction cache memory,
When testing one of two sets of data memory while operating the instruction cache memory, by fetching instructions, you can test not only the set that is not the target of the test, but also the set that is not the target of the test.
Instructions may also be written to the set being tested. Therefore, in order to properly test the data memory, the test must be performed without using the instruction cache memory, which poses a problem in that it takes a long time to test the data memory.

In view of these conventional problems, the present invention prohibits writing to a set in a test state by fetching instructions, so that when testing data memory in the instruction cache memory, data memory in the instruction cache memory that is not in the test state is prohibited. It is an object of the present invention to provide an instruction cache memory that can be used effectively and that allows a test of data memory in a large capacity instruction cache memory to be executed in a short time.

Means for Solving the Problems In order to achieve the above object, the present invention provides, in addition to the signals necessary for normal replacement control, information from a control register that stores information on which set is in a test state. This is done manually, and the set to be written is selected from among the sets that are not in the test state.

Effect of the Invention With the above-described configuration, the present invention eliminates the set selected as a write target based on the contents of the control register upon execution of a write instruction in the instruction cache from being replaced by an instruction fetch, thereby replacing the set other than the set in the test state. Since only the instruction cache memory can be operated as an instruction cache, a test of the data memory in the instruction cache memory can be executed at high speed.

Embodiment FIG. 1 is a schematic block diagram of an instruction cache memory showing an embodiment of the present invention. Since it has almost the same configuration as the conventional example shown in FIG. 2, similar elements are designated by the same reference numerals. It is attached. In FIG. 1, 1 is a decoder, 2.3 is a data memory, 4.5 is a tag memory, 6.7 is a comparator,
8 is a read control circuit, 9 is a write control circuit, 10 is a replacement control circuit, 11 is a control register, 12
13 is a data bus, 13 is an address bus, 14 is an enable signal, 15 is a read request signal, 16 is a write request signal, 17 is a control signal, 18° and 19 are hit signals, 20.
21 is a read signal, 22.23 is a write signal, 24
25 and 26 are the human output signals of the data memory, 27 and 28 are the output signals of the tag memory, 2 are the miss signals, and 30 is the second selection signal, respectively.

Data bus 12 and address bus 13 are each 32 bits. Data memories 2 and 3 each consist of 256 blocks, and the block length is 32 bits.

The tag memories 4 and 5 each consist of 256 blocks, and each block length is 22 bits. Decoder 1
takes the lower 10 bits of address bus 13 as input, and inputs 256 bits of each of data memories 2 and 3 and tag memories 4 and 5.
Select one of the blocks.

When the read signal 20.21 input to each data memory 2.3 is asserted, the data memory 2.3 transfers the contents of the block selected by the decoder l to the data bus 12.
The write signal 22 that is output to and manually input to each
．． 23 is asserted, the value applied to the data bus is written into the block selected by the decoder 1.

The tag memories 4, 5 always output the contents of the block selected by the decoder 1 as output signals 27, 28, respectively, and write signals 22, 28, which are input manually, respectively.
23 is asserted, the upper two on address bus 13
The value applied to the 2 bits is written to the block selected by the decoder 1.

Comparators 6 and 7 constantly compare the values of the output signals 27 and 28 of the tag memory input to each with the value applied to the upper 22 bits on the address bus 13, and if they match, the respective hit signals are output. Assert 18.19 and negate if they do not match.

The read control circuit 8 outputs a hit signal 18 if the enable signal 14 is asserted, the control signal 17 is negated, and the read request signal 15 is asserted.
．． It operates according to 19 states. At this time, the hit signal 1
8 is asserted, the read signal 20 is asserted, if the hit signal 19 is asserted, the read signal 21 is asserted, and if all the hit signals 18 and 19 are negated, the miss signal 29 is asserted. Further, if the control signal 17 is asserted and the read request signal 15 is asserted, the read control circuit 8 outputs the read signal 2 regardless of the state of the hit signal 18.19.
0.21, the read signal connected to the set selected by the first selection signal 24 is asserted.

If the enable signal 14 is asserted, the control signal 17 is negated, and the write request signal 16 is asserted, the write control circuit 9 outputs the write signal 2.
2. Assert the write signal connected to the set selected by the state of the second selection signal 30 among 23. Further, if the control signal 17 is asserted and the write request signal 16 is asserted, the write signal 22
．． 23, a write signal connected to the set selected by the state of the first selection signal 24 is asserted.

The replacement control circuit 10 manually generates one hit signal 18, a read request signal 15, and a first selection signal 24,
Among the sets not selected by the first selection signal 24, information indicating the set that was not read out during the most recent instruction fetch is outputted as the second selection signal 30.

The control register 11 stores information for selecting a target set of instructions for reading and writing into the instruction cache memory, and transmits the information to the first selection signal 2.
Output as 4.

Reading data memory 2.3 by instruction fetch is as follows:
It is executed as follows. First, while the enable signal 14 is asserted, the read request signal 15 is asserted and a read address is applied to the address bus 13. Then, the tag memory 4 is selected from each set of blocks selected by the lower 10 bits of the read address.
, 5 are read out, and the comparator 6 of each set is read out.
．． 7 are compared with the upper 22 bits of the address. Depending on the comparison result, the hit signal is 18 or 19.
and instruction cache memory enable signal 1
4 and the read request signal 15 are input to the read control circuit 8. If the hit signal 18 is asserted, the read signal 20 is asserted, and if the hit signal 19 is asserted, the read signal 21 is asserted. If both 19 and 20 are negated, miss signal 2
Assert one. Therefore, if the contents of the block of tag memory 4.5 selected by the lower 10 bits of the read address match the upper 22 bits of the address, the contents of the block of data memory selected by the lower 10 bits of the read address will match the address. The data is read out onto the bus 13.

Furthermore, data memory writing by instruction fetch is executed as follows. If the instruction cache memory enable signal 14 is asserted, the write request signal 16 is asserted upon completion of the access to the external memory, and the fetched instruction is applied onto the data bus 12. At this time, the write control circuit 9 sends the write signal 22 to the set indicated by the second selection signal 30.
or 23. At this time, the replacement control circuit 10 controls the first set indicating the target set by the instruction cache read and write instructions.
Among the sets not selected by the selection signal 24, the set that has not been read by instruction fetch for the longest time is selected, and its information is output as the second selection signal 30. Therefore, the second selection signal 30 selects a set other than the set selected by the value on the data bus 12 as the target of instruction cache memory read and write instructions, and the lower 10 bits of the address bus 13 select a set other than the set selected as the target of the instruction cache memory read and write instructions. data is written to a block of memory.

Here, data memories 2 and 3 in the instruction cache memory
Reading by the read command is executed as follows. At the same time that an address for selecting a block to be read is input to the decoder 1, a read request signal 15 and a control signal 17 indicating that the read is based on an instruction cache read command are asserted. At this time, the read control circuit 8 selects the set to be read from the first selection signal 24 output from the control register 11, and asserts the read signal 20 or 21 regardless of the state of the instruction cache enable signal 14. Therefore, the block of data memory selected by the lower 10 bits of the address of the set selected by the first selection signal 24 is read onto the data bus 12.

Further, writing to the data memory 2.3 in the instruction cache memory by a write command is executed as follows. The address for selecting the block to be written is entered into decoder 1, and the write data is transferred to data bus 1.
2, a write request signal 16 and a control signal 17 indicating that the write is due to an instruction cache write command are asserted. At this time, the write control circuit 9 selects the set to be written from the first selection signal 24 and asserts the write signal 22 or 23, regardless of the state of the instruction cache enable signal 14. As a result, the value on the data bus 12 becomes
The lower 10 bits of the address of the set selected by the first selection signal 24 are written to the block of data memory selected.

Therefore, when testing the data memory 2, after storing information indicating that the data memory 2 is in the test state in the control register 11, the enable signal 14 is asserted and a program for testing the data memory 2 is executed. Written only to data memory 3,
executed. Further, instructions for reading and writing from the instruction cache in the program are executed to the data memory 4. Therefore, it is possible to test the data memory of the set to be tested while operating the set not to be tested as the instruction cache memory, making it possible to execute the test program at high speed and reducing the test time for the instruction cache memory. can do. In addition, the control register 11
By executing the program after storing information indicating that the data memory 3 is in a test state, it is possible to test the data memory 3 while storing instructions in the data memory 2, which reduces the effort required to create a test program. can be reduced.

Effects of the Invention As is clear from the above description, the present invention selects a set to be written to by fetching an instruction from among sets that are not in a test state in a control register.
Since the program for testing the set to be tested is stored in a set other than the set to be tested, the data portion of the instruction cache memory can be tested in a short time.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an instruction cache memory showing an embodiment of the present invention, and FIG. 2 is a schematic block diagram of an instruction cache memory showing a conventional example. 1... Decoder, 2.3... Data memory, 4, 5
... Tag memory, 6, 7... Comparator, 8... Read control circuit, 9... Write control circuit, 10... Replacement control circuit, 11... Control register, 1
2...Data bus, 13...Address bus, 14...
・Enable signal, 15...Read request signal, 16
. . . Write request signal, 17. . . Control signal, 18.
19...Hit signal, 20.21...Read signal, 22°23...Write signal, 24...First selection signal, 25.26...Human output signal, 27.28...
- Output signals, 2... miss signal, 30... second selection signal.

Claims (2)

[Claims] (1) A control circuit that controls rewriting of blocks generated by instruction fetch, a control register that stores information as to whether each set is a target of a read or write command, and an output signal of the control register that controls the rewriting of the block. By controlling the control circuit,
An instruction cache memory comprising: means for selecting a set to be a target for block rewriting by instruction fetch from sets that are not targets for read or write instructions. (2) at least two sets, a control register that outputs a first selection signal for selecting one of the sets depending on the contents to be stored, and a control register that outputs all hit signals and read and write signals output by each of the sets; A control signal indicating whether the request is an instruction fetch request or an instruction cache read or write command, a read request signal, and the first selection signal are input, and if the control signal is negated, one of the hit signals is asserted. asserts only the read signal connected to the set to which the hit signal currently selected is connected; and if the control signal is asserted, asserts the read signal connected to the set selected by the first selection signal. a read control circuit; a replacement control circuit that receives the first selection signal as an input and selects one set from among the sets not selected by the first selection signal and outputs it as a second selection signal; and the control signal. , a write request signal, and the first and second selection signals, and if the write request signal is asserted while the control signal is negated, the set selected by the second selection signal is selected. Write control that asserts a write signal connected to the set, and asserts a write signal connected to the set selected by the first selection signal if the write request signal is asserted while the control signal is asserted. An instruction cache memory with a circuit.