JPH1049440A - Cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory system which can avoid its useless operations, can reduce its power consumption and also can simplify its circuit configuration. SOLUTION: A CPU 10 outputs a high level of a data/instruction identification signal DCI simultaneously with an address ADR in a data bus cycle mode. Receiving the signal DCI, a cache memory 30 is set in an enable state. The CPU 10 outputs the address ADR to a main memory 20 and the memory 30 respectively via an address bus ADRBUS. The memory 30 holds the address ADR via an address register DAR and also holds the data received form a data bus. Therefore, the memory 30 operates only in the data bus cycle mode to avoid its useless operations and to reduce its power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, for example, a cache memory system including a secondary cache memory provided outside a CPU (Central Processing Unit).

[0002]

2. Description of the Related Art In an on-chip cache memory formed as a part of a CPU, a so-called primary cache memory, a cache memory for instructions and a cache memory for data must be separated in order to perform smooth arithmetic processing of the CPU. It is now mainstream. In addition, the cache memory for instructions and the cache memory for data often change specifications such as associativity and write operation.

For example, normally, a programmed instruction is not rewritten by the CPU during execution, so that the CPU does not similarly write the instruction cache memory. Therefore, many CPUs have an instruction cache memory that does not support the writing function of the CPU.

[0004]

By the way, generally,
Most secondary cache memories provided outside the CPU are complex cache memories in which instructions and data are mixed. For this reason, there is a problem that a useless operation is performed.

For example, when an error occurs in the instruction cache memory inside the CPU, and when the secondary cache memory is applied by the look-aside method, the CPU outputs an address and the like, and replaces the line fill with the secondary cache memory. Request to main memory at the same time.

In the secondary cache memory, it is not known whether the data held in the cache memory block corresponding to the lower bits of the transmitted address is data or an instruction. Therefore, regardless of the content, CPU
A lookup operation must be performed on the address sent from. If it is known from the beginning that the data held there is data, it is not necessary to operate in this bus cycle. Since the address lookup is performed every time the memory is accessed, the power wastefully consumed by the above lookup cannot be ignored.

[0007] Also, since it is a composite cache memory,
There are redundant circuits to manage the instructions.
For example, as in the related art, in a combined cache memory, an instruction may be held in a cache memory block configured as a write-back cache memory. Normally, writing by the CPU is not performed on the cache memory block in which the instruction is held, and in this case, the write-back circuit is redundant.

In addition, it is not possible to change the associativity and capacity of data and instructions with a composite cache memory. If an independent secondary cache memory can be constituted by data and instructions from the beginning, an instruction-only cache memory can be realized by a simpler circuit. Also, it is possible to freely change the associativity and storage capacity by data and instructions.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a cache memory system capable of reducing power consumption and simplifying a circuit configuration, in addition to avoiding useless operation. It is in.

[0010]

In order to achieve the above object, the present invention has at least two bus cycles, a data bus cycle and an instruction bus cycle, and has a data / instruction identification for identifying these bus cycles. A cache memory system having a control device for outputting a signal, comprising: a cache memory that receives the data / instruction identification signal and operates only in one of the data or instruction bus cycles.

Further, according to the present invention, a cache memory system having at least two bus cycles of a data bus cycle and an instruction bus cycle and having a control device for outputting a data / instruction identification signal for identifying these bus cycles is provided. And a first cache memory that operates only in the data bus cycle and a second cache memory that operates only in the instruction bus cycle.

Further, in the present invention, the first and second cache memories have first and second registers for temporarily holding an address output by the control device.

Further, according to the present invention, there is provided a main memory having a register for temporarily holding an address output by the control device, and the main memory has at least a register for temporarily holding a continuous bus cycle. I have two.

According to the present invention, there is provided a cache memory which operates on only a data or an instruction bus cycle in response to a data / instruction identification signal output from a control device, and Or, store the address.

According to the present invention, the first cache memory which operates only in the data bus cycle, ie, the cache memory dedicated to data, and the second cache memory which operates only in the instruction bus cycle, ie, the instruction A dedicated cache memory is separately provided, and the data dedicated cache memory stores an address from the control device during a data bus cycle, and the instruction dedicated cache memory stores an address from the control device during an instruction bus cycle. The cache memory operates independently of the data bus cycle and the instruction bus cycle, can prevent useless operation, reduce the power consumption of the cache memory system, and simplify the circuit configuration.

Further, according to the present invention, by providing at least two address registers for temporarily storing addresses in the main storage device, a search result as to whether or not a continuous address is hit by the cache memory is determined. By the time the address is output, the address is held by the address register, thereby improving the use efficiency of the address bus and the performance of the entire system.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a cache memory system according to the present invention. FIG. 1 shows a CPU 10, a main memory (main storage device) 20, and a cache memory 3.
FIG. 1 is a block diagram showing an example of a system constituted by 0.

In this embodiment, the cache memory 30 is a cache memory provided outside the CPU 10, ie, a so-called secondary cache memory, in contrast to a cache memory built in the CPU 10, that is, a so-called primary cache memory. In the present embodiment, the cache memory 30 is a data-only cache memory that operates only during a data bus cycle.

As shown, the CPU 10 is connected to the main memory 20 and the cache memory 30 via an address bus ADRBUS. The output terminal D / C # of the data / instruction identification signal DCI of the CPU 10 is connected to the chip selection signal input terminal CS of the cache memory 30.

The CPU 10 outputs a high-level data / instruction identification signal DCI when performing data bus cycles when accessing data with the main memory 20, and outputs a low-level data / instruction identification signal DCI when performing instruction bus cycles. Is output at the same timing as the address ADR.

The main memory 20 accesses data at an address specified by an address from the CPU 10 to the CPU 10 via a data bus (not shown). The main memory 20 has an address register MA.
R1 is provided, and the address ADR from the address bus ADRBUS is temporarily held in the address register MAR1. Further, data and instructions from a data bus (not shown) are held in the main memory 20.

Since the cache memory 30 is enabled by a high-level chip select signal, when performing a data bus cycle, the high-level data /
Receiving the instruction identification signal DCI, the cache memory 30 is enabled, and the address ADR from the address bus ADRBUS is stored in the address register DAR. Further, data from a data bus (not shown) is input to the cache memory 30 and held by the cache memory 30. On the other hand, when performing an instruction bus cycle,
Low-level data / instruction identification signal DC from CPU 10
Since I is output, the cache memory 30 is not enabled and does not operate.

As described above, the cache memory 30 operates only during a data bus cycle, and is a so-called data-only cache memory. Therefore, the cache memory 30 operates only during the data bus cycle, and does not operate during the instruction bus cycle. Therefore, useless operation during the instruction bus cycle is prevented, and power consumption can be reduced.

As described above, according to the present embodiment, the CPU 10 controls the address AD during the data bus cycle.
A high-level data / instruction identification signal DCI is output at the same timing as R.
0 is enabled, the CPU 10 transfers the address ADR to the main memory 20 and the cache memory 30 via the address bus ADRBUS, the cache memory 30 holds the address ADR in the address register DAR, and transfers the data from the data bus. Since the cache memory 30 holds the data, the cache memory 30 operates only during the data bus cycle, and does not operate at other times. Therefore, useless operation can be avoided and power consumption can be reduced.

Second Embodiment FIG. 2 is a circuit diagram showing a second embodiment of the cache memory system according to the present invention. As illustrated, the system of the present embodiment includes a CPU 10, a main memory 20, and cache memories 30 and 40. The cache memory 30 is a cache memory dedicated to data, and the cache memory 40 is a cache memory dedicated to instructions.
That is, the cache memory 30 operates only in the data bus cycle, and the cache memory 40 operates only in the instruction bus cycle.

The second embodiment shown in FIG. 2 is different from the first embodiment shown in FIG. 1 in that an instruction-only cache memory 40 is newly provided, and the other components are the same as those of the first embodiment shown in FIG. This is the same as the embodiment. Hereinafter, the operation of the second embodiment will be described with reference to FIG.

The cache memory 30 is a data-only cache memory similar to that shown in the first embodiment, has an address register DAR, and is used only when a high-level signal is input to the chip select signal input terminal CS. Operate.

The cache memory 40 is an instruction-only cache memory. The cache memory 40 operates only when a low-level signal is input to the chip select signal input terminal CSB. Chip select signal input terminal CSB is CP
It is connected to the output terminal of the data / command identification signal DCI of U10. When performing an instruction bus cycle, the CPU 10
As a result, the low-level data / command identification signal DCI is output at the same timing as the address ADR. Therefore, the cache memory 40 is enabled in the instruction bus cycle, and holds the address ADR from the address bus ADRBUS in the address register IAR.

An instruction from a data bus (not shown) is input to the cache memory 40, and the
It is held by 0. Since the instruction-only cache memory 40 in this example operates only during the instruction bus cycle, only the instruction is held therein. Since a write operation is not performed by the CPU 10 for a normal instruction, the control of the cache memory 40 is simpler than that of the data-only cache memory 30, and the circuit can be simpler. further,
Since the data-only cache memory 30 and the instruction-only cache memory 40 can operate independently of each other,
Each can have different associativity and storage capacity.

In the main memory 20, as in the first embodiment shown in FIG. 1, an address ADR from the address bus ADRBUS is held in an address register MAR1 in the main memory 20, and data from a data bus (not shown) is stored. And instructions are held in the main memory 20.

As described above, according to this embodiment, the data-only cache memory 30 and the instruction-only cache memory 40 are provided, and the cache memory 30 is provided with the address register DAR, and the cache memory 40 is provided with the address register IAR, respectively. The cache memory 30 operates only in the data bus cycle and the cache memory 40 operates only in the instruction bus cycle under the control of the data / instruction identification signal DCI from the CPU 10, so that useless access to the memory cells can be avoided. Power consumption can be reduced.

Third Embodiment FIG. 3 is a circuit diagram showing a third embodiment of the cache memory system according to the present invention. As illustrated, the system of the present embodiment includes a CPU 10, a main memory 20a, and cache memories 30 and 40. The components other than the main memory 20a are the same as the respective components of the second embodiment of the present invention shown in FIG. 2, and only the main memory 20a different from the second embodiment will be described below in detail.

As shown in FIG. 3, the main memory 20a has two address registers MAR1 and MAR2, which can hold different types of addresses. In the present embodiment,
As in the second embodiment, the data-only cache memory 30 and the instruction-only cache memory 40
Each has an address register DAR and an IAR independently. Therefore, when the CPU 10 transfers two consecutive addresses of the instruction and the data, the respective registers can hold the address of the instruction and the address of the data without conflict between the respective registers.

FIG. 4 shows an example of a timing chart of the present embodiment. FIG. 4 shows the system clock signal CL.
K, the address bus ADRBUS, and the data / instruction identification signal DCI are shown respectively. Also, here, the cache memory 30 and the cache memory 4
Assume that 0 is a look-aside cache memory with no lookup penalty and supports one-wait operation. Hereinafter, the operation of the present embodiment will be described with reference to FIG.

As shown in FIG. 4, at clock 1 of system clock signal CLK, address bus ADRBU
S has an address AD1 and a data / instruction identification signal DCI
Is output. Here, the data / command identification signal DC
Since I is set to the low level, it indicates that the bus cycle at clock 1 is an instruction bus cycle.

Therefore, in the system shown in FIG. 3, the instruction-only cache memory 40 is set to the enabled state and operates, and the data-only cache memory 30 does not operate. Therefore, the address AD1 is input to and held in the address register IAR of the cache memory 40 and the address register MAR1 of the main memory 20a. Since the cache memory 30 does not operate, the address AD1 is not input to the address register DAR.

Then, in the cache memory 40,
An address lookup operation is performed using the address AD1, and as a result of the address lookup, for example, a hit or a miss is detected by the CPU 10 by the clock 3 shown in FIG.
And output to the main memory 20a.

When only one MAR 1 is provided in the main memory 20 as in the second embodiment shown in FIG. Until the timing 3, the next address cannot be output. Because only one address can be stored in the address register of the conventional main memory 20, when a new address AD2 is input,
The address AD1 stored earlier is overwritten.
Then, if the result of the address lookup by the cache memory 40 is a mistake, the wrong address is read from the main memory 20a and transferred to the CPU 10.

In this embodiment, the main memory 20
Since a is provided with two address registers MAR1 and MAR2, the CPU 10 outputs the first address AD1 at the timing of the clock 1 and then outputs the address AD2 of the data bus cycle at the timing of the next clock 2, for example. Is output. At the same time, the output data / instruction identification signal DCI is held at, for example, a high level, indicating that clock 2 is a data bus cycle.

Then, the address AD1 in the instruction bus cycle of clock 1 is stored in the address register MAR1 of the main memory 20a, and the address AD2 in the instruction bus cycle of clock 2 is stored in the address register MAR2 of the main memory 20a.

At clock 2, since the data / instruction identification signal DCI is held at the high level, the instruction-only cache memory 40 does not operate, and the data-only cache memory 30 is set to the enabled state and operates. As a result, the address AD2 is held in the address register DAR of the cache memory 30.

Then, in the cache memory 30,
Using this address AD2, an address lookup operation is performed, and by clock 4 shown in FIG. 4, the result of the hit or miss is determined by the CPU 10 and the main memory 20a.
Is output to

Similarly, if the clock 1 is a data bus cycle, the clock 2 is an instruction bus cycle, and the instruction cache memory 30 and the main memory 20a can operate.

As described above, according to this embodiment, independent address registers DAR and IAR are provided.
Dedicated cache memory 30, instruction dedicated cache memory 40 and two address registers MAR having
1 and MAR2, a system is configured. The cache memory 30 operates in a data bus cycle, the cache memory 40 operates in an instruction bus cycle, and continuous addresses are stored in the main memory 20a.
Are stored in the two address registers MAR1 and MAR2, respectively, so that the use efficiency of the address bus ADRBUS can be improved and the performance of the entire system can be improved.

[0045]

As described above, according to the cache memory system of the present invention, the power consumption can be reduced, unnecessary operations can be omitted, the circuit configuration can be simplified, the use efficiency of the address bus and the entire system can be reduced. There is an advantage that the performance of the device can be improved.

[Brief description of the drawings]

FIG. 1 shows a first example of a cache memory system according to the present invention.
FIG. 3 is a circuit diagram showing the embodiment.

FIG. 2 shows a second example of the cache memory system according to the present invention.
FIG. 3 is a circuit diagram showing the embodiment.

FIG. 3 shows a third example of the cache memory system according to the present invention;
FIG. 3 is a circuit diagram showing the embodiment.

FIG. 4 is a timing chart of the third embodiment.

[Explanation of symbols]

10 CPU, 20 main memory, 30 40 cache memory, ADRBUS address bus, IAR,
DAR, MAR1, MAR2 ... address register, CL
K: system clock signal, ADR, AD1, AD2 ...
Address, DCI ... data / instruction identification signal.

Claims (7)

[Claims] 1. A cache memory system having a control device having at least two bus cycles, a data bus cycle and an instruction bus cycle, and outputting a data / instruction identification signal for identifying these bus cycles. A cache memory system having a cache memory that operates in only one of the data or instruction bus cycles in response to the data / instruction identification signal. 2. A cache memory system having at least two bus cycles, a data bus cycle and an instruction bus cycle, and a control device for outputting a data / instruction identification signal for identifying these bus cycles, A cache memory system comprising: a first cache memory that operates only in the data bus cycle in response to the data / instruction identification signal; and a second cache memory that operates only in the instruction bus cycle. 3. The cache memory system according to claim 1, wherein an address is output together with the data / instruction identification signal by the control device, and the first cache memory has a register for temporarily holding the address. 4. The control device outputs an address together with the data / instruction identification signal. The first cache memory temporarily stores the address, the first register temporarily stores the address, and the second cache memory stores the address. 3. The cache memory system according to claim 2, further comprising a second register for temporarily storing the address. 5. The cache memory system according to claim 1, wherein an address is output together with the data / instruction identification signal by the control device, and the main memory includes a register for temporarily holding the address. 6. The cache memory system according to claim 2, wherein an address is output together with the data / instruction identification signal by the control device, and the main memory includes a register for temporarily holding the address. 7. The cache memory system according to claim 6, wherein said main memory device has at least two registers for temporarily storing addresses of successive bus cycles.