JP2952884B2 - Cache controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache controller, and more particularly, to a cache controller including an address tag memory composed of dual-port memory cells.

[Conventional technology]

Conventionally, a cache controller including a memory for an address tag using a dual-port memory cell is:
This was as shown in the block diagram of FIG. The address tag memory 1 and the valid bit memory 10 use dual port memory cells. Therefore,
The memories 1 and 10 can operate by receiving simultaneous read accesses of the set address 20 from the CPU and the set address 30 from the main memory. The address tag 22 is read from the memory 1 in response to the access of the set address 20, and the free address 21 from the CPU is compared by the comparator 2 to output a coincidence signal 23. At the same time, a valid bit signal 35 is output from the memory 10 accessed by the set address 20, and the match signal 23 is output by the AND gate 4.
And outputs a hit signal 25. Similarly, the memory 1 and the memory 10 access the set address 30 from the main memory, while the memory 1 sends the address tag 32
Is read out, compared with the tag address 31 from the main memory by the comparator 3, and outputs a coincidence signal. at the same time,
The memory 10 accessed at the address 30 outputs a valid bit signal 36, and the AND gate 12 performs an AND operation with the coincidence signal 34.
And outputs a write access request signal 37. This signal 37 means a hit signal.

At this time, if the write access request signal 37 becomes a hit state value, the valid bit specified by the address 30 in the memory 10 is turned off, and the address tag in the memory 1 specified by the address 30 is invalidated. For this purpose, the arbiter (arbiter) 11 is activated. Since the memory 1 and the memory 10 cannot simultaneously perform read or write access from the CPU and write access from the main memory for the same address, the arbiter 11 sends the write access request signal 37 from the main memory and the CPU Access request signal 38
And an arbitration signal 39 is output to the memory 1 and the memory 10 in response to the earlier request.

[Problems to be solved by the invention]

The above-described conventional cache controller issues a write request to the valid bit when invalidating the valid bit according to the result of the rewrite monitoring of the main memory.
Since arbitration with the access request from the CPU is necessary, the CPU
Has the disadvantage that it may temporarily wait (wait) for its operation, thereby reducing CPU performance.

An object of the present invention is to monitor the rewriting of the main memory,
By providing a valid bit register that stores the validity of the address tag regardless of the access from the CPU, the CPU operation can be temporarily stopped by the rewrite monitoring operation of the main memory and the invalid bit invalidating operation. A cache that can monitor rewriting of the main memory without the need to wait and reduce the CPU performance
To provide a controller.

[Means for solving the problem]

The cache controller of the present invention comprises a dual-port memory, an address tag memory that can operate simultaneously for access from the CPU and access from the main memory, and a memory for the address free memory that is accessed from the CPU. A valid bit memory for storing the validity of the address tag, and a storage circuit for writing invalidation data corresponding to the set address of the main memory in accordance with the result of rewriting monitoring of the main memory. A valid bit register for selecting output data by the set address of the CPU and reading the validity of the address tag in the address tag memory; and a valid bit memory and the valid bit register when accessed from the CPU. Both registers indicate the validity of the address tag When that, characterized in that it comprises a logic circuit for generating a hit signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and shows only parts related to the present invention. Since the address tag memory 1 uses a dual-port memory cell, it can receive and perform simultaneous read access of the set address 20 from the CPU and the set address 30 from the main memory. In response to the access to the address 20, the address tag 22 is read from the memory 1 and compared with the tag address 21 from the CPU by the comparator 2 to output a coincidence signal 23. At the same time, a valid bit signal 33 is output from the valid bit memory 5 accessed by the set address 20, and sent to the valid bit register 6. This valid bit register 6 stores a valid bit signal 33
And whether the register bit corresponding to the address 20 is valid is determined, and a valid signal 24 is output to the AND gate 4. The AND gate 4 performs an AND operation with the coincidence signal 23 from the comparator 2. The hit signal 25 is output.

On the other hand, set address by main memory rewrite monitoring
When 30 is accessed to the memory 1, the address tag 32 is read from the memory 1, and the tag address from the main memory is read.
31 is compared with the comparator 3 and a coincidence signal 34 is output. The coincidence signal 34 is sent to the control circuit 7, and if the coincidence signal
If 34 is a status value indicating a match, the corresponding register bit of the valid bit register 6 is written "0" to turn off the valid bit. That is, set address 3
Invalidates the address tag in the memory 1 specified by 0. At this time, the valid bit specified by the set address 30 of the memory 5 is not invalidated. However, as described above, when the valid bit of the memory 5 and the valid bit of the register 6 are not valid at the time of access from the CPU,
The valid signal 24 does not become a valid state value.

Register 6 inputs the set address 30 from the main memory used to turn off the register bits, and turns on
Enter the set address 20 from the CPU to be used for setting.

The control circuit 7 receives the coincidence signal 34 of the instruction signal for turning off the register bit, and replaces the instruction signal 27 for turning on the register bit.
Enter Also, input clock 26 synchronized with CPU and
The data signal 28 set to "0" in the case of the FF instruction and set to "1" in the case of the ON instruction is sent to the register 6 together with the register write pulse 29.

It is apparent that the present invention can be realized by using a valid bit register 6 instead of the valid bit memory 5 in order to obtain the effect of the present invention. Further, the memory 1 may use a memory circuit having a similar function without using a dual-port memory cell.

FIG. 2 shows a main circuit of the present invention, a valid bit
2 shows specific circuits of a register 6 and a control circuit 7.

The register 6 has a decoder 61 for decoding the address 30, and the decode signal group 41 as an output signal uses each bit of the register 63 as an enable signal.
Further, it has a decoder 62 for decoding the address 20, and the decoded signal group 42 as an output signal is composed of each valid bit signal group 43 from the register 63 and each NAND gate group 64.
, And the output signal group 44 of the NAND gate group 64 is collectively NANDed by the NAND gate 65. That is, the output signal 45 of the NAND gate 65 indicates whether the valid bit of the address tag accessed from the CPU is valid in the register 6. Valid bit signal 33 and output signal from memory 5
The signal 45 and the AND signal 66 are ANDed and the valid signal 24 is output.

If either the replace signal 27 or the coincidence signal 34 is ON, the control circuit 7 outputs the clock signal 26 to the register 6 and writes the data signal 29 to the register 6. This data signal
29 is set to "0" by the NAND gates 73, 74 and 75 when the coincidence signal 34 is ON, and becomes "1" when the replacement signal 27 is ON.

The replace signal is generated when data of the main memory is loaded into the cache memory. In this case, the corresponding address becomes valid when the loading is completed, and the valid bit must be turned ON.
In addition, when the data in the cache memory is rewritten in the main memory by another processor or the like, the match signal invalidates the data in the cache memory so that the data in the cache memory always matches the data in the main memory. If a match signal is output at the time of the check signal, it indicates that data in the cache memory has been rewritten in the main memory.

〔The invention's effect〕

As described above, the present invention includes a valid bit register that stores the validity of an address tag as a result of monitoring the rewriting of the main memory irrespective of access from the CPU. The operation eliminates the need to temporarily wait for the operation of the CPU, and has the effect of monitoring rewriting of the main memory without deteriorating the performance of the CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a block diagram of an example of a conventional cache controller, and FIG. 3 is a block diagram of an example of a conventional cache controller. 1 ... Memory for address tag (using dual-port memory cells), 2,3 ... Comparator, 4,12,71,66 ... AND gate, 5 ... Valid bit using single-port memory cell • Memory, 6: Valid bit register, 7: Control circuit, 10: Valid bit memory using dual-port memory cells, 11: Arbiter, 20, 30, ... Set address, 21, 31 …… Tag address, 22,32 …… Address tag, 23,34 …… Match signal, 24…
… Valid signal, 25… hit signal, 26… clock (C
L), 27: Replace signal (RE), 28: Data signal, 29: Register write pulse, 33, 35, 36 ... Valid bit signal, 37 ... Write access request signal, 38 ...
Access request signal, 39 Arbitration signal, 61, 62 Decoder, 63 Register, 64, 65, 73, 74, 75 NAND gate
72 …… OR gate.

Claims (1)

(57) [Claims] 1. An address tag memory comprising a dual port memory and capable of simultaneously operating for access from a CPU and access from a main memory, and an address for access from the CPU to the address free memory. A valid bit memory for storing the validity of the tag, and a storage circuit for writing invalidation data in accordance with a set address of the main memory according to a result of rewriting monitoring of the main memory; A valid bit register for selecting the validity of the address tag in the address tag memory by selecting the set address of the CPU and the valid bit memory and the valid bit register when the CPU accesses. Hit signal when both indicate address tag validity Cache controller which comprises a logic circuit which.