JPH03167856A - Package for semiconductor-element - Google Patents
Package for semiconductor-elementInfo
- Publication number
- JPH03167856A JPH03167856A JP30860089A JP30860089A JPH03167856A JP H03167856 A JPH03167856 A JP H03167856A JP 30860089 A JP30860089 A JP 30860089A JP 30860089 A JP30860089 A JP 30860089A JP H03167856 A JPH03167856 A JP H03167856A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead terminal
- semiconductor element
- lid
- insulating base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000010949 copper Substances 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 8
- 239000000956 alloy Substances 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 229910001374 Invar Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000011029 spinel Substances 0.000 claims description 4
- 229910052596 spinel Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 239000005394 sealing glass Substances 0.000 description 21
- 239000011521 glass Substances 0.000 description 7
- 230000005291 magnetic effect Effects 0.000 description 7
- 230000035699 permeability Effects 0.000 description 7
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 229910000833 kovar Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- -1 Ni) and cobal (Co) Chemical class 0.000 description 1
- 229910000691 Re alloy Inorganic materials 0.000 description 1
- 229910006853 SnOz Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910000174 eucryptite Inorganic materials 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000003003 spiro group Chemical group 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 229910052844 willemite Inorganic materials 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子を収容する半導体素子収納用パッケ
ージの改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a semiconductor element housing package that houses a semiconductor element.
（従来の技術）
従来、半導体素子を収容するためのパッケージ、特にガ
ラスの溶着によって封止するガラス封止型半導体素子収
納用バッケージは、絶縁基体と蓋体とから成り、内部に
半導体素子を収容する空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に電気的に接
続するための外部リード端子とから構威されており、絶
縁基体及び蓋体の相対向する主面に予め封止用のガラス
部材を被着形威すると共に、絶縁基体主面に外部リード
端子を固定し、半導体素子の各電極と外部リード端子と
をワイヤボンド接続した後、絶縁基体及び蓋体のそれぞ
に被着させた封止用のガラス部材を溶融一体化させるこ
とによって内部に半導体素子を気密に封止している。(Prior Art) Conventionally, a package for accommodating a semiconductor device, particularly a glass-sealed semiconductor device storage package sealed by glass welding, consists of an insulating base and a lid, and the semiconductor device is housed inside. The structure consists of an insulating container having a cavity, and an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit, and an insulating base and a lid facing each other. A glass member for sealing is preliminarily applied to the main surface of the insulating substrate, external lead terminals are fixed to the main surface of the insulating substrate, and each electrode of the semiconductor element and the external lead terminal are connected by wire bonding. A semiconductor element is hermetically sealed inside by melting and integrating a sealing glass member attached to each lid.
（発明が解決しようとする課題）
しかし乍ら、この従来のガラス封止型半導体素子収納用
パッケージは通常、外部リード端子がコバール（２９
ＷｔχＮｉ−１６ Ｗｔｌ Ｃｏ−５５ ＷｔＸＦｅ合
金）や４２ＡＩｌｏｙ（４２ ＷｔＸ Ｎｉ−５８ Ｗ
ｔχＰｅ合金）の導電性材料から成っており、該コバー
ルや４２＾１ ｔｏｙ等は透磁率が高く、且つ導電率が
低いことから以下に述ベる欠点を有する。(Problem to be Solved by the Invention) However, in this conventional glass-sealed package for storing semiconductor elements, the external lead terminals are usually made of Kovar (29
WtχNi-16 Wtl Co-55 WtXFe alloy) and 42AIloy (42 WtX Ni-58 W
Kovar, 42^1 toy, and the like have high magnetic permeability and low conductivity, so they have the following drawbacks.
即ち、
■コバールや４２Ａ１１ｏｙは鉄（Ｆｅ）、ニッケル（
Ｎｉ）、コバル｝ （Ｃｏ）といった強磁性体金属のみ
から戒っており、その透磁率は２５０〜７００ （ＣＧ
Ｓ）と高い。そのためこのコバールや４２Ａｌｌｏｙ等
から成る外部リード端子に電流が流れると外部リード端
子中に透磁率に比例した大きな自己インダクタンスが発
生し、これが逆起電力を誘発してノイズとなると共に、
該ノイズが半導体素子に入力されて半導体素子に誤動作
を生じさせる、
■コバールや４２Ａ１ １ｏｙはその導電率が３．０〜
３．５χ（ＩＡＣＳ）と低い。そのためこのコバーノレ
や４２Ａ１１ｏｙ等から成る外部リード端子に信号を伝
搬させた場合、信号の伝搬速度が極めて遅いものとなり
、高速駆動を行う半導体素子はその収容が不可となって
しまう、
■半導体素子収納用パッケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記■に
記載のコバールや４２Ａｌｌｏｙの導電率が低いことと
相俊って電気抵抗が極めて大きなものになってきており
、外部リード端子に信号を伝搬させると、該外部リード
端子の電気抵抗に起因して信号が大きく減衰し、内部に
収容する半導体素子に信号を正確に入力することができ
ず、半導体素子に誤動作を生しさせてしまう、
等の欠点を有していた。That is, ■ Kovar and 42A11oy are iron (Fe) and nickel (
It is strictly prohibited to use ferromagnetic metals such as Ni) and cobal (Co), whose magnetic permeability is 250 to 700 (CG
S) and high. Therefore, when a current flows through the external lead terminal made of Kovar, 42Alloy, etc., a large self-inductance proportional to the magnetic permeability is generated in the external lead terminal, which induces a back electromotive force and causes noise.
The noise is input to the semiconductor device and causes the semiconductor device to malfunction. Kovar and 42A1 1oy have a conductivity of 3.0 to 3.0.
It is low at 3.5χ (IACS). Therefore, when a signal is propagated to an external lead terminal made of this cover or 42A11oy, the signal propagation speed becomes extremely slow, making it impossible to accommodate semiconductor devices that drive at high speed. With the progress of higher density and higher integration of semiconductor elements housed inside packages, the number of electrodes on semiconductor elements has increased significantly. The line width has also become extremely thin. Therefore, the electrical resistance of external lead terminals has become extremely large due to the low conductivity of Kovar and 42Alloy described in (2) above, and when a signal is propagated to the external lead terminals, The signal was greatly attenuated due to the electrical resistance of the device, making it impossible to accurately input the signal to the semiconductor device housed inside, which could cause the semiconductor device to malfunction. .
（発明の目的）
本発明は上記欠点に鑑み案出されたもので、その目的は
外部リード端子で発生するノイズ及び外部リード端子に
おける信号の減衰を極小となし、内部に収容する半導体
素子への信号の入出力を確実に行うことを可能として半
導体素子を長期間にわたり正常、且つ安定に作動させる
ことができる半導体素子収納用パッケージを提供するこ
とにある。(Object of the Invention) The present invention was devised in view of the above drawbacks, and its purpose is to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal, and to minimize the noise generated at the external lead terminal and the attenuation of the signal at the external lead terminal. It is an object of the present invention to provide a package for storing a semiconductor element, which enables reliable input and output of signals and allows the semiconductor element to operate normally and stably for a long period of time.
また本発明の他の目的は高速駆動を行う半導体素子を収
容することができる半導体素子収納用パフケージを提供
することにある。Another object of the present invention is to provide a puff cage for storing semiconductor devices that can accommodate semiconductor devices that are driven at high speed.
（課題を解決するこめの手段）
本発明は絶縁基体と蓋体とから或り、内部に半導体素子
を収容するための空所を有する絶縁容器と、該容器内に
収容される半導体素子を外部電気回路に接続するための
外部リード端子とから成る半導体素子収納用バソケージ
において、前記絶縁基体及び蓋体をスピネルもしくはス
テアタイト質焼結体で、外部リード端子をインバー合金
から成る板状体の上下面に、該板状体の厚みに対し４０
乃至６０χの厚みの銅板を接合させた金属体で形威した
ことを特徴とするものである。(Further Means for Solving the Problems) The present invention provides an insulating container comprising an insulating base and a lid and having a cavity for accommodating a semiconductor element therein, and an insulating container for accommodating a semiconductor element housed in the container from the outside. In a bass cage for storing semiconductor elements, which is composed of an external lead terminal for connection to an electric circuit, the insulating base and the lid are made of a spinel or steatite sintered body, and the external lead terminal is made of a plate-like body made of an invar alloy. 40 to the thickness of the plate-like body on the lower surface.
It is characterized by being made of a metal body to which copper plates having a thickness of 60 to 60x are bonded.
（実施例） 次に本発明を添付図面に基づき詳細に説明する。(Example) Next, the present invention will be explained in detail based on the accompanying drawings.
第１図及び第２図は本発明の半導体素子収納用パッケー
ジの一実施例を示し、■は絶縁基体、２は蓋体である。FIGS. 1 and 2 show an embodiment of a package for storing semiconductor elements according to the present invention, in which .largecircle. is an insulating base and 2 is a lid.
この絶縁基体１と蓋体２とにより絶縁容器３が構威され
る。The insulating base 1 and the lid 2 constitute an insulating container 3.
前記絶縁基体ｌ及び蓋体２はそれぞれの中央部に半導体
素子を収容する空所を形成するための凹部が設けてあり
、絶縁基体１の凹部底面には半導体素子４が樹脂、ガラ
ス、ロウ剤等の接着剤を介し取着固定される。The insulating base 1 and the lid 2 are each provided with a recess in the center thereof to form a cavity for accommodating the semiconductor element, and the semiconductor element 4 is placed on the bottom of the recess of the insulating base 1 with resin, glass, or brazing agent. It is attached and fixed via adhesive such as.
前記絶縁基体１及び蓋体２はスビネルもしくはステアタ
イト質焼結体から成り、第１図に示すような絶縁基体１
及び蓋体２に対応した形状を有するプレス型内に、スピ
ネルの場合はマグネシア（ＭｇＯ）、アルミナ（ ＡＩ
２０３ ）等の原料粉末を、ステアタイト質焼結体の場
合はマグネシア（ＭｇＯ） 、シリカ（ＳｉＯｚ）等の
原料粉末を充填させるとともに一定圧力を印加して威形
し、しかる後、成形品を約１２００〜１７００℃の温度
で焼戒することによって製作される。The insulating base 1 and the lid 2 are made of Subinel or steatite sintered body, and the insulating base 1 as shown in FIG.
In the case of spinel, magnesia (MgO) and alumina (AI
In the case of a steatite sintered body, raw material powder such as 203) is filled with raw material powder such as magnesia (MgO) or silica (SiOz), and a constant pressure is applied to shape it, and then the molded product is shaped. It is produced by firing at a temperature of about 1200 to 1700 degrees Celsius.
尚、前記絶縁基体１及び蓋体２を形戒するスピ不ルもし
くはステアタイト質焼結体はその熱膨張係数が７０〜８
５Ｘ１０−’／ ”Ｃであり、後述する封止用ガラス部
材の熱膨張係数との関係において絶縁基体ｌ及び蓋体２
と到止用ガラス部材間に大きな熟？張の差が生じること
はない。The thermal expansion coefficient of the spiro or steatite sintered body forming the insulating base 1 and the lid 2 is 70 to 8.
5X10-'/''C, and in relation to the thermal expansion coefficient of the sealing glass member described later, the insulating base l and the lid body 2
And the big ripe between the glass parts for reaching? There will be no difference in tension.
また前記絶縁基体１及び蓋体２にはその相対向する主面
に封止用のガラス部材６が予め被着形或されており、該
絶縁基体１及び蓋体２の各々に被着されている封止用ガ
ラス部材６を加熱溶融させ一体化させることによりｗＡ
縁容器３内の半導体素子４を気密に封止する。Furthermore, a sealing glass member 6 is attached in advance to the main surfaces of the insulating base 1 and the lid 2 that face each other, and is attached to each of the insulating base 1 and the lid 2. By heating and melting the sealing glass member 6 and integrating it, wA
The semiconductor element 4 inside the edge container 3 is hermetically sealed.
前記絶縁基体１及び蓋体２の相対向する主面に被着され
る封止用ガラス部材６は、例えばホウケイ酸鉛系ガラス
にフイラーを添加したものから成り、原料粉末としての
酸化鉛（ ＰｂＯ ）７０．０〜９０．０ＷｔＸ 、酸
化ホウ素（ Ｂｚ０３）１２．０〜１３．０％１ｔχ、
シリカ（ＳｉＯ■）０．５〜３，Ｑ ＷｔＸ及びアルξ
ナ（＾１ｔＱ，）Ｑ，５〜３．０ ＷｔＸ ニ７ ４
’ｙ一としてチタン酸鉛（ＰｂＴｉＯ：＋）、β−ユー
クリプタイト（ＬｉＪ１２Ｓ１ｚＯｓ） 、コージライ
ト（ＭｇｚＡｌ＊ＳｉｓＯｔａ）、ジルコン（ＺｒＳｉ
０４）、醇化スズ（ＳｎＯｚ）、ウイレマイト（Ｚｎｚ
ＳｉＯ＃）等を１５〜３０Ｖｏ１χ添加混合すると共に
、該混合粉末を９５０〜１１００℃の温度で加熱溶融さ
せることによって製作される。このホウケイ酸鉛系のガ
ラスはその熱膨張係数が６０〜９０Ｘ１０−’／ ’Ｃ
である。The sealing glass member 6 adhered to the opposing main surfaces of the insulating base 1 and the lid 2 is made of, for example, lead borosilicate glass with a filler added, and is made of lead oxide (PbO) as a raw material powder. ) 70.0~90.0WtX, boron oxide (Bz03) 12.0~13.0%1tχ,
Silica (SiO■) 0.5-3, Q WtX and Al ξ
Na(＾1tQ,)Q,5～3.0 WtX Ni7 4
Lead titanate (PbTiO:+), β-eucryptite (LiJ12S1zOs), cordierite (MgzAl*SisOta), zircon (ZrSi
04), tin acidified (SnOz), willemite (Znz
It is manufactured by adding and mixing 15 to 30 Vo1χ of SiO#), etc., and heating and melting the mixed powder at a temperature of 950 to 1100°C. This lead borosilicate glass has a thermal expansion coefficient of 60 to 90X10-'/'C.
It is.
前記封止用ガラス部材６はその熱膨張係数が６０〜９０
ｘｌＯ−’／ ”ｃであり、絶縁基体１及び蓋体２の各
々の熱膨張係数と近似することから絶縁基体１及び蓋体
２の各々に被着されている封止用ガラス部材６を加熱溶
融させ一体化させることにより絶縁容器３内の半導体素
子４を気密に封止する際、絶縁基体１及び蓋体２と封止
用ガラス部材６との間には両者の熱膨張係数の相違に起
因する熱応力が発生することは殆どなく、絶縁基体１と
蓋体２とを封止用ガラス部材６を介し強固に接合するこ
とが可能となる。The sealing glass member 6 has a thermal expansion coefficient of 60 to 90.
xlO-'/''c, which approximates the coefficient of thermal expansion of each of the insulating base 1 and the lid 2, so the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is heated. When the semiconductor element 4 in the insulating container 3 is hermetically sealed by melting and integrating, there is a difference in thermal expansion coefficient between the insulating base 1 and lid 2 and the sealing glass member 6. Almost no resulting thermal stress occurs, and it becomes possible to firmly join the insulating base 1 and the lid 2 via the sealing glass member 6.
尚、前記封止用ガラス部材６はフィラーを添加したホウ
ケイ酸鉛系ガラスの粉末に適当な有機溶剤、溶媒を添加
して得たガラスペーストを従来周知の厚膜手法を採用す
ることによって絶縁基体１及び蓋体２の相対向する主面
に被着形成される。The sealing glass member 6 is made by applying a well-known thick film method to a glass paste obtained by adding a suitable organic solvent to a filler-added lead borosilicate glass powder to form an insulating substrate. 1 and lid body 2, which are opposite to each other.
また前記封止用ガラス部材６はフィラーを添加したホウ
ケイ酸鉛系のガラスに限定されるものではなく、熱膨張
係数が６０〜９０ｘｌＯ−？／ ℃の範囲のガラスであ
ればいかなるものでも使用することができる。Further, the sealing glass member 6 is not limited to lead borosilicate glass containing filler, and has a coefficient of thermal expansion of 60 to 90xlO-? /°C any glass can be used.
前記絶縁基体１と蓋体２との間には導電性材料から成る
外部リード゜端子５が配されており、該外部リード端子
５は半導体素子４の各電極がワイヤ７を介し電気的に接
続され、外部リード端子５を外部電気回路に接続するこ
とによって半導体素子４が外部電気回路に接続されるこ
ととなる。An external lead terminal 5 made of a conductive material is arranged between the insulating base 1 and the lid 2, and each electrode of the semiconductor element 4 is electrically connected to the external lead terminal 5 via a wire 7. By connecting the external lead terminals 5 to the external electrical circuit, the semiconductor element 4 is connected to the external electrical circuit.
前記外部リード端子５は絶縁基体１と蓋体２の相対向す
る主面に被着させた封止用ガラス部材６を溶融一体化さ
せ、絶縁容器３を気密封止する際に同時に絶縁基体ｌと
蓋体２との間に取着される。The external lead terminal 5 is formed by melting and integrating the sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating base l when the insulating container 3 is hermetically sealed. and the lid body 2.
前記外部リード端子５はインバー合金から成る板状体の
上下面に、該板状体の厚みに対し４０乃至６０χの厚み
の銅板を接合させた金属体から成り、その透磁率は約２
００（ＣＧＳ）、導電率は５１．１２（ＩＡＣＳ）、熱
膨張係数は約８２ＸＩＯ−’／ ’Ｃである。The external lead terminal 5 is made of a metal body in which copper plates having a thickness of 40 to 60x relative to the thickness of the plate body are bonded to the upper and lower surfaces of a plate body made of an invar alloy, and its magnetic permeability is approximately 2.
00 (CGS), conductivity is 51.12 (IACS), and coefficient of thermal expansion is approximately 82XIO-'/'C.
尚、前記外部リード端子５はインバー合金（３６．５れ
χＮｉ−６３．５ Ｗｔ！ ｒｅ合金）から成る板状体
の上下面に銅（Ｃｕ）板を圧接し、しかる後、これを圧
延することによって形威される。The external lead terminals 5 are made by pressing copper (Cu) plates onto the upper and lower surfaces of a plate-shaped body made of an invar alloy (36.5×Ni-63.5 Wt! re alloy), and then rolling this. It is shaped by this.
また前記外部リード端子５は板状体と銅板の厚みが上述
の範囲を外れると外部リード端子５は透磁率が所望する
低い値に、導電率が高い値にならず、また熱膨張係数も
絶縁基体及び蓋体の熱膨張係数と合わなくなる。そのた
め外部リード端子５はインバー合金から成る板状体の上
下面に、該板状体の厚みに対し４０乃至６０χの厚みの
銅板を接合させた金属体で形成することに限定される。Furthermore, if the thickness of the plate-like body and the copper plate of the external lead terminal 5 is outside the above range, the external lead terminal 5 will not have the desired low magnetic permeability or high conductivity, and the thermal expansion coefficient will also be insulated. The coefficient of thermal expansion does not match that of the base and lid. Therefore, the external lead terminals 5 are limited to being formed of a metal body made by bonding copper plates having a thickness of 40 to 60x with respect to the thickness of the plate-like body on the upper and lower surfaces of a plate-like body made of an invar alloy.
前記外部リード端子５はその透磁率が２００ （ＣＧＳ
）であり、ｉ３ｍ率が低いことから外部リード端子５に
電流が流れたとしても外部リード端子５中には大きな自
己インダクタンスが発生することはなく、その結果、前
記自己インダクタンスにより誘発される逆起電力に起因
したノイズを極小となし、内部に収容する半導体素子４
を常に正常に作動させることができる。The external lead terminal 5 has a magnetic permeability of 200 (CGS
), and since the i3m ratio is low, even if a current flows through the external lead terminal 5, a large self-inductance is not generated in the external lead terminal 5, and as a result, the back electromotive force induced by the self-inductance is Semiconductor element 4 that minimizes noise caused by electric power and houses it inside.
can always operate normally.
また前記外部リード端子５はその導電率が５１．１χ（
ＩＡＣＳ）以上であり、電気を流し易いことから外部リ
ード端子５の信号伝搬速度を極めて速いものとなすこと
ができ、絶縁容器３内に収容した半導体素子４を高速駆
動させたとしても半導体素子４と外部電気回路との間に
おける信号の出し入れは常に安定、且つ確実となすこと
ができる。Further, the external lead terminal 5 has a conductivity of 51.1χ(
IACS), and since electricity can easily flow, the signal propagation speed of the external lead terminal 5 can be made extremely fast, and even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, the semiconductor element 4 The input/output of signals between the external electric circuit and the external electric circuit can always be performed stably and reliably.
また同時に外部リード端子５の導電率が高いことから外
部リード端子５の線幅が細くなったとしても外部リード
端子５の電気抵抗を低く抑えることができ、その結果、
外部リード端子５における信号の減衰を極小として内部
に収容する半導体素子４に外部電気回路から供給される
電気信号を正確に入力することができる。At the same time, since the conductivity of the external lead terminal 5 is high, even if the line width of the external lead terminal 5 becomes thin, the electrical resistance of the external lead terminal 5 can be kept low, and as a result,
By minimizing the attenuation of the signal at the external lead terminal 5, it is possible to accurately input the electrical signal supplied from the external electrical circuit to the semiconductor element 4 housed inside.
また更に前記外部リード端子５はその熱膨張係数が約８
２Ｘ１０−’／ ’Ｃであり、封止用ガラス部材６の熱
膨張係数と近似することから外部リード端子５を絶縁基
体ｌと蓋体２の間に封止用ガラス部材６を用いて固定す
る際、外部リード端子５と封止用ガラス部材６との間に
は両者の熱膨張係数の相違に起因する熱応力が発生する
ことはなく、外部リード端子５を封止用ガラス部材６で
強固に固定することも可能となる。Furthermore, the external lead terminal 5 has a coefficient of thermal expansion of about 8.
2X10-'/'C, which approximates the coefficient of thermal expansion of the sealing glass member 6, so the external lead terminal 5 is fixed between the insulating base l and the lid 2 using the sealing glass member 6. At this time, no thermal stress is generated between the external lead terminal 5 and the sealing glass member 6 due to the difference in coefficient of thermal expansion between the two, and the external lead terminal 5 is firmly secured by the sealing glass member 6. It is also possible to fix it.
かくして、この半導体素子収納用パッケージによれば絶
縁基体ｌの凹部底面に半導体素子４を取着固定するとと
もに該半導体素子４の各電極をボンディングワイヤ７に
より外部リード端子５に接続させ、しかる後、絶縁基体
ｌと蓋体２とを該絶縁基体ｌ及び蓋体２の相対向する主
面に予め被着させておいた封止用ガラス部材６を溶融一
体化させることによって接合させ、これによって最終製
品としての半導体装置が完或する。Thus, according to this semiconductor element storage package, the semiconductor element 4 is attached and fixed to the bottom surface of the recess of the insulating substrate l, and each electrode of the semiconductor element 4 is connected to the external lead terminal 5 by the bonding wire 7, and then, The insulating base 1 and the lid 2 are joined together by melting and integrating the sealing glass member 6 that has been previously attached to the opposing main surfaces of the insulating base 1 and the lid 2, and thereby the final The semiconductor device as a product is completed.
（発明の効果）
本発明の半導体素子収納用パフケージによれば、半導体
素子を収容するための絶縁容器を構或する絶縁基体及び
蓋体をスピネルもしくはステアタイト質焼結体で、外部
リード端子をインバー合金から成る板状体の上下面に、
該板状体の厚みに対し４０乃至６０ｍの厚みの銅板を接
合させた透磁率が約２００ （ＣＧＳ）、導電率が５１
．１χ（ＩＡＣＳ） 、熱膨張係数が約８２Ｘ１０−’
／ ”Ｃの金属体で形成したことから外部リード端子に
電流を流したとしても該外部リード端子中に大きな自己
インダクタンスが発生することはなく、その結果、前記
自己インダクタンスにより誘発される逆起電力に起因し
たノイズを極小となし、内部に収容する半導体素子を常
に正常に作動させることが可能となる。(Effects of the Invention) According to the puff cage for storing semiconductor devices of the present invention, the insulating base and the lid, which constitute the insulating container for accommodating the semiconductor devices, are made of spinel or steatite sintered body, and the external lead terminals are connected to the puff cage. On the top and bottom surfaces of the plate-shaped body made of Invar alloy,
A copper plate with a thickness of 40 to 60 m is bonded to the thickness of the plate, and the magnetic permeability is approximately 200 (CGS) and the electrical conductivity is 51.
．． 1χ (IACS), thermal expansion coefficient is approximately 82X10-'
/ Since it is formed from a metal body of C, even if a current is passed through the external lead terminal, a large self-inductance will not be generated in the external lead terminal, and as a result, the back electromotive force induced by the self-inductance will be reduced. It is possible to minimize the noise caused by this, and to always operate the semiconductor element housed inside normally.
また外部リード端子の信号伝搬速度を極めて速いものと
なすことができ、絶縁容器内に収容した半導体素子を高
速駆動させたとしても半導体素子と外部電気回路との間
における信号の出し入れを常に安定、且つ確実となすこ
とが可能となる。In addition, the signal propagation speed of the external lead terminal can be made extremely fast, so that even if the semiconductor element housed in the insulating container is driven at high speed, the signal input and output between the semiconductor element and the external electric circuit is always stable. Moreover, it becomes possible to do so reliably and reliably.
更に外部リード端子の線幅が細くなったとしても外部リ
ード端子の電気抵抗を低く抑えることができ、その結果
、外部リード端子における信号の減衰を極小として内部
に収容する半導体素子に外部電気回路から供給される電
気信号を正確に入力することが可能となる。Furthermore, even if the line width of the external lead terminal becomes thinner, the electrical resistance of the external lead terminal can be kept low, and as a result, the attenuation of the signal at the external lead terminal is minimized, and the external electrical circuit is connected to the semiconductor element housed inside. It becomes possible to accurately input the supplied electrical signal.
また更に外部リード端子はその熱膨張係数が絶縁基体、
蓋体及び封止用ガラス部材の各々の熱膨張係数と近似し
、絶縁基体と蓋体との間に外部リード端子を挟み、各々
を封止用ガラス部材で取着接合したとしても絶縁基体及
び蓋体と封止用ガラス部材との間、外部リード端子と封
止用ガラス部材との間のいずれにも熱膨張係数の相違に
起因する熱応力は発生せず、すべてを強固に取着接合す
ることも可能となる。Furthermore, the coefficient of thermal expansion of the external lead terminal is
The coefficient of thermal expansion is similar to that of each of the lid body and the sealing glass member, and even if an external lead terminal is sandwiched between the insulating base body and the lid body and each is attached and bonded with the sealing glass member, the insulating base and No thermal stress is generated between the lid and the sealing glass member, nor between the external lead terminal and the sealing glass member due to differences in thermal expansion coefficients, and all are firmly attached and bonded. It is also possible to do so.
第１図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第２゛図は第１図に示すパソケージの
絶縁基体上面より見た平面図である。
ｌ ・・絶縁基体 ２ ・・蓋体
３ ・・絶縁容器
５ ・・外部リード端子
６ ・・封止用ガラス部材FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor element storage package of the present invention, and FIG. 2 is a plan view of the insulating base of the PASO cage shown in FIG. 1, viewed from above. l...Insulating base 2...Lid 3...Insulating container 5...External lead terminal 6...Glass member for sealing
Claims (1)
するための空所を有する絶縁容器と、該容器内に収容さ
れる半導体素子を外部電気回路に接続するための外部リ
ード端子とから成る半導体素子収納用パッケージにおい
て、前記絶縁基体及び蓋体をスピネルもしくはステアタ
イト質焼結体で、外部リード端子をインバー合金から成
る板状体の上下面に、該板状体の厚みに対し４０乃至６
０％の厚みの銅板を接合させた金属体で形成したことを
特徴とする半導体素子収納用パッケージ。An insulating container consisting of an insulating base and a lid and having a cavity for accommodating a semiconductor element therein, and an external lead terminal for connecting the semiconductor element housed in the container to an external electric circuit. In the package for storing semiconductor elements, the insulating base and the lid are made of spinel or steatite sintered body, and the external lead terminals are formed on the upper and lower surfaces of a plate-like body made of an invar alloy. 6
A package for storing semiconductor elements, characterized in that it is formed of a metal body bonded with 0% thick copper plates.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30860089A JP2691305B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
| US07/573,406 US5057905A (en) | 1989-08-25 | 1990-08-24 | Container package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30860089A JP2691305B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03167856A true JPH03167856A (en) | 1991-07-19 |
| JP2691305B2 JP2691305B2 (en) | 1997-12-17 |
Family
ID=17982991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30860089A Expired - Fee Related JP2691305B2 (en) | 1989-08-25 | 1989-11-27 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2691305B2 (en) |
-
1989
- 1989-11-27 JP JP30860089A patent/JP2691305B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2691305B2 (en) | 1997-12-17 |
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| Date | Code | Title | Description |
|---|---|---|---|
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