JPH03167820A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable steady lift-off through electron beam exposure by removing a developed and exposed alignment mark to expose the substrate and using an etched step as a spacer for lift-off. CONSTITUTION:An active layer 12, a source electrode 13, a drain electrode 14 and alignment mark 15 are formed on a GaAs substrate 11. The substrate is coated with resist film 16, and irradiated with an electron beam 17 between electrodes 13 and 14 to form openings 18a and 18b. Etchant is applied through the opening 18b to remove the mark 15 selectively. The active layer and the substrate 11 are etched through the openings 18a and 18b to form recesses. Metal film 19 for the gate electrode is deposited, and it is removed from the resist film 16. The metal film of the mark 15 is removed in the area of the opening 18b in this structure. Therefore, the substrate 11 is etched, and it is easy to the lift-off of the film 19 using the etched step as a spacer.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device. (Prior Art) The minimum processing dimensions required in the manufacturing process of semiconductor devices have become significantly finer. In particular, the gate electrode dimensions of microwave semiconductor devices using compound semiconductors such as gallium arsenide (GaAS) have already reached 0. 25. The following has been achieved. Electron beam exposure technology using an electron beam is widely used as a method for processing such fine patterns. In order to form a pattern on a semiconductor substrate using electron beam exposure, it is necessary to accurately align the existing pattern with the electron beam. For this purpose, alignment marks for electron beam exposure (hereinafter referred to as alignment marks) with a cross-shaped or L-shaped planar shape are formed on the semiconductor substrate, and the alignment marks are scanned with an electron beam. After detecting marks, the positional relationship between the existing pattern and the electron beam is determined, and corrections are made to achieve highly accurate positioning. Generally, a metal film with a large signal-to-noise ratio (S/N ratio) of a detection signal is often used for this alignment mark. FIG. 2 shows a process diagram for forming a gate electrode pattern of a Schottky barrier field effect transistor (MESFET) using GaAs by electron beam exposure. As shown in FIG. 2(a), a semi-insulating GaAs substrate 1
An active layer 102 is stacked on 01, and a source electrode 103, a drain electrode 104, and a semi-insulating GaA layer are stacked on the active layer 102.
Alignment marks 105 made of gold (Au) are formed on the s substrate, and after coating the entire surface with a positive resist film 106, the area including the alignment marks 105 is scanned with an electron beam 107 to mark the marks. perform the detection,
An electron beam 7 is irradiated between the source electrode 103 and the drain electrode 104 to expose the resist film 106 according to the shape of the gate electrode pattern. Next, when the resist film 106 is developed, the portions of the resist film 106 irradiated with the electron beam 107 have openings 108a as shown in FIG. 2(b).
108b is formed. Figure 2 (C) is Figure 2 (b)
FIG. The L-shaped alignment mark 105 has openings 108x and 108y formed by mark detection in the X and Y directions. For example, taking into account the exposure time per wafer and highly accurate and stable mark detection, set the electron beam exposure conditions to beam current = 0.
．． 2nA, beam shot time during mark detection = 10μ
sec, beam spacing=0.1. , number of beam scans = I
In the case of O times, the amount of electrons (dose) irradiated to the resist film on the alignment mark is ((beam current/beam shot time)/beam interval)
- Number of scans = 20C/am. This value is approximately the same as the optimum dose of an electron beam resist such as PMMA (polymethyl methacrylate), and the thickness of the resist film 106 on the alignment mark 105 is thicker than on other parts. The resist film 10 on the alignment mark 105 after development is thinner by the film thickness of .
6 will be removed. Note that FIG. 2(b) is a sectional view taken along the dashed line AA in FIG. 2(c).

Subsequently, as shown in FIG. 2(d), the active layer 102 is recess-etched to a predetermined depth through the opening 108, and a gate electrode metal film 109 is deposited. The purpose of recess etching is to control the saturated drain current of the MESFET, reduce the source resistance, and form a lift-off spacing layer when forming the gate electrode. In FIG. 2(d), since the alignment mark 5 is not attacked by the GaAs etchant during recess etching, the gate electrode metal film 1
09, the metal film 109 on the resist film 6 and the metal film 109 on the alignment mark 105 are connected, and the metal film 10 on the resist film 106 due to the lift-off.
There was a problem in that it became impossible to remove 9, making it difficult to form the gate electrode of the MESFET.

As a method to solve the above problem, the resist film 105 on the alignment mark 105 is changed by changing the mark detection conditions such as beam current, beam shot time, beam interval, and number of scans.
Although it is possible to consider a method of suppressing the dose of resist film 106 below the optimum dose of the resist film 106 so that the alignment mark 105 is not exposed after development, the following problems occur in throughput, mark detection, etc.

(1) The time required for electron beam exposure is approximately proportional to the beam current. Therefore, reducing the beam current is
The time required for exposure increases accordingly, resulting in a decrease in throughput. (2) In the method of shortening the beam shot time, the signal strength to be detected becomes weaker, the S/N ratio decreases, and stable mark detection becomes difficult.

(3) The method of widening the beam spacing reduces the positional accuracy of mark detection and increases the pattern overlay error. (4) The method of reducing the number of scans reduces the amount of data required for averaging processing of mark detection signals, resulting in a decrease in pattern overlay accuracy. Therefore, in order to perform highly accurate and stable mark detection without increasing the exposure time per wafer, it is necessary to irradiate the resist film on the alignment mark with the same amount of electron beam as the electrode pattern area. There is. Furthermore, the PMM is used as a resist film.
When using a resist film with higher sensitivity than A, the resist film 106 on the alignment mark 105 is irradiated with an electron beam that is larger than the optimum dose, so the alignment mark 5 is exposed after the development process. It is impossible to avoid this. (Problems to be Solved by the Invention) As described above, with conventional alignment marks, when attempting to perform highly accurate and stable mark detection without increasing the exposure time per wafer, it is difficult to There was a problem in that it was difficult to shape the electrode pattern using the lift-off method because the alignment marks were exposed by electron beam irradiation.The present invention eliminates this drawback and forms the electrode pattern using the lift-off method. The purpose of this invention is to provide a method for manufacturing semiconductor devices that can perform highly accurate and stable mark detection without increasing the exposure time per wafer when forming a pattern. [Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of forming alignment marks for electron beam exposure on a semiconductor substrate, and a step of forming a resist on the semiconductor substrate. After applying the film, a step of irradiating the resist film in a region including the alignment mark for electron beam exposure with an electron beam, and a step of irradiating the resist film on the semiconductor substrate with an electron beam according to a predetermined pattern. a step of developing the resist film to form an opening in the resist film; etching away at least a portion of the alignment mark for electron beam exposure through the opening, and then removing the semiconductor substrate from the opening. The method is characterized in that it includes a step of etching away through the hole to a predetermined depth. (Function) In the method for manufacturing a semiconductor device of the present invention, the alignment mark exposed after the development process is etched away to expose the semiconductor substrate, and the step created by the subsequent etching of the semiconductor substrate is replaced with a spacer layer for lift-off. By doing so, stable lift-off is possible even with electron beam exposure. (Example) An example of the present invention will be described with reference to the drawings.

As shown in FIG. 1(a), a semi-insulating GaAs substrate 11
An active layer 12 is laminated thereon, a source electrode 13 and a drain electrode l4 are formed on the active layer l2, and alignment marks 15 made of a metal film such as gold (Au) are formed on the semi-insulating GaAs substrate 11. After applying a positive type resist film l6 to the entire surface, the area including the alignment mark l5 is scanned with an electron beam l7 to detect the mark.
An electron beam 17 is irradiated between the source electrode 13 and the drain electrode 14 to expose the resist film 16 according to the shape of the gate electrode pattern. Next, when the resist film 16 is developed, openings 18a and 18b as shown in FIG. 1(b) are formed in the resist film 17 at the portions irradiated with the electron beam 17. #! Then, as shown in FIG. 1(C), the alignment mark 15 is removed by etching with an aqueous solution of Enstrip AU-78 (product name: manufactured by Japan Metal Finishing Kanbani) through the hole 18b, and then the hole is opened. The active layer 12 is recessed through the opening 18a, and the semi-insulating GaAs substrate 1l is recessed to a predetermined depth through the opening 18b. Here, the active layer 12 made of GaAs
Since the marks are not etched by the Enstrip AIJ-78 aqueous solution, only the alignment marks are selectively etched. Next, as shown in FIG. 1(d), after depositing the gate electrode metal film 19, the gate electrode metal film 19 on the resist film 16 is removed by a lift-off method, as shown in FIG. 1(e). The MESFET shown in is demonstrated.
In FIG. 1(d), there is no metal film of the alignment mark 15 in the part where the resist film 17 is opened, and the GaAs substrate l1 is etched away during recess etching, and the step created by this etching is used as a spacer for lift-off. By forming a layer, lift-off of the gate electrode metal film 19 can be easily performed without any problem, as shown in FIG. In the above embodiment, Au is used as the alignment mark, but Ni-AuGe or Au-AuGe formed simultaneously with the source electrode and the drain electrode and of the same metal may also be used. Furthermore, the present invention is not limited to the shape or process of the gate electrode, but can of course be widely applied to source electrodes, drain electrodes, and other pattern shapes formed using the lift-off method. Furthermore, the present invention is also effective for manufacturing semiconductor devices using other charged beams such as ion beams. Furthermore, the method of exposing the resist film is not limited to electron beams, but it is also effective to use other charged beams such as ion beams.

〔Effect of the invention〕

As described above, in the method for manufacturing a semiconductor device according to the present invention, the alignment mark exposed by electron beam irradiation during mark detection is etched away, so that the electrode pattern can be easily formed by the lift-off method6. Since mark detection can be performed stably with high precision without increasing the exposure time per wafer, it has the remarkable effect of providing a method for manufacturing semiconductor devices without mask alignment misalignment.

[Brief explanation of the drawing]

Figures 1 (a) to (e) are cross-sectional views for explaining one embodiment of the alignment mark according to the present invention, and Figures 2 (a) to (d) illustrate conventional alignment marks. (a), (b), and (d) are all cross-sectional views, and (C) is a top view. 11...Semiconductor substrate. 12...active layer, l3...
- Source electrode, 14... Drain electrode, 15... Alignment mark, 16... Resist film. 17...
Electron beam, 18a, 18b - aperture, 18x, 18
y-opening, 19...metal film for gate electrode.

Claims (1)

[Claims] A step of forming an alignment mark for electron beam exposure on a semiconductor substrate, and after applying a resist film on the semiconductor substrate, irradiating the resist film in a region including the alignment mark for electron beam exposure with an electron beam. irradiating the resist film on the semiconductor substrate with an electron beam according to a predetermined pattern; performing a development process on the resist film to form an opening in the resist film; A method for manufacturing a semiconductor device, comprising the steps of etching away at least a portion of the alignment mark for electron beam exposure, and then etching away the semiconductor substrate to a predetermined depth through the opening.