JPH07240425A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately offset a gate electrode to a source electrode side in a recess, for reducing the resistance between a source electrode and a gate electrode, and manufacturing an FET of high performance with high yield. CONSTITUTION:An electron beam resist whose sensitivity is higher than an intermediate layer 15 and lower than a lower layer 14 is used as an upper layer 16. An electron beam resist whose sensitivity is lower than the upper layer 16 and the lower layer 14 is used as the intermediate layer 15. An electron beam resist whose sensitivity is higher than the upper layer 16 and the intermediate layer 15 is used as the lower layer 14. Exposure parts 24', 26', 25' of the respective layers are irradiated with electron beam 21 having the amount by which electron beam resists 24, 26, 25 can be selectively exposed to light. A recess structure 17 and a gate electrode 18 are formed by using the patterns of the upper layer 16, the intermediate layer 15, and the lower layers 14 which can be obtained by simultaneously developing the resists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode of a compound semiconductor field effect transistor.

[0002]

2. Description of the Related Art Source and drain electrodes are ohmic-connected to the surface of an active layer on a semi-insulating substrate, and the active layer between the source and drain electrodes is dug to have a film thickness that gives a predetermined gate characteristic. The breakdown voltage (drain breakdown voltage or gate breakdown voltage) can be improved and the source resistance can be reduced by forming a recess structure and further Schottky connection, that is, by offsetting the gate electrode toward the source electrode side in the recess. . By reducing the source resistance, a low noise FET having a noise figure NF of 0.5 at 12 GHz can be obtained.

FIGS. 4 to 5 show a conventional manufacturing method in which a gate electrode is formed by offsetting in such a recess structure.
Shown in.

4 to 5 show a conventional gate electrode forming process using a two-layer electron beam resist.

First, the source electrode 32 and the drain electrode 33 are formed on the surface of the active layer 31 on the semi-insulating substrate 30, a photoresist pattern 34 is formed by a photolithography process, and the active layer 31 is used as a mask.
Is removed from the surface by etching to form a recess 35 (FIG. 4A).

Next, after removing the photoresist 34,
A low-sensitivity lower layer electron beam resist 36 is newly applied, and a high-sensitivity upper layer electron beam resist 37 is applied thereon (FIG. 4B).

Next, the exposed portion 39 of the high-sensitivity upper electron beam resist 37 is exposed to an electron beam 38 with a small electron beam dose.
Then, the recess 35 is subjected to alignment exposure to form an exposure latent image. This dose corresponds to the high-sensitivity upper layer electron beam resist 37.
An exposure image can be formed on the low-layer electron beam resist 36 with low sensitivity, but an exposure latent image cannot be formed on the lower-layer electron beam resist 36 (FIG.
(C)).

Then, the exposure portion 40 of the low-sensitivity lower electron beam resist 36 located below the exposure portion 39 is aligned and exposed with an electron beam 38 having a large electron beam dose capable of forming an exposure latent image thereon. (FIG. 5 (A)).

Next, after development is performed to remove the exposed portions 39 and 40, aluminum is vapor-deposited on the entire surface and lift-off is performed using the upper layer electronic resist 37 and the lower layer electronic resist 36. The gate electrode 41 made of aluminum in the shape of the drain electrode 33
It is offset closer to the source electrode 32 side than the source electrode 32 side, and is formed by Schottky connection (FIG. 5B).

Next, another prior art manufacturing method of forming a gate electrode with a recess structure by offsetting it will be described with reference to FIGS.
Shown in.

6 to 7 show a conventional gate electrode forming process of an optical system, for example, Japanese Patent Laid-Open No. 63-169076.
It is disclosed in the publication.

First, a high-sensitivity photoresist (PR) 52 and a low-sensitivity photoresist (PR) 53 are sequentially formed on an active layer 51 having a source and drain electrodes (not shown) formed on a semi-insulating substrate 50. Then, a PR mask 54 having a bright portion 54 'and a dark portion 54''is placed thereon. Then, by vertically irradiating the UV light 55, the exposed portion 56 of the low-sensitivity photoresist (PR) 53, 52 located under the bright portion 54 'is exposed to form an exposed latent image (FIG. 6).
(A)).

Subsequently, UV light 55 is radiated from an oblique direction. As a result, a portion 57 of the high-sensitivity photoresist (PR) 52 in the lower layer is exposed laterally (to the right in the figure) in a lateral direction from below the bright portion 54 'of the PR mask 54, and an exposure latent image is formed there. It is formed. However, since the upper layer is the low-sensitivity photoresist (PR) 53, the bright portion 5
A portion 58 which is smaller in the lateral direction (rightward in the figure) than below 4'is exposed in an overhang shape and a slight exposure latent image is formed (FIG. 6 (B)).

Then, both photoresists (PR) 52, 5
3 is developed to obtain a photoresist pattern as shown in FIG.

Next, using the pattern portion of the photoresist 52 under the photoresist pattern as a mask, the active layer 51 is removed by isotropic etching from the surface to form a recess 59. Next, a metal 60 'for the gate electrode is deposited by vapor deposition to form a gate electrode 60 for Schottky connection at the bottom of the recess corresponding to under the bright portion 54'. Since the recess 59 is formed asymmetrically toward the drain electrode side from the position corresponding to the bright portion 54 'of the mask by the UV light irradiation from the oblique direction, the bright portion 54' of the mask is formed.
The gate electrode 60 located at the position corresponding to is offset to the source electrode side in the recess 59 (FIG. 7A).
Next, the photoresists (PR) 52 and 53 are peeled off, and lift-off is performed to remove the metal 60 'for the gate electrode on the photoresists 52 and 53 to obtain the structure shown in FIG. 7B.

[0016]

In the prior art using the EB exposure method shown in FIGS. 4 to 5, it is necessary to align the recess pattern formed in advance.
Since it is not possible to perform alignment with sufficient accuracy, there is a problem in that the amount of offset varies, which causes variations in FET characteristics.

Further, in the prior art shown in FIGS. 6 to 7, since the optical exposure method is used, the gate length cannot be reduced to 0.5 μm or less, and the FET performance cannot be improved. It was a problem.

An object of the present invention is to reduce the resistance between the source electrode and the gate electrode and to improve the withstand voltage.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of accurately offsetting a gate electrode having a short gate length to the source electrode side in a recess in order to manufacture T with a high yield.

[0019]

A feature of the present invention is that a lower layer electron beam resist and an intermediate layer electron beam having a lower sensitivity than the lower layer electron beam resist are formed on an active layer of a substrate on which source and drain electrodes are formed. Resist, a step of stacking an upper electron beam resist having a lower sensitivity than the lower electron beam resist and a higher sensitivity than the intermediate electron beam resist, and an exposure latent image is formed on the lower electron beam resist. A step of selectively irradiating an electron beam having an electron dose that does not form an exposure latent image on the line resist and the upper layer electron beam resist to form an exposure latent image at a first exposure position of the lower layer electron beam resist; And an exposure latent image is formed on the upper-layer electron beam resist, but an exposure latent image is not formed on the intermediate-layer electron beam resist. A step of forming an exposure latent image on the second exposed portion of the strike, and then selectively irradiating the intermediate layer electron beam resist with an electron beam having an electron dose for forming an exposure latent image on the intermediate layer. Forming an exposure latent image at a third exposure position of the electron beam resist, and developing the lower layer, upper layer and intermediate layer electron beam resists to form first and second exposure positions at the first, second and third exposure positions, respectively. A step of forming a resist pattern having second and third openings, and etching from the surface of the active layer through the first opening formed therein using the lower electron beam resist as a mask. Forming a recess in the layer, and connecting to the bottom surface of the recess in the second and third openings and under the third opening formed therein using the electron beam resist of the upper layer and the intermediate layer as a mask Game And forming an electrode, in a method of manufacturing a semiconductor device and a step of removing the resist pattern made of the lower layer, the upper layer and the intermediate layer electron beam resist. Here, it is preferable that the third exposed portion of the intermediate layer electron beam resist is located below the central portion of the second exposed portion of the upper layer electron beam resist. Further, the second exposure portion of the upper layer electron beam resist may be positioned so as to overlap the first exposure portion of the lower layer electron beam resist. The etching for forming the recess is preferably isotropic etching such as wet etching with a chemical solution. The lower layer, upper layer and intermediate layer electron beam resists are preferably resists having different molecular weights, for example, polymethylmethacrylate (PMMA).

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

As shown in FIG. 1A, semi-insulating GaA
The substrate 20 is configured to include the active layer (n-type channel layer) 11 on the s substrate 10. The active layer 11 includes, for example, a non-doped GaAs buffer layer deposited on the upper surface of the substrate 10, an n ⁺ GaAs operating layer deposited thereon, and an n ⁺⁺ GaAs contact layer deposited thereon. It consists of N is added to the contact layer on the surface of the active layer 11.
The source electrode 12 and the drain electrode 13 of i-AuGe-Au are formed by ohmic connection.

A lower layer electron beam resist 14, an intermediate layer electron beam resist 15 and an upper layer electron beam resist 16 are entirely provided.
Are respectively applied to form a laminate. Among these three layers of resist, the lower layer electron beam resist 14 has the highest sensitivity, the intermediate layer electron beam resist 15 has the lowest sensitivity, and the upper layer electron beam resist 16 has the sensitivity of the lower layer electron beam resist and the intermediate layer. It is a value between the sensitivity of the electron beam resist.

As these electron beam resists, PMMAs having different molecular weights (and thus different sensitivities) are used.
(Polymethylmethacrylate) (polymethy
l methacrylate).

For example, the lower layer electron beam resist 14 is coated with PMMA having a molecular weight of 240,000 to a film thickness of 100 nm, and the intermediate layer electron beam resist 15 is coated with PMMA having a molecular weight of 960,000 to a film thickness of 150 nm. 16 is formed by applying PMMA having a molecular weight of 500,000 to a film thickness of 800 nm.

After that, the upper layer electron beam resist, the intermediate layer electron beam resist and the lower layer electron beam resist are selectively exposed with electron beams having different electron doses in the EB apparatus.

First, as shown in FIG. 1 (B), E
In the apparatus B, the lower layer electron beam resist 14 having the highest sensitivity is selectively exposed at an exposure spot 24 by an electron beam (EB) 21 having a small electron dose to form an exposure latent image. The length L1 of the exposed portion 24 is 0.8 μm. At this time, since the upper layer electron beam resist 16 and the intermediate layer electron beam resist 15 have lower sensitivity than the lower layer electron beam resist 14, an exposure latent image is not formed by the electron dose in this step.

Next, as shown in FIG. 1C, an upper electron beam resist 16 having a lower sensitivity than the lower electron resist 14 and a higher sensitivity than the intermediate electron resist 15 in the EB apparatus.
1 is exposed by the electron beam 21 that is larger than the number of steps in FIG. 1 (B) where the lower layer electron beam resist 14 was exposed to form an exposure latent image. The length L2 of the exposed portion 26 is 0.4 μm. At this time, the intermediate layer electron beam resist 15
Has a lower sensitivity than the upper-layer electron beam resist 16, so that the exposure latent image is not formed by the electron dose in this step. Further, the exposed portion 26 of the upper layer electron beam resist 16 is superposed on the exposed portion 24 of the lower layer electron beam resist 14, and one end (the left end in the figure) of both exposed portions coincides.

Next, as shown in FIG. 2A, in the EB apparatus, the exposed portion 25 of the intermediate layer electron beam resist 15 having the lowest sensitivity is selectively exposed by the electron beam 21 having the highest electron dose. Then, an exposure latent image is formed there. The length L3 of the exposed portion 25 is 0.15 μm. Further, the exposed portion 25 of the intermediate layer electron beam resist 15 is formed by the upper layer electron beam resist 16
Of the upper layer electron beam resist 16 and the exposed portion 26 of the lower layer electron beam resist 14 and the central portion of the exposed portion 26 of the upper layer electron beam resist 16.

Next, as shown in FIG. 2B, an electron beam having openings 24 ', 25' and 26 'obtained by developing and removing the resist at the exposed portions 24, 25 and 26 is performed. A resist pattern is formed.

In each of the above-mentioned exposure steps, the exposed portion of the upper layer electron beam resist, the exposed portion of the intermediate layer electron beam resist,
± 0.04μ because the alignment of the backside of the exposed electron beam resist is not accompanied by mechanical movement of the stage.
It is possible to perform with a high accuracy of m.

Next, as shown in FIG. 2C, the active layer 11 is isotropically etched from the surface under the opening 24 'using the pattern portion of the electron beam resist 14 under the electron beam resist pattern as a mask. The recesses 17 are formed by etching away. The recess 17 has a depth of, for example, 20n.
m in, forming the bottom to the active layer 11 inside the n ⁺ GaAs operation layer through the n ⁺⁺ GaAs contact layer of the active layer 11 surface.

After that, aluminum metal 18 'for the gate electrode is deposited by vapor deposition to make a Schottky connection from the inside of the opening 25' of the intermediate layer electron beam resist 15 to the bottom of the recess 17 directly below it, and to form the upper layer. Electron beam resist 16
The gate electrode 18 is formed in the opening 26 '.

After that, electron beam resists 14, 15, 16 are used.
Then, the metal 18 'for the gate electrode is removed and lift-off is performed to obtain the structure shown in FIG. The gate electrode is Schottky connected to the bottom of the recess 17 of the active layer 11 by Schottky connection and has a narrow portion 18G that sets the gate length L3 that determines the gate characteristics and a wide portion (L2) that reduces the gate resistance. 18W.

In this way, the gate electrode 18 can be offset to the source electrode 12 side in the recess 17.

As a result, the variation in the offset amount in the recess of the gate electrode was ± 0.2 μm in the prior art, but is ± 0.04 μm by using the manufacturing method of the present invention.
Could be reduced to

Further, since the resist is exposed by the electron beam, the gate length L3 can be easily set to 0.15 μm, so that a high performance low noise FET can be manufactured with a high yield.

[0038]

As described above, in the method for manufacturing a semiconductor device of the present invention, an electron beam resist having a higher sensitivity than the intermediate layer and a lower sensitivity than the lower layer is used in the upper layer, and the intermediate layer has a lower sensitivity than the upper layer and the lower layer. The electron beam resist is used, and the electron beam resist having a higher sensitivity than the upper layer and the intermediate layer is used for the lower layer, and the exposed portion is selectively irradiated with an electron beam in an amount that sensitizes the electron beam resist of each layer. , The lower layer resist pattern is formed respectively, and the recess structure and the gate structure are formed using the same, so that the gate electrode can be accurately offset to the source electrode side in the recess,
Moreover, since the electron beam is used, for example, 0.15
A gate electrode having a short gate length of μm can be easily formed. Therefore, a high-performance low noise FET can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

2A to 2D are cross-sectional views sequentially showing a step following that of FIG.

FIG. 3 is a cross-sectional view showing a semiconductor device obtained by a process following that of FIG.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device in the related art in the order of steps.

5A to 5C are cross-sectional views sequentially showing a step following that of FIG.

FIG. 6 is a cross-sectional view showing another method of manufacturing a semiconductor device of the related art in the order of steps.

7A to 7C are cross-sectional views sequentially showing a step following that of FIG.

[Explanation of symbols]

 10, 30, 50 Semi-insulating substrate 11, 31, 51 Active layer 12, 32 Source electrode 13, 33 Drain electrode 14 Lower layer electron beam resist 15 Intermediate layer electron beam resist 16 Upper layer electron beam resist 17 Recess 18 Gate electrode 18 'Gate Electrode material 20 Substrate 21 Electron beam 24 Exposure part of lower layer electron beam resist 24 'Opening part of lower layer electron beam resist 25 Exposure part of intermediate layer electron beam resist 25' Opening part of intermediate layer electron beam resist 26 Exposure of upper layer electron beam resist Location 26 'Lower-layer electron beam resist opening 34 Photoresist pattern 35 Recess 36 Lower-layer electron beam resist 37 Upper-layer electron beam resist 39 Upper-layer electron beam resist exposure location 40 Lower-layer electron beam resist exposure location 41 Gate electrode 52 High-sensitivity photoresist (PR) 53 Low sensitivity photoresist (PR) 54 PR mask 54 'PR mask bright part 54' 'PR mask dark part 55 UV light 56 Exposure location 57 Large overhang exposure location 58 Small overhang exposure Location 59 Recess 60 Gate electrode 60 'Gate electrode material

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/41 29/417 7352-4M H01L 21/30 573 8932-4M 29/44 C 8932-4M 29/50 S

Claims (6)

[Claims] 1. A lower layer electron beam resist, an intermediate layer electron beam resist having lower sensitivity than the lower layer electron beam resist, on an active layer of a substrate on which source and drain electrodes are formed.
Stacking an upper electron beam resist having a lower sensitivity than the lower electron beam resist and a higher sensitivity than the intermediate electron beam resist; and an exposure latent image is formed on the lower electron beam resist, but the intermediate electron beam resist is formed. And a step of selectively irradiating an electron beam having an electron dose at which an exposure latent image is not formed on the upper layer electron beam resist to form an exposure latent image at a first exposure portion of the lower layer electron beam resist, Second exposure of the upper-layer electron beam resist by selectively irradiating an electron beam of an electron dose at which an exposure latent image is formed on the upper-layer electron beam resist but not on the intermediate-layer electron beam resist. A step of forming an exposure latent image on the spot, and then, by selectively irradiating the intermediate layer electron beam resist with an electron beam having an electron dose for forming the exposure latent image, Exposure of Step and said lower layer, said developing the upper and intermediate layer electron beam resist first, first, respectively second and third exposure portion forming the exposed latent image,
Forming a resist pattern having second and third openings, and etching from the surface of the active layer through the first opening formed therein using the lower electron beam resist as a mask. Forming a recess in the layer, and connecting to the bottom surface of the recess in the second and third openings formed under the upper layer and the intermediate layer electron beam resist as a mask and under the third opening. A method of manufacturing a semiconductor device, comprising: a step of forming a gate electrode; and a step of removing the resist pattern made of the electron beam resist of the lower layer, the upper layer and the intermediate layer. 2. The semiconductor device according to claim 1, wherein the third exposed portion of the intermediate layer electron beam resist is located below the central portion of the second exposed portion of the upper layer electron beam resist. Manufacturing method. 3. The second exposed portion of the upper layer electron beam resist is located so as to overlap with the first exposed portion of the lower layer electron beam resist. A method for manufacturing a semiconductor device as described above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the etching for forming the recess is isotropic etching. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the electron beam resists of the lower layer, the upper layer and the intermediate layer are resists having different molecular weights. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the lower layer, upper layer and intermediate layer electron beam resists are polymethylmethacrylate (PMMA).