WO2003067664A1 - Field-effect transistor and method for manufacturing it - Google Patents

Abstract

A field-effect transistor having a T-shaped gate electrode has an offset gate structure in which a parasitic capacitance created between the canopy of the T-shaped gate electrode and a semiconductor substrate is reduced. In this structure, the ohmic contact layer just below the bottom region of an insulating film formed in contact with both the source side and the drain side of the column portion of the T-shaped gate electrode is removed from the column portion to just below the canopy end portion of the T-shaped gate electrode. Moreover, the structure is an offset structure in which the drain side removed region is larger than the source side removed region. The removal of the ohmic contact layer is done by an anisotropic etching method. The structure of the field effect transistor having the T-shaped gate is applied to a strain-relaxed high-mobility field-effect transistor. This field effect transistor is used as an active element constituting an the MMIC.

Description

 Description Field effect transistor and method for manufacturing the same

 The present invention relates to a field-effect transistor having a T-shaped gate electrode and a method for manufacturing the same. Background art

 Since compound semiconductor field-effect transistors have high electron mobility as their characteristics, applications in the microwave and millimeter-wave bands are being promoted. For applications in higher frequency bands, shortening the gate length is effective, but this has the disadvantage that the cross-sectional area in the gate width direction becomes smaller and the gate resistance increases. As a countermeasure, τ-shaped gates, which can secure a cross-sectional area while keeping the gate length small, are widely used.

 In order to reduce the parasitic capacitance on the drain side of such a high electron mobility field effect transistor (hereinafter referred to as HEMT) having a T-shaped gut electrode structure, an electric field effect having an offset gate structure is used. A transistor and a method for manufacturing the transistor are disclosed in Japanese Patent Application Laid-Open No. 11-97454.

 The cross-sectional structure of this conventional HEMT is shown in FIG. In FIG. 15, the T-shaped gate electrode 21 has a parasitic capacitance C l, C 2 between the eaves portion of the gate electrode and the ohmic contact layer 16 as shown in FIG. appear. The source-side parasitic capacitance C2 causes a decrease in cutoff frequency and maximum oscillation frequency and an increase in noise, and the drain-side parasitic capacitance C1 causes a decrease in power gain. In addition, because of the insulating films (SiO film and SiON film) 18 and 19 having a high dielectric constant in contact with the eaves and the pillars of the T-shaped gate electrode 21, the parasitic capacitance becomes It becomes even higher, which causes a decrease in transistor performance.

In FIG. 15, reference numeral 11 denotes a semi-insulating GaAs substrate, and reference numeral 12 denotes an AND. GaAs buffer layer, 13 is undoped InGas channel layer, 14 is 11-type A 1 GaAs electron supply layer, 15 is undoped A 1 GaAs layer, 1 6! Type 1 0 & A s O over ohmic contact layer, 1 7 3丄0 ₂ film, 1 8 S i ON film, 1 9 3 i O film, 2 0 WS i gate electrode, 2 1 A u The plating layer, 22 is a drain electrode, 23 is a source electrode, 24 is a drain electrode side gap, and 25 is a source electrode side gap. This conventional method of manufacturing a field-effect transistor having an offset gate structure has a step of forming an insulating film on a resist and increases the number of steps due to a reduction in parasitic capacitance on the drain side.

 Usually, the method of forming an insulating film often involves a high temperature of 200 ° C. or more, and when the insulating film is formed on a resist, problems such as burning of the resist and dimensional change due to reduction occur. To prevent this, it is necessary to use a low-temperature process. However, since a low-temperature film is formed, the film quality of the insulating film such as etching resistance, heat resistance, and dielectric strength is inferior to that of a normal insulating film. This decrease in film quality causes a decrease in transistor reliability and yield.

 In addition, in the conventional manufacturing method having an offset gate structure effective for reducing the drain-side parasitic capacitance, the drain-side eaves portion of the T-shaped gate electrode that protrudes from the gap 24 and the insulating film 17 still remain. , 18 and the ohmic contact layer 16, and the ohmic contact layer via the source-side eaves portion of the gate electrode projecting from the gap 25 and the insulating film 19. No consideration was given to the reduction of the parasitic capacity that occurs between the two. In particular, the structure and manufacturing method cannot reduce the parasitic capacitance formed between the insulating film immediately below the source-side electrode and the limiter contact layer to the same extent as the drain-side.

 Therefore, an object of the present invention is to reduce the source-side parasitic capacitance of a field-effect transistor further using a simple process as compared with the conventional example, and at the same time, to increase the drain-side parasitic capacitance without increasing the number of steps. It is an object of the present invention to provide a field effect transistor capable of reducing the power consumption and a method for manufacturing the same.

Another object is to provide a high-frequency module using the field-effect transistor of the present invention. Disclosure of the invention

 An object of the present invention is to provide a semiconductor layer formed on a semiconductor substrate, a T-shaped gate electrode which is in contact with the semiconductor layer and has a pillar portion and an eaves portion, and a contact portion which is in contact with the pillar portion and the eaves portion of the gate electrode. An insulating film provided between the insulating film and the semiconductor substrate, and a gap formed in a portion of the gate electrode recessed from the pillar portion, and making contact with a source drain. A field-effect transistor having an limiter contact layer of

 At least a source-side ohmic contact layer immediately below the bottom region of the insulating film in contact with the pillar portion of the gate electrode has a void formed from the pillar portion of the gate electrode to just below the end of the eaves portion. This can be achieved by adopting a structure. In other words, by increasing the ratio of the gap portion on the insulating film between the eaves portion of the gate electrode and the semiconductor substrate, the gap portion on the source side as well as the drain electrode side as compared with the conventional structure, The parasitic capacitance formed between the eaves portion and the semiconductor substrate can be further reduced.

 Also, when partially removing the bottom region of the insulating film in contact with the pillar portion of the gate electrode, the width of the drain side is made larger than the source side, and the emitter contact layer is etched through the opening formed by the removal. This makes it possible to easily form the offset gate structure. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a sectional view of a strain-relaxed high-electron-mobility field-effect transistor (hereinafter, referred to as strain-relaxed HEMT) which is a first embodiment of the field-effect transistor according to the present invention. FIG. 2 is a cross-sectional view of a manufacturing process of the strain-mitigating HEMT shown in FIG.

FIG. 3 is a cross-sectional view of the strain relief HEMT showing the next manufacturing process shown in FIG. FIG. 4 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing process shown in FIG. FIG. 5 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing process shown in FIG. FIG. 6 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing process shown in FIG. FIG. 7 is a cross-sectional view of the strain relief HEMT showing the next manufacturing process shown in FIG. FIG. 8 shows a strain relief HE according to a second embodiment of the field effect transistor according to the present invention.

It is sectional drawing of MT.

 FIG. 9 is a cross-sectional view of the manufacturing process of the strain-mitigating HEMT shown in FIG.

 FIG. 10 is a cross-sectional view of the strain relief HEM showing the next manufacturing process shown in FIG. FIG. 11 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing process shown in FIG. FIG. 12 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing process shown in FIG. FIG. 13 is a cross-sectional view of the strain-mitigating HEMT showing the next manufacturing step shown in FIG. FIG. 14 shows a strain relief H according to a third embodiment of the field effect transistor according to the present invention.

It is sectional drawing of EM.T.

 FIG. 15 is a cross-sectional view showing a conventional HEMT.

 FIG. 16 is a cross-sectional view of a monolithic microwave integrated circuit using the strain relaxation HEMT according to the present invention.

 FIG. 17 is a block diagram of a basic circuit of a high-frequency module equipped with the monolithic microwave integrated circuit shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

 <Example 1>

FIG. 1 shows a sectional structure diagram of a strain relaxation HEMT which is a first embodiment of the field effect transistor according to the present invention. Bottom region of the high dielectric constant insulating film 44 in contact with the eaves part and the bar portion of the T-shaped gate electrode 52, both the source side and drain side, Ii one _{I η 0. 5 G a 0.} 5 A s The cap layer 41 has a structure having a source-side gap 51S and a drain-side gap 51D, which are removed by protruding from the end of the eaves portion of the gate electrode. The parasitic capacitance formed between the portion and the semiconductor substrate 31 can be further reduced as compared with the conventional example.

Next, a method of manufacturing the strain-mitigating HEMT of this embodiment will be described in the order of steps with reference to FIGS. As shown in FIG. 2, an undoped GaAs buffer layer 32 with a thickness of 28 nm, an undoped A1 3 buffer layer 33 with a thickness of 20 nm, a thickness of 600 nm undoped I n a 1 a s step graded layer 34.. (I n a s molar ratio varies from 0.1 5 to 0.45), undoped I n ₀ thickness _{200 nm 5 a 1 o 5 a} s Paglia layer 35, an undoped I n ₀ thickness _{20 nm. 5 G a 0.} 5 a s Chiyane Le layers 3 6, thickness 2 nm of undoped I n. ₅ A1. . ₅ A s layer 3 7, the thickness 1 2 nm S i doped n-I n. . ₅ A l. ₅ A s Kiyaria supply layer ^{38 (5 X l 0 18 cm-} 3), undoped thickness _{1 0 nm;.. Ln 0} 5 A 1 0 5 3 layers 3 9, a thickness of 7 nm and one-flop I n P layer 40, the third thickness 4,011,111 i doped _{n- I n 0. 5 G a} . , A _{5 As} cap layer 41 (5 × 10 ¹⁹ cm ⁻³ ) is formed sequentially by epitaxy. Next, a PSG film 42 is deposited on the entire surface by a thermal CVD (Chemical Vapor Deposition) method to a thickness of 50 nm, and a resist pattern 43 having a width of 0.55 is formed on the PSG film 42 using an optical exposure apparatus.

As shown in FIG. 3, using the resist pattern as a mask, the PSG film 42 is anisotropically dry-etched to form a recess etching dummy pattern 42a. Next, after removing the resist pattern 43, a 60 nm thick Si ₃ N ₄ film 44 is formed on the entire surface by ECR (Electron Cyclotron Resonance) sputtering.

Next, as shown in FIG. 4, a resist opening pattern 45 having an opening size of 0.15 μm was formed using an EB (Electron Beam) lithography apparatus to form a source-side end S on the recess etching dummy pattern 42a. the position of 0. 2 mu m from the _E, the end P _E of the opening pattern 45 is formed so as to be located.

Next, the Si ₃ N ₄ film 44 is anisotropically dry-etched through the resist opening pattern 45 to form a 0.15 im Si ₃ N ₄ film opening pattern 46. At this time, the recess etching dummy pattern 42 a may or may not be etched together with the Si ₃ N ₄ film 44. The figure shows a case where etching is performed.

Next, as shown in Fig. 5, a 400-nm thick PSG film 47 is deposited on the entire surface by thermal CVD, and then the source / drain electrode forming resist opening pattern is formed using an optical exposure system. Forming a over emissions, a PSG film 47 is etched through the resist pattern, exposing the _{n- I n 0. 5 G ao} , 5 A s cap layer 41. Next, an electrode metal made of An and Mo (molybdenum) is deposited by EB deposition, and a source electrode 48 and a drain electrode 49 are formed by lift-off.

Next, as shown in FIG. 6, a resist opening pattern 50 is formed on the Si ₃ N ₄ film opening pattern 46 using an optical exposure apparatus, and the PSG film is passed through the resist opening pattern 50 using a hydrofluoric acid aqueous solution. performs isotropic © Etsu preparative etching 47 to expose the _{n_ I n 0. 5 G a} 0. 5 a s cap layer 41. At this time, the recess etching dummy pattern 42a is also etched at the same time to form the recess etching opening pattern 51. The Si ₃ N ₄ film 44 has an extremely small etching rate with respect to the hydrofluoric acid aqueous solution as compared with the PSG film 42, and the isotropic nature of the PSG film 42 ゥ The size of the Si ₃ N ₄ film opening pattern 46 even after the etching. Remains almost at 0.15 m.

Next, as shown in FIG. 7, through S i ₃ N ₄ film aperture pattern 46, the _{n- I n 0. 5 G a} 0. 5 A s capping layer 41 using an aqueous solution of Kuen acid and hydrogen peroxide Isotropic wet etching. At this time, the etchant enters through the Si ₃ N ₄ film opening pattern 46 and flows equally into the recess etching opening pattern 51 to form the opening 51a. Thus, n-I n ₀ after etching. ₅ recess etching width G a 0. ₅ A s cap layer 41, from both ends of the dummy pattern 42 a for the width and the recess etching of the dummy pattern 4 2 a for recess etching N−In ₀ , ₅ G a 0.5 As a sum with the side etching width of the As layer 41 of the cap layer.

 For example, if the side etching width is 0.1 m, the recess etching width on the source side is 0.2 μηι and the recess etching width on the drain side is 0.4 / zm in this embodiment, which is a so-called offset gate structure. Become.

Here, by adjusting the width of the recess etching dummy pattern 42a and the formation position of the Si ₃ N ₄ film opening pattern 46 on the recess etching dummy pattern 42a, the recess etching on the source side and the drain side is performed. The width can be set freely. For example, the drain side from the center of the recess etching dummy pattern 42a S i ₃ N ₄ placing the film aperture pattern 46 and, in order to divided only part insulating film on the source side, also possible to place the S i ₃ N ₄ film aperture pattern 46 on the drain side end in It is.

Finally, an electrode metal consisting of Au, Pt (platinum), and Ti (titanium) is deposited by EB evaporation, and a gate electrode 52 is formed by a lift-off method. The source electrode side gap 51 S and the drain electrode side gap 51 D may be formed below the Si ₃ N ₄ film 44 in contact with the eaves so as to protrude beyond the end of the eaves of the gate electrode. I understand. The strain relief HEMT with the structure shown in Fig. 1 is completed. In this way, the offset structure of the T-shaped gate electrode, the ratio of the eaves of the T-shaped gate electrode on the drain side and the source electrode side, and the ratio of the void portion to the insulating film between the semiconductor substrate and the conventional structure are compared. As a result, the parasitic capacitance formed between the eaves portion of the gate electrode and the semiconductor substrate decreases. Therefore, at least 150 & ₂ current gain cut-off frequency f _T, the maximum oscillation frequency £ ₁₁₁ can realize a field effect transistor having a high-frequency characteristics such as at least 200 GH z.

 In the present embodiment, the InAlAsZlnGasAs strain relaxation HEMT on the GaAs substrate has been described, but the InA1AsZInGaAsHEMT on the InP substrate, It is also applicable to AI GaAs / InGaAs strained channel HEMTs on GaAs substrates and other field effect transistors such as MES FETs and JFETs. <Example 2>

 FIG. 8 shows a sectional structure view of a strain relaxation HEMT which is a second embodiment of the field effect transistor according to the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

 The feature of this embodiment is that the source-side gap 51S and the drain-side gap 51D formed in the bottom region of the insulating film in contact with the eaves portion and the pillar portion of the T-shaped gate electrode have the same width and thickness. It is. As in Fig. 1, the voids 51S and 51D are of course formed up to the region protruding from the eaves of the T-shaped gate electrode.

This structure can be realized by positioning the Si ₃ N ₄ film opening pattern 46 at the center on the recess etching dummy pattern 42a. For example, when used as a switching element in a digital circuit such as an SRAM (Static Random Access Memory), the parasitic capacitance C 1, C on the drain side and the source side because the potentials on the source and drain sides are frequently inverted. 2 affects performance at an equal rate. However, in the strain relaxation HEMT of the present embodiment, the parasitic capacitance formed between the eaves portion of the T-shaped gate electrode and the semiconductor substrate can be reduced equally at the drain side and the source side at the same time. Regardless, high performance is possible.

<Example 3>

 Third Embodiment A third embodiment of a field-effect transistor according to the present invention, which is a strain relief HEMT and a method of manufacturing the same, will be described with reference to FIGS. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, 3 i-doped n-In with a thickness of 40 11111 from an undoped GaAs buffer layer 32 having a thickness of 28 nm on a GaAs substrate 31 similarly to the first embodiment. , Formed by ₅ G a 0. ₅ A s cap layer ^{41 (5 X 10 19 c m_} 3) the layers to sequentially Epitakishi catcher Le deposition. Further, a PSG film 42 is deposited on the entire surface by a thermal CVD method to a thickness of 50 nm, and a Si ₃ N ₄ film 44 is formed on the entire surface by an ECR sputtering method to a thickness of 60 nm. An m resist opening pattern 45 is formed.

Next, as shown in FIG. 10, the Si ₃ N ₄ film 44 is anisotropically dry-etched through the resist opening pattern 45 to form a 0.15 μηι wide Si ₃ N ₄ film opening pattern.

Form 46. At this time, ? The 30 film 42 may or may not be etched with the Si ₃ N ₄ film 44. In the same figure, the case where etching is performed is shown. Next, a 400 nm PSG film 47 is deposited on the entire surface by thermal CVD. Next, as shown in FIG. 11, a resist pattern for forming source / drain electrodes is formed using an optical exposure apparatus, and the PSG film 47 and the PSG film 47 are formed through the resist pattern.

The 5 i ₃ N ₄ film 44 is etched to leave exposed the _{n- I n 0. 5 G a} 0. 5 A s cap layer 41. Next, an electrode metal made of Au and Mo is deposited by EB deposition, and a source electrode 48 and a drain electrode 49 are formed by lift-off. Next, as shown in FIG. 12, using an optical exposure apparatus, a resist opening pattern 50 is formed on the Si ₃ N ₄ film opening pattern 46, and a hydrofluoric acid aqueous solution is passed through the resist opening pattern 50. rows that have isotropic © Etsu preparative etching the PSG film 47 Te, exposing the _{n- I n 0. 5 Ga 0} . 5 as cap layer 41. At this time, the PSG film 42 is simultaneously etched. The etching time is set so that the side etching width of the PSG film 42 is 0.1 μπι.

Next, as shown in FIG. 13, through the Si ₃ N ₄ film opening pattern 46, n-In using an aqueous solution of citric acid and hydrogen peroxide. . ₅ G a. . Isotropically wet etched ₅ A s cap layer 41. The recess etching width at this time is 0.2 μπι on both the source side and the drain side when the side etching amount is 0.1 m, for example.

 Finally, an electrode metal consisting of Au, Pt, and Ti is deposited by EB deposition, and the gut electrode 52 is formed by lift-off, thereby completing the strain-mitigating HEMT.

Similarly to the first embodiment, the strain relief HEMT of the present embodiment also has a T-shaped gate electrode having an offset structure, and has a source electrode side gap below the Si ₃ N ₄ film 44 in contact with the eaves portion of the gate electrode. A field effect transistor having the same high-frequency characteristics as the first embodiment because 51 S and a gap 51 D on the drain electrode side are formed from the pillar portion of the gate electrode to a position protruding from the eaves end portion, thereby reducing parasitic capacitance. Can be realized.

In this embodiment, it is difficult to control the side etching width of the P SG film 42, compared with Example 1, finally _{n- I n 0. 5 G a 0.} 5 control recess etching width A s cap layer 41 Although it is inferior in reproducibility and reproducibility, there is an advantage that the cost can be reduced because the lithography process for forming the dummy pattern 42a for recess etching and the etching process can be omitted.

<Example 4>

 FIG. 14 shows a sectional structure view of a strain-mitigating HEMT which is a fourth embodiment of the field-effect transistor according to the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is characterized in that the recess etching width of the ohmic contact layer is That is, it is formed to have the same width as the etching dummy pattern 42a.

This structure, in etching the _{S i 3 N 4 n- I n} 0 through film aperture pattern _{4 6. 5 G a 0.} 5 A s capping layer 4 1, side direction Etsuchin grayed the depth direction Can be realized by performing etching using an anisotropic liquid etchant that is as small as a fraction. As the anisotropic wet etching solution, for example, an aqueous solution of citric acid and hydrogen peroxide cooled to 10 ° C. or less may be used.

The etchant that has penetrated through the Si ₃ N ₄ film opening pattern 46 flows equally into the recess etching opening pattern 51 formed by etching and removing the recess etching dummy pattern 42 a, and the recess etching dummy pattern. N—I n equal to the width of the pattern 4 2 a. . ₅ G a. . Anisotropically etching only ₅ A s capping layer 4 1 part. As in FIG. 1, the voids 51S and 5ID are of course formed up to the region that extends beyond the eaves of the T-shaped gate electrode.

 It is very difficult to control the side etching width during isotropic etching, and variations in the side etching width result in variations in transistor performance. However, in this embodiment, since recess etching is performed by anisotropic etching, it is possible to ignore performance variations due to variations in the side etching width.

 Also, when isotropic etching is performed, the width of the recess etching dummy pattern 42a must be larger than the final recess etching width because the recess etching width must be determined in consideration of the side etching width. Need to be smaller. Therefore, the effect of reducing the capacity is reduced. However, in the present embodiment, since the recess etching width and the width of the recess etching dummy pattern 42a can be made equal, the capacity reduction effect can be maximized.

 The manufacturing method of the present embodiment is also applicable to the case where the recess etching opening pattern 51 is formed by using the side etching of the insulating film as described in the third embodiment.

Example 5>

FIG. 16 shows a microstrip-type monolithic microwave integrated circuit (MM IC: mounting a field-effect transistor according to the fifth embodiment of the present invention). 1 shows a cross-sectional view of Monolithic Microwave Integrated Circuit 100.

 As shown in FIG. 16, the surface of the GaAs semiconductor substrate 101 has a strain relaxation H E MT

102, resistance 104 are formed, and capacitance (including the conductor 105 of the transmission line as an electrode) 106 via the interlayer insulating film 103, inductance 107, transmission line Various microwave circuit elements such as the conductor 105 are formed. In addition, a via hole 108 and a ground conductor 109 are provided on the back surface of the GaAs semiconductor substrate 101, and a conductor 105 on the front surface of the substrate and a ground conductor 109 on the back surface have a resistor 104. Are connected via a suitable impedance.

 Here, the strain relaxation HEMT having the T-shaped gate electrode structure shown in the first embodiment is used as the strain relaxation HEMT 102.

 According to the present embodiment, since the high-performance strain relaxation HEMT is used as an active element, a high-performance MMIC can be realized.

 <Example 6>

 FIG. 17 shows a configuration diagram of an on-vehicle radar according to a sixth embodiment of the present invention. The automotive radar is a high-frequency module 2 consisting of a voltage variable oscillator 201, an amplifier 202, a receiver 203, a receiving antenna terminal 207, a transmitting antenna terminal 208, and a terminal 209. 0 0, the receiving antenna 210 connected to the receiving antenna terminal 207, the transmitting antenna 211 connected to the transmitting antenna terminal 208, and the signal processing system 2 connected to the terminal 209 It is composed of one and two. Here, the voltage variable oscillator 201, the amplifier 202, and the receiver 203 are configured by the MMIC described in the fifth embodiment.

 Hereinafter, the operation of the vehicle radar will be described. The 76 GHz signal S 1 from the voltage variable oscillator 201 is amplified by the amplifier 202 and radiated from the transmission antenna 211 via the transmission antenna terminal 208. The signal S 2 reflected back from the object is received by the receiving antenna 210 and amplified from the receiving antenna terminal 207 by the amplifier 205 in the receiver 203.

Further, the amplified signal is combined with the reference signal S 1 of 76 GHz from the variable voltage oscillator 201 amplified by the amplifier 204 in the receiver 203 and the mixer in the receiver 203. The signals are mixed in the sub-unit 206 to form an intermediate frequency (IF intermediate Frequency) signal. The IF signal is taken out from the terminal 209 and input to the signal processing system 212, where the relative speed, distance, and angle of the object are calculated.

 The high-frequency module of the present embodiment has high performance because it uses the MMIC of the fifth embodiment. Therefore, a high-performance in-vehicle radar can be realized. Industrial applicability

 As described above, as is apparent from the above-described embodiment, according to the present invention, the hole just below the bottom region of the insulating film provided in contact with both the source side and the drain side of the pillar portion of the T-shaped gate electrode. A field-effect transistor with a reduced parasitic capacitance on both the source and drain sides by adopting a configuration in which the mic contact layer is partially removed to the position protruding from the eaves end of the T-shaped gate electrode Can be.

 Further, by adjusting the ratio and width of the source and drain sides of the bottom region to be removed, a field-effect transistor can be obtained in which parasitic capacitance, parasitic resistance, breakdown voltage, and the like are freely set.

 In addition, by performing anisotropic etching of the ohmic contact layer, it is possible to prevent performance variations due to variations in side etching width, and at the same time, to manufacture a field effect transistor capable of maximizing the capacity reduction effect. A method can be provided.

Claims

The scope of the claims

1. A semiconductor layer formed on a semiconductor substrate, a T-shaped gate electrode in contact with the semiconductor layer and including a pillar portion and an eaves portion, and provided in contact with the pillar portion and the eaves portion of the gate electrode. An insulating film formed between the insulating film and the semiconductor substrate, and a gap formed in a portion of the gate electrode recessed from the pillar portion, and a contact between the source and the drain. A field effect transistor having a

 At least a source-side emitter contact layer immediately below the bottom region of the insulating film that is in contact with the pillar portion of the good electrode has a void that is removed from the pillar portion of the gate electrode to immediately below the end of the eaves portion. A field effect transistor characterized by the above-mentioned.

2. The field-effect transistor according to claim 1, wherein the drain-side ohmic contact layer immediately below a bottom region of the insulating film in contact with a pillar portion of the gate electrode is formed from the pillar portion of the gate electrode. A field-effect transistor further comprising a void that is removed to just below the end of the eaves portion.

 3. The field effect transistor according to claim 2, wherein the width and thickness of the voids of the removed ohmic contact layer are equal on the source side and the drain side. Effect transistor.

 4. The field-effect transistor according to any one of claims 1 to 3, wherein the semiconductor substrate is a compound semiconductor substrate, and the semiconductor layer includes a plurality of compound semiconductor layers including a strain relaxation layer. A field-effect transistor, comprising a strain-relaxed high-electron-mobility field-effect transistor.

5. The field effect transistor according to claim 4, wherein the semiconductor substrate is a semi-insulating GaAs substrate, and the laminated film is an AND GaAs buffer from the GaAs substrate side. layer, an undoped A 1 A s buffer layer, an undoped Ι ηΑ Ι Α s step graded layer, an undoped _{I n 0. 5 A 10. 5} A s Paglia layer, and-loop ^{I n o. 5 ° "a} 0. Rayanenore layerヽ'Notofu _{I n 0 5 A 1 0 5} A s layer 1 doped n-type _{I n 0. 5 A 1 o} . 5 A s carrier supply layer, an undoped _{I n 0. 5 A 1 0} . 5 A s layer, an undoped I n P layer, S i doped n-type _{I n 0. 5 G a 0} . 5 A s field effect transistor, which is a cap layer or Ranaru laminated film.

 6. A microstrip type monolithic microwave integrated circuit having at least a field effect transistor, a capacitance, an inductance, and a transmission line mounted on a semiconductor substrate, wherein the field effect transistor is any one of claims 1 to 5. A monolithic microwave integrated circuit, characterized by using the field-effect transistor described in (1).

 7. A voltage variable oscillator, a transmission antenna terminal, an amplifier connected between the voltage variable oscillator and the transmission antenna terminal, a reception antenna terminal, and a connection between the voltage variable oscillator and the reception antenna terminal. 5. A high-frequency module having a receiver and a terminal for an intermediate frequency signal of a mixer of the receiver, wherein the voltage variable oscillator, the amplifier, and the receiver are connected to each other according to claim 4. A high-frequency module comprising an integrated circuit.

 8. forming a semiconductor layer on the semiconductor substrate;

 Forming a first insulating film on the semiconductor layer;

 Forming a resist pattern on the first insulating film;

 Performing anisotropic etching on the first insulating film using the resist pattern as a mask to form a first insulating film pattern;

 Forming a second insulating film on the semiconductor substrate and the first insulating film pattern;

 The second insulating film portion formed on the first insulating film pattern is arranged to be shifted by a predetermined amount from the source side end of the first insulating film pattern to the drain side, and has a dimension larger than the width of the first insulating film. Forming a first resist opening pattern having a small size, and forming a second insulating film opening pattern by anisotropically etching the second insulating film using the first resist opening pattern as a mask.

 Isotropically etching the first insulating film pattern through the second insulating film opening pattern;

Using the second insulating film opening pattern and the first insulating film pattern as masks, Removing a part of the conductor layer by etching;

 Forming a T-shaped gate electrode on the surface of the semiconductor substrate exposed at the opening of the semiconductor layer removed by the etching;

A method for manufacturing a field-effect transistor, comprising:

9. forming a semiconductor layer on the semiconductor substrate;

 Forming a first insulating film on the semiconductor layer;

 Forming a second insulating film on the first insulating film;

 Forming a resist opening pattern on the second insulating film;

 Forming a second insulating film opening pattern by anisotropically etching the second insulating film using the resist opening pattern as a mask;

 Forming a first insulating film opening pattern by isotropically etching a part of the first insulating film through the second insulating film opening pattern;

 Removing a portion of the semiconductor layer by etching through the second insulating film opening pattern and the first insulating film opening pattern;

 Forming a T-shaped gate electrode on the surface of the semiconductor substrate exposed at the opening of the semiconductor layer removed by the etching;

A method for manufacturing a field-effect transistor, comprising:

 10. The method for manufacturing a semiconductor device according to claim 8, wherein an anisotropic etching is used for etching a part of the semiconductor layer. A method for manufacturing a transistor.

 11. The method for manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the semiconductor substrate is a compound semiconductor substrate, and the semiconductor layer is a plurality of compound semiconductors including a strain relaxation layer. A method for manufacturing a field-effect transistor, which is a laminated film of layers.

12. The method for manufacturing a field-effect transistor according to claim 11, wherein the semiconductor substrate is a semi-insulating GaAs substrate, and the laminated film is undoped from the GaAs substrate side. a A s buffer layer, an undoped A 1 A s buffer layer, and-loop I n A 1 A s step graded layer, an undoped I n _{0. S} A 1. _{5 As} Rear layer, an undoped _{I n 0. 5 G a o} . 5 As channel layer, an undoped _{I n 0. 5 A 1 0} . 5 As layers, S i doped n-type _{I n 0. 5 A Γ 0} . 5 A s carrier supply layer, an undoped _{I n 0. 5 a 1 0} . 5 a s layer, the undoped I nP layer, the S i doped n-type I n _0. a ₅ G a _{0. 5} a s a laminated film made of the cap layer A method for manufacturing a field-effect transistor.