JPH03167822A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform high-precision mark detection by short-time exposure by lapping a thin-film selectively on a region including a positioning mark on a semiconductor substrate, applying a resist mask and making an opening in the thin-film, and using the thin-film for lift-off. CONSTITUTION:Electrodes 13, 14 are made on an active layer 12 put on a GaAs substrate 11, and an Au positioning mark 15 is made on the substrate 11. The SiO2 thin-film 10 in the region other than the mark is removed by wet-etching using a resist mask 26. The mark is covered with resist 16 and detected by the scanning of an electronic beam. And the resist 16 is exposed in accordance with a gate electrode pattern by irradiating between electrode 13, 14. Opening 18a, 18b are made after the development. The active layer 12 is etched through an opening 18a after an opening is made in the thin-film 10 selectively through the opening 18b with an NH4F aqueous solution. An FET is completed by covering with metallic films 19 for gate electrodes and lifting off the metallic films 19 put on the resist 16. This constitution makes it possible to perform stable lift-off even by electronic beam exposure, and stable high-precision mark detection.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device. (Prior Art) The minimum processing dimensions required in the manufacturing process of semiconductor devices have become significantly finer. In particular, the gate electrode dimensions of microwave semiconductor devices using compound semiconductors such as gallium arsenide (GaAs) have already reached 0. 25. The following has been achieved. Electron beam exposure technology using an electron beam is widely used as a method for processing such fine patterns. In order to form a pattern on a semiconductor substrate by electron beam exposure, it is necessary to accurately align the existing pattern and the electron beam. For this purpose, alignment marks for electron beam exposure (hereinafter referred to as alignment marks) having a cross-shaped or L-shaped planar shape are formed on the semiconductor substrate, and the alignment marks are scanned with an electron beam and marked. After detection, the positional relationship between the existing pattern and the electron beam is determined, and correction is applied to achieve highly accurate positioning. Generally, a metal film with a high signal-to-noise ratio (S/N ratio) of a detection signal is often used for this alignment mark.

FIG. 2 shows a process diagram for forming a gate electrode pattern of a Schottky barrier field effect transistor (MESFET) using GaAs by electron beam exposure. As shown in FIG. 2(a), a semi-insulating GaAs substrate 1
An active layer 102 is stacked on 01, and a source electrode 103, a drain electrode 104, and a semi-insulating GaA layer are stacked on the active layer 102.
Alignment marks 105 made of gold (Au) are formed on the S substrate 1, and after applying a positive type resist film 106 to the entire surface, the area including the alignment marks 105 is scanned with an electron beam 107. Perform mark detection,
An electron beam 7 is irradiated between the source electrode 103 and the drain electrode 104 to expose the resist film 106 according to the shape of the gate electrode pattern. Next, when the resist film 106 is developed, openings 108a, 1 as shown in FIG.
08b is formed. FIG. 2(c) is a top view showing the state of FIG. 2(b).

Openings 108x and 108y are formed in the L-shaped alignment mark 105 by detecting the mark in the X direction and the Y direction. For example, considering the exposure time per wafer and highly accurate and stable mark detection, the conditions for electron beam exposure are as follows: beam current = 0.2 nA, beam shot time during mark detection = 10 μsec, beam interval = 0.
1 μm, and the number of beam scans = 10 times, the amount of electrons (dose amount) irradiated to the resist film on the alignment mark is ((beam current/beam shot time)/beam interval)
- Number of scans = 2nC/an. This value is approximately the same as the optimum dose of an electron beam resist such as PHMA (polymethyl methacrylate), and the thickness of the resist film 106 on the alignment mark 105 is thicker than on other parts. The resist film 10 on the alignment mark 105 after development is thinner by the film thickness of .
6 will be removed. Note that FIG. 2(b) is a sectional view taken along the dashed line AA in FIG. 2(c).

Subsequently, as shown in FIG. 2(d), the active layer 102 is recess-etched to a predetermined depth through the opening 108, and a gate electrode metal film 109 is deposited. The purpose of the recess etching is to control the saturated drain current of the MESFET, to reduce the source resistance, and to form a spacer layer for lift-off when forming the gate electrode. In FIG. 2(d), since the alignment mark 5 is not attacked by the GaAs etchant during recess etching, the gate electrode metal film 1
After depositing the metal film 109 on the resist film 6,
The metal film 109 on the alignment mark 105 is connected to the metal film 1 on the resist film 106 due to lift-off.
There was a problem in that it became impossible to remove 09, making it difficult to shape the gate electrode of the MESFET.

As a method to solve the above problem, the resist film 105 on the alignment mark 105 is changed by changing the mark detection conditions such as beam current, beam shot time, beam interval, and number of scans.
Although it is possible to consider a method of suppressing the dose of resist film 106 below the optimum dose of resist film 106 so as to prevent the alignment mark 105 from being exposed after development, the following problems occur in throughput, mark detection, etc.

(1) The time required for electron beam exposure is approximately proportional to the beam current. Therefore, reducing the beam current is
6(2) The method of shortening the beam shot time causes a corresponding increase in the time required for exposure and a decrease in throughput. However, the signal strength to be detected becomes weaker, the S/N ratio decreases, and stable mark detection becomes difficult.

(3) The method of widening the beam spacing reduces the positional accuracy of mark detection, which increases the pattern overlay error.

(4) In the method of reducing the number of scans, the number of data required for averaging processing of mark detection signals is reduced, resulting in a decrease in pattern overlay accuracy.

Therefore, in order to perform highly accurate and stable mark detection without increasing the exposure time per wafer, it is necessary to irradiate the resist film on the alignment mark with the same amount of electron beam as the electrode pattern area. There is. Furthermore, when using a resist film with higher sensitivity than the above-mentioned PMMA as the resist film, the resist film on the alignment mark 105 is irradiated with an electron beam that is larger than the optimum dose, so that the position after development processing is It is inevitable that alignment mark 5 will be exposed. (Problems to be Solved by the Invention) As described above, with conventional alignment marks, when trying to perform highly accurate and stable mark detection without increasing the exposure time per wafer, it is difficult to Because the alignment marks are exposed by electron beam irradiation, it is extremely difficult to form electrode patterns using the lift-off method.

The present invention eliminates the above-mentioned drawbacks and provides a semiconductor device that can perform highly accurate and stable mark detection without increasing the exposure time per wafer when forming an electrode pattern using the lift-off method. The purpose is to provide a manufacturing method. [Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the method for manufacturing a semiconductor device according to the present invention, a thin film is selectively laminated in a region including alignment marks on a semiconductor substrate. , the area including the alignment mark is scanned with an electron beam. (Function) In the method for manufacturing a semiconductor device according to the present invention, a thin film is selectively laminated on a region including alignment marks on a semiconductor substrate, and after resist coating, electron beam exposure, and development processing are performed. Since the thin film is etched away through the openings in the resist film and this thin film is used as a spacer layer for lift-off, stable lift-off is possible even with electron beam exposure.

(Example) An example of the present invention will be described with reference to the drawings. As shown in Figure 1(a), a semi-insulating GaAs substrate ll
An active layer 12 is laminated thereon, and a source electrode l3 and a drain electrode l4 are formed on the active layer 12, and alignment marks 15 made of a metal film such as gold (Au) are formed on the semi-insulating GaAs substrate 11, respectively. ．． Subsequently, a thin film such as a silicon oxide film of 0.5 IR and a resist film 26 are sequentially laminated on the entire surface, patterning is applied to the resist film 26, and a thin film 10 is formed in the region including the alignment mark 15 as shown in FIG.
Form selectively as in b). Here, the reason why the thin film other than the region including the alignment mark 15 is removed is to shorten the width of the recess formed at the same time as the gate electrode, thereby suppressing an increase in source resistance. For example, if there is a thin film on the active layer in the area where the gate electrode is formed, it is necessary to remove the thin film before performing recess etching, and if dry etching is used to remove this thin film, damage to the active layer may occur. Because of this concern, wet etching is usually performed. In wet etching, etching progresses not only in the depth direction but also in the lateral direction, so the recess width with the thin film becomes wider than in the case without the thin film, resulting in an increase in source resistance. Next, after removing the resist film 26, as shown in FIG.
After applying a new resist film l6 to the entire surface as shown in FIG. Irradiated resist film l6
is exposed according to the gate electrode pattern shape. Next, when the resist film 16 is developed, openings 18a and 18b as shown in FIG. 1(d) are formed in the portions of the resist film 16 irradiated with the electron beam 17. Next, Figure 1(e)
After the thin film 10 is etched away through the opening 18b using, for example, an aqueous ammonium fluoride solution, the active layer 12 is recess-etched to a predetermined depth through the opening 18a, as shown in FIG. Here, since the active layer 12 made of GaAs is not etched by the ammonium fluoride aqueous solution, only the thin film 1O is selectively etched. Furthermore, as shown in FIG. 1(f), after depositing the gate electrode metal film 19, the gate electrode metal film 19 on the resist film l6 is
Figure 1 (g) is obtained by removing the
A MESFET shown in is formed. In FIG. 1(f), on the alignment mark l5 is a gate electrode metal film l9.
However, the thin film 10 becomes a spacer layer for lift-off, and the gate electrode metal film 19 on the alignment mark 15 and the gate electrode metal film 19 on the resist film l6 are separated. As shown in FIG. 1(g), lift-off of the metal film 19 for the gate electrode 1 can be easily performed without any problem.

In the above embodiment, the case where recess etching is performed after the thin film is etched away is exemplified, but the same effect can be obtained even if the thin film is etched away after performing recess etching.

Further, in the present invention, the thin film is not limited to a silicon oxide film, but may also be a silicon nitride film, aluminum oxide, or the like. Furthermore, the present invention is not limited to the shape or process of the gate electrode, but can of course be widely applied to the formation of source electrodes, drain electrodes, and other patterns formed using the lift-off method. moreover,
The present invention is also effective for manufacturing semiconductor devices using other charged beams such as ion beams. Furthermore, the method of exposing the resist film is not limited to electron beams, but it is also effective to use other charged beams such as ion beams.

[Effects of the Invention] As described above, in the semiconductor device manufacturing method according to the present invention, since a thin spacer layer for lift-off is formed on the alignment mark, alignment can be performed by electron beam irradiation when detecting the mark. Even if the mark is exposed, an electrode pattern can be easily formed using the lift-off method. Therefore, it is possible to manufacture a semiconductor device that performs highly accurate and stable mark detection without increasing the exposure time per wafer.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(g) are diagrams for explaining one embodiment of the alignment mark according to the present invention. FIGS. 2(a) to 2(d) are diagrams for explaining conventional alignment marks. 10... Thin film. 11...Semiconductor substrate, I2...
Active layer, 13... Source electrode, 14... Drain electrode, 15... Alignment mark, l6, 26... Resist film, 17-... Electron beam, 18a. 18b,
18x, ■sy-...opening, 19...metal film for gate electrode,

Claims (1)

[Claims] forming an alignment mark for electron beam exposure on a semiconductor substrate; selectively laminating a thin film in a region including the alignment mark for electron beam exposure; and applying a resist film on the semiconductor substrate. a step of irradiating the resist film in a region including the alignment mark for electron beam exposure with an electron beam; a step of irradiating the resist film on the semiconductor substrate with an electron beam according to a predetermined pattern; After developing the resist film and forming an opening in the resist film, and etching away the thin film in a region including the alignment mark for electron beam exposure through the opening, the semiconductor substrate is exposed to the opening. 1. A method of manufacturing a semiconductor device, comprising the step of removing by etching through a hole.