KR0137573B1 - Gate fabrication method of mosfet - Google Patents

Abstract

In a field effect transistor having a fine gate, a method of improving the electrical performance of a device by greatly reducing the resistance and parasitic capacitance of the gate is disclosed.

In the present invention, the first and second resists for electron beam exposure are sequentially applied onto a substrate, and the first and second resists in the gate region are exposed with electron beams according to the gate shape, but are irradiated to form an upper portion of the gate. The energy magnitude of the electron beams and the energy magnitude of the electron beam to be irradiated for the formation of the gate bottom are different.

Description

FABRICATION METHOD FOR GATE OF FIELD EFFECT TRANSISTOR

1A and 1B are cross-sectional views for explaining a method of forming a T-type gate as an example of the prior art.

2b to 2e show a gate forming method according to an embodiment of the present invention, a cross-sectional view showing a method of forming a T-type gate in the order of the process.

＊ Description of symbols for main parts of the drawings ＊

DESCRIPTION OF SYMBOLS 1: Semi-insulating gallium arsenide substrate 2: Two-dimensional electron gas gun

3: aluminum gallium arsenide layer 4: cap layer

5a, 5b: ohmic layers 6, 7: resist

8a, 8b, 8c: electron beam description region distribution 8d, 8e: description region space

9, 9a, 9b: undeveloped resist 11: recessed portion

12, 12a, 12b: gate metal 13: insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a field effect transistor, and more particularly to sub-micron scale the gate pattern of a field effect transistor used in a communication device or a high speed computer such as a high electron mobility transistor. The present invention relates to a method for obtaining a gate line width in which the process is simple and reproducible in forming below.

In the manufacturing technology of a semiconductor device, it is difficult to form a subpattern-class fine pattern by a conventional technique using an optical stepper due to the limitation of the resolution of the optical stepper.

In order to overcome the limitations of the optical stepper technology, a technique of reducing the wavelength of the stepper light source using an excimer laser, a technique of using a phase reversal mask, a technique of reducing the size of the pattern by dry etching after pattern formation, Techniques for using X-rays as light sources, techniques for direct writing using electron beams as light sources have been developed.

All of the above techniques enable the formation of smaller patterns than conventional optical stepper techniques.

However, according to the first to third techniques, it is difficult to obtain a pattern of 0.2 mu m or less, and according to the fourth technique, it is difficult to manufacture a mask.

Therefore, the last electron beam direct drawing technique is mainly used in order to form a pattern of 0.2 micrometer or less at present.

For example, Japanese Patent Laid-Open Nos. 2-266535 and USP 4,700,462 disclose a technique for manufacturing a field effect transistor having a T-type gate.

In Japanese Patent No. 2-266535, a fine pattern is formed using an electron beam, a recess is etched using a resist, and then a metal is deposited, and a resist is applied to form a pattern at the top, and the metal is used. After etching, lift off.

In this way, the resistance of the gate can be reduced, but the exposure process must be performed twice, and the metal layer etching process is difficult to perform.

In USP 4,700,462, an oxide film is formed on a substrate, and then an electron beam resist is applied to form a gate shape.

The oxide film is etched by a resistive ion etchin (RIE) using a resist gate shape, and undercutting is formed in the upper resist by an overdevelopment process, and then metal is deposited and lift-off.

This makes the formation of the fine pattern relatively smooth, but it is difficult to etch the oxide film and the width of the top metal of the T-type gate does not become much wider than that of the bottom metal.

In general, in devices that require the formation of fine gates, the narrower the gate width, the larger the gate resistance and parasitic capacitance.

Many attempts have been made to reshape the gate to solve this problem.

`` L.D. Nguyen, P.J. Tasker, D.C. Radulescu, and L.F. Estman, “Design, Fabrication, and Characterization of Ultra High Speed AlGaAs / InGaAs MOSFET ’s,” IEDM Tech. Dig., December 1988, pp. 176-179., Chao et al., “Electron Beam Fabrication of Quater-Micron T-spaped Gate FETs Using a New Tri-Layer Resist System.” IEDM Tech. Dig., Deathbr 1983, pp. 613-616. Discloses a resist structure for the formation of a T-type gate.

1A and 1B are cross-sectional views showing a method of forming a T-type gate of a field effect transistor according to the prior art.

In FIG. 1A, reference numeral 1 denotes a semi-insulating gallium arsenide substrate, 2 denotes a 2-dmentional elctron gas layer, 3 denotes an aluminum gallium arsenide (AlGaAs) layer, and 4 denotes a cap. Layers 5a and 5b represent ohmic layers and 6 and 7 represent resist, respectively.

Referring to FIGS. 1A and 1B, a conventional method of forming a T-type gate using an electron beam exposure technique will be described in detail as follows.

First, the two-dimensional electron gas layer 2, the aluminum gallium arsenide layer 3, and the cap layer 4 are sequentially formed on the substrate 1, and then ohmic layers 5a and 5b are formed.

The first resist 6 is applied to the cap layer 4 by heat treatment, and then the second resist 7 is applied to perform heat treatment.

An electron beam lithography technique is then used to create a T-shape in the resists 6, 7.

At this time, exposure of each resist is performed by electron beam of uniform energy.

Finally, referring to FIG. 1B, a gate metal is deposited in a vacuum by an electron beam deposition method.

According to this method, there is a limit to reducing the gate resistance because the resistance of the gate metal is determined by the cross-sectional area of the gate metal formed by the electron beam exposure technique.

An object of the present invention is to significantly reduce the resistance and parasitic capacitance of the fine gate to improve the electrical performance of the device.

The method of the present invention comprises the steps of sequentially applying a first resist and a second resist for electron beam exposure on a substrate; Exposing the first and second resists in the gate region with electron beams according to a gate shape, wherein the energy magnitudes of the electron beams irradiated for the formation of the gate and the energy magnitudes of the electron beams irradiated for the formation of the gate are different. It includes.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2E.

2A through 2B illustrate a process sequence for forming a fine T-type gate according to an embodiment of the present invention.

Referring to FIG. 2A, first, a two-dimensional electron gas layer 2, an aluminum gallium arsenide layer 3, and a doped Schottky layer are sequentially formed on the substrate 1 in order. Thereafter, the ohmic layers 5a and 5b are formed.

Subsequently, the first resist 6 is applied on the cap layer 4 to a thickness of about 2000 kPa, and heat treated at a temperature of about 190 ° C.

At this time, PMMA (polymethylmetacrylate) is used as the first resist 6.

Next, the second resist 7 is applied onto the first resist 6.

At this time, P (MMA-MAA) is used as the second resist 7.

Then, an exposure process using an electron beam of nonuniform energy is performed.

At this time, in the direct drawing of the pattern for forming the shape of the gate in the resists 6 and 7, electron beams each having spatially separated and non-uniformly set energies at a predetermined distance are used.

In FIG. 2A, 8a, 8b, and 8c represent first to third electron beams irradiated with a resist, respectively, and it can be seen that two adjacent electron beams are spatially separated from each other at a predetermined distance of 8c and 8d.

These distances can be changed from 0 to the hand drawing point (in this example, 1 drawing point = 0.025 µm).

If the energy of the electron beam is 30KV, 1 to 3 drawing points are appropriate.

In order to form the T-gate, the first electron beam 8a and the third electron beam 8c have an energy enough to expose only the second resist 7, and the second electron beam 8b is the second and the second. One resist 6 or 7 has an energy that can expose all of them.

In this way, by appropriately adjusting the energy of each of the first to third electron beams, it is possible to form a gate having an arbitrary shape (for example, a T-type or a gamma-type).

When drawing the pattern for the electron beam exposure process as described above, only the size of each part of the pattern is determined and only different energy may be specified at the time of exposure.

2b shows the T-gate shape 8 of the resist formed by the electron beam exposure process.

The inclined surface 7a of the shape 8 is used in a later lift-off process.

Even after the electron beam exposure process is performed, as shown in FIG. 2B, the remaining films 9, 9a, and 9b of the undeveloped resist are present in the region where the gate is to be formed.

These undeveloped resist residual films make it impossible to form a pattern of uniform size.

Therefore, the undeveloped resist residual films 9, 9a, and 9b are removed by dry etching using an oxygen plasma.

This determines the width 10 of the gate bottom, as shown in FIG. 2C.

Next, referring to FIG. 2d, the cap layer 4 is selectively recess-etched to have the inclined surface 11 inclined by about 45 degrees in the gate region, and then the gate metals 12, 12a, and 12b. E).

Next, referring to FIG. 2E, a gate is formed by lifting off the first resist 7, and an insulating film 13 is deposited to prevent oxidation of the recess etched cap layer 4.

According to the present invention described above through the embodiment the following advantages are obtained.

Since direct drawing is performed by one data file, the process is convenient and economical in comparison with conventional techniques requiring multiple exposure processes.

One-time direct drawing reduces the occurrence of errors due to changes in energy and alignment.

T-shaped or When forming a resist pattern for forming the top of the -type gate, electron beams having different energies are used, so that the size of the top of the gate can be adjusted as desired, thereby reducing the gate resistance and parasitic capacitance. .

Since the width of the lower portion of the gate is determined by dry etching, a uniform gate pattern can be obtained and the reproducibility of the gate line width is excellent.

Claims (3)

In the method of forming the gate of the field effect transistor, Sequentially applying an electron beam exposure first resist and a second resist onto the substrate; Exposing the first and second resists in the gate region with electron beams according to a gate shape, wherein the energy magnitudes of the electron beams irradiated for the formation of the gate and the energy magnitudes of the electron beams irradiated for the formation of the gate are different. Gate forming method of a field effect transistor comprising a. Forming a two-dimensional electron gas layer (2), an aluminum gallium arsenide layer (3), and a cap layer (4) sequentially on the substrate (1), and then forming ohmic layers (5a, 5b); Applying a first resist (6) for electron beam exposure on the cap layer (4) to a thickness of about 2000 kPa, and heat-processing at a temperature of about 190 占 폚; Applying a second resist (7) for electron beam exposure on the first resist (6); Irradiating the first and second resists with electron beams each having spatially separated and non-uniformly set energies at a predetermined distance to form a gate in the first and second resists; Removing undeveloped resist residual films (9, 9a, 9b) in the gate shape of the first and second resists by dry etching; Selectively recess etching the cap layer (4) so that the cap layer (4) has an inclined surface (11) in the gate region, and then depositing gate metals (12, 12a, 12b); Forming a gate by lifting off the first resist 7 and depositing an insulating film 13 to prevent oxidation of the recess etched cap layer 4. Forming method. The method of claim 2, And the electron beam exposure process is performed such that the second resist has a reverse slope (7a).