JPH0575146A - Manufacture of filed-effect semiconductor devices - Google Patents

Abstract

PURPOSE:To make it possible to form dual gates in greater detail, by forming an isolated resist pattern with a negative resist or a resist pattern having a very small opening with a positive resist. CONSTITUTION:An active layer is formed on a semi-insulation semiconductor substrate 11. A negative layer (NR) 15 is applied on the active layer 12 and electrode 13 and 14 so that a clearance shape between dual gates may be exposed with an electron beam 16. The negative resist NR 15 is developed, and a negative resist pattern (NG) 15a may be left and the active layer 12 is formed on a region 17. A positive resist layer 18 (PR) is developed with a developer which is unable to dissolve the negative resist (NR) 15 so as to bore an opening 20 on the emitted portion where a negative resist (NG) 15A remains. The gate electrode-shaped openings (GO) 20A and 20B are specified with the opening of the positive resist layer (PR) 18 and the negative resist layer (NG) 15A. The whole surfaces are clad with gate metals, which forms a metal film on the NG 15A and the PR 18 while gate electrodes 23 and 24 are simultaneously formed directly on the active layer 12 in the portions of the GO 20A and 20B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor semiconductor device, and more particularly to a method of manufacturing a field effect semiconductor device having a dual gate.

[0002]

2. Description of the Related Art As shown in FIG. 1, a dual gate field effect semiconductor device is a compound semiconductor semi-insulating substrate 1.
And a epitaxial substrate 2 on the semiconductor substrate 3, a source electrode 4 and a drain electrode 5 on the substrate 3, and two gate electrodes 6 and 7 between these electrodes. This dual gate field effect semiconductor device is conventionally manufactured as follows.

First, an active layer 2 of a compound semiconductor is formed on a compound semiconductor substrate 1 of GaAs, InP or the like by an epitaxial growth method. On the active layer 2, an electrode metal (for example, by a sputtering method or a vacuum deposition method) (for example,
AuGe) is deposited to form a metal film, a source electrode 4 and a drain electrode 5 having a predetermined pattern are formed by a lithography technique, and heat treatment is performed. Next, a positive resist is applied on the entire surface to form a resist layer, and the gate electrode shape pattern is exposed and developed to form a positive resist pattern (not shown). A metal film is deposited on the entire surface of this semiconductor substrate with a resist pattern by sputtering or vacuum deposition in a vacuum to form a metal film, and the positive resist pattern is removed with a solvent. At that time, the metal film portion (most part) on the resist is removed. At the same time, they are removed (by so-called lift-off) to form the gate electrodes 5 and 6 as shown in FIG.

[0004]

The dual gate field effect semiconductor device (transistor) has high performance (higher frequency,
In order to reduce noise, it is necessary to miniaturize the semiconductor device. In the conventional manufacturing method, the dual gate itself is miniaturized and the electrode distance between these gates is 0.25 μm.
It is difficult to do the following. In the usual case, it depends on the line and space of resist development, and this electrode distance is narrowed to about 0.5 μm.

An object of the present invention is to provide a manufacturing method capable of miniaturizing a dual gate field effect semiconductor device.

[0006]

[Means for Solving the Problems]

The above-mentioned objects are steps (a) to (d): (a) a step of forming a thin line negative resist pattern on a compound semiconductor substrate, (b) a positive resist on the negative resist pattern and the compound semiconductor substrate And apply
A step of forming a positive resist pattern having gate-shaped openings on both sides of the negative resist pattern by exposure and development, (c) a step of depositing a metal film on the entire surface, and (d) removal of the negative resist pattern and the positive resist pattern. And a step of selectively removing the metal film on the gate electrode to form two gate electrodes, the method for manufacturing a field effect semiconductor device.

In the positive resist pattern forming step, a low-sensitivity positive resist is applied on the negative resist pattern and the compound semiconductor substrate and pre-baked to form a first positive resist layer, and a high-sensitivity positive resist is applied thereon to pre-bak. To form a second positive resist layer, and expose the positive resist layer with an electron beam at a high dose amount to a portion corresponding to the gate electrode and a low dose amount to a peripheral portion thereof, and then develop the same. May be composed of

In the positive resist pattern forming step,
The exposure pattern is usually one including the portion corresponding to the gate electrode, but it may be two of the two portions corresponding to the gate electrodes.

[0009]

In the present invention, the use of a negative resist facilitates the formation of an extremely fine isolated resist pattern (thin line resist pattern), and the use of a positive resist facilitates the formation of a resist pattern having fine openings. By combining the advantages of the above, a gate electrode-shaped opening is formed in the resist layer. Mixing does not occur even if a positive resist is applied on the negative resist layer, and since the negative resist does not dissolve during the development of the positive resist layer, it is possible to leave a fine line resist pattern and form openings on both sides of it. it can.

In order to avoid mixing when the positive resist layer has a two-layer structure of the first and second positive resist layers, the first positive resist layer is prebaked and then the second positive resist layer is prebaked.
Apply positive resist. If attention is paid to the opening only in the second positive resist layer, this is larger than the opening in the first positive resist layer, and the cross-sectional area of the gate electrode can be increased to prevent the resistance of the gate electrode from increasing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings by way of example embodiments of the present invention. 2-8,
FIG. 6 is a schematic cross-sectional view illustrating a process of manufacturing a dual gate field effect semiconductor device according to the manufacturing method of the present invention.

As shown in FIG. 2, the active layer 12 is formed by epitaxial growth on the semi-insulating semiconductor substrate 11 as in the conventional case. For example, the n-GaAs epitaxial active layer 12 is formed on the semi-insulating GaAs substrate 11 by CVD to have a thickness of 100 nm. Then, the source electrode 13 and the drain electrode 14 are formed on the active layer 12 so as to face each other. For example, a resist is applied on the active layer 12, exposed and developed to form a resist pattern (not shown) having openings for a source electrode and a drain electrode, and an electrode metal (AuGe) having a thickness of about 200 nm is formed on the entire surface. Then, the source electrode 13 and the drain electrode 14 are formed by a vacuum evaporation method and a lift-off method by removing the resist pattern. After forming the electrodes, heat treatment is performed at 450 ° C. for several minutes to form ohmic contacts.

As shown in FIG. 3, the exposed active layer 1
2 and electrodes 13, 14 on top of a negative resist (eg
SAL601-ER7: Product of Shipley Far East Co., Ltd.)
Is applied to form a negative resist layer 15 and the shape of the gap between the gates of the dual gate is exposed (drawn) with an electron beam 16.
To do. For example, the width of the negative resist layer 15 having a thickness of 0.5 μm
Irradiation with an electron beam 16 of 0.2 μm at an acceleration voltage of 30 keV and a dose of 50 × 10 ⁻⁶ coulomb / cm ² .

As shown in FIG. 4, the negative resist layer 15 is developed and the fine line-shaped isolated resist pattern 15 in the irradiated portion is developed.
The active layer 12 is exposed in the region 17 while leaving A. For example,
Develop a solution that dissolves the non-irradiated area with an organic alkaline solution.
The fine linear resist pattern 15A having a thickness of 0.2 μm is used. Next, as shown in FIG. 5, a positive resist (for example,
ZCMR-100: a product of Nippon Zeon Co., Ltd.) is applied to form a positive resist layer 18 and exposed (drawn) with an electron beam 19 in a size (one exposure pattern) of the dual gates. For example, a positive resist layer 18 having a thickness of 0.6 μm
And an electron beam 19 having a width of 0.6 μm is accelerated at an acceleration voltage of 30 keV:
Irradiate with a dose amount of 150 × 10 ⁻⁶ coulomb / cm ² .

As shown in FIG. 6, the positive resist layer 18 is developed with a developing solution that does not dissolve the negative resist to open the opening 20 in the irradiated portion, and the negative resist pattern 15 is formed therein.
Leave A. With the opening 20 of the positive resist layer 18 and the negative resist pattern 15A, the gate electrode shape opening 20A,
20B is specified. For example, in the development in which the irradiated portion is dissolved with an organic solution (methyl ethyl ketone), the dual gate entire pattern opening 20 having a width of 0.6 μm is opened, and the openings 20A and 20B are formed in the opening 20A, and the active layer 12 is exposed. There is.

As shown in FIG. 7, by depositing a gate metal on the entire surface, a metal film 21 is formed on the resist patterns 15A and 18 and at the same time, directly on the active layer 12 at the openings 20A and 20B. The first gate electrode 23 and the gate electrode 24 are formed. For example, Al is deposited on the entire surface to a thickness of 0.5 μm by a vacuum deposition method. Then, as shown in FIG. 8, the resist patterns 15A and 18 are removed by a solvent (resist remover), and the metal film 21 on the resist pattern is also removed (lifted off). In this way, the dual gate electrodes 23 and 24 are completed,
A field effect semiconductor device can be obtained. These gate electrodes 2
3 and 24 each have a width of 0.2 μm, and the distance between these gate electrodes is 0.2 μm, so that miniaturization of the dual gate can be achieved. The semiconductor device shown in FIG. 8 has basically the same structure as the semiconductor device shown in FIG. 1 except for the difference in size.

In the electron beam exposure shown in FIG. 5, if the position of the electron beam 19 is shifted to the left (or right) in the drawing, the width of the first gate electrode 23 becomes slightly larger, while the second gate electrode 24 is made wider. The width of becomes a little smaller. In this way, the width of the gate electrode can be made different. In addition, as shown in FIGS. 9 and 10, the positive resist layer 1
In the electron beam exposure of No. 8, two electron beams 31A and 31B may be used instead of the electron beam 19 of FIG. 5 to perform exposure and development. These electron beams 31A, 31
The pattern shape of B is the shape of the gate electrodes 23 and 24, and the openings 20A and 20B are formed in the positive resist layer 18 after development.
Is open. In this case, the electron beams 31A, 31
By changing the pattern shape of B, the gate electrode width can be controlled and different electrode widths can be set. Can be changed. Note that the source / drain electrodes are omitted in FIGS.

Furthermore, as another embodiment, after forming the negative resist pattern 15A of FIG. 4 as described above, instead of the positive resist layer 18 (FIG. 5), as shown in FIG.
It is also possible to employ a two-layer structure of a low sensitivity positive resist layer 41 and a high sensitivity positive resist layer 42 as shown in FIG. In this case, a low-sensitivity positive resist is applied on the entire surface and pre-baked to form a positive resist layer 41, and a high-sensitivity positive resist is applied thereon and pre-baked to form a positive resist layer 42. Prebaking can prevent mixing of these resists. Then, when the electron beam exposure is performed, the electron beam is composed of the central high dose portion 43A and the low dose portions 43B on both sides as shown in FIG. The electron beam of the high dose amount portion 43A corresponds to the electron beam 19 in FIG.

When exposed and developed, an opening 44 as shown in FIG. 12 is formed in the high-sensitivity positive resist layer 42, and in the opening 44, openings 20A and 20B having gate electrode shapes are further formed.
Are exposed in the low-sensitivity positive resist layer 41. As shown in FIG. 13, by depositing a gate metal (Al) on the entire surface, a metal film 45 is formed on the resist pattern, and at the same time, a portion directly contacting the active layer 12 at the openings 20A and 20B is formed. A first gate electrode 46 and a gate electrode 47 consisting of the exposed portion on the low-sensitivity positive resist layer 41 are formed. Then, as shown in FIG. 14, the resist patterns 41 and 42 are removed by a solvent (resist remover), and the metal film 45 on the resist pattern is also removed (lifted off). In this way, the dual gate electrodes 46 and 47 are completed, and the field effect semiconductor device is obtained. In this case, each of the gate electrodes 46 and 47 has an L-shaped cross section, and since a horizontal portion is added, the resistance of the gate electrode itself can be reduced accordingly.

[0020]

As described above, according to the manufacturing method of the present invention, the dual gate can be formed finer than the conventional one, and a high performance dual gate field effect type semiconductor device such as high frequency and low noise can be obtained. Can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a dual gate field effect semiconductor device.

FIG. 2 is a schematic cross-sectional view of a semiconductor device in which source / drain electrodes are formed.

FIG. 3 is a schematic cross-sectional view of a semiconductor device exposing a negative resist layer.

FIG. 4 is a schematic cross-sectional view of a semiconductor device on which a negative resist pattern is formed.

FIG. 5 is a schematic cross-sectional view of a semiconductor device exposing a positive resist layer.

FIG. 6 is a schematic cross-sectional view of a semiconductor device in which a positive resist layer is developed.

FIG. 7 is a schematic cross-sectional view of a semiconductor device having a gate metal deposited thereon.

FIG. 8 is a schematic cross-sectional view of a dual gate field effect semiconductor device manufactured by the method of the present invention.

FIG. 9 is a schematic cross-sectional view of a semiconductor device in which a positive resist layer is exposed with two electron beam patterns.

FIG. 10 is a schematic cross-sectional view of a semiconductor device having a positive resist layer developed.

FIG. 11 is a schematic cross-sectional view of a semiconductor device in which a positive resist layer is exposed with electron beam patterns having different dose amounts.

FIG. 12 is a schematic cross-sectional view of a semiconductor device having a positive resist layer developed.

FIG. 13 is a schematic cross-sectional view of a semiconductor device having a gate metal deposited thereon.

FIG. 14 is a schematic sectional view of a field effect semiconductor device having a dual gate having an L-shaped section.

[Explanation of symbols]

 11 ... Semi-insulating semiconductor substrate 12 ... Active layer 13, 14 ... Source / drain electrode 15 ... Negative resist layer 15A ... Negative resist pattern 16, 19 ... Electron beam 18 ... Positive resist layer 20A, 20B ... Gate electrode shape opening 21 ... Metal film 23 ... First gate electrode 24 ... Second gate electrode 31A, 31B ... Electron beam 41 ... Low sensitivity negative resist layer 42 ... High sensitivity negative resist layer 46, 47 ... Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/338 29/812 7352-4M H01L 21/30 361 S 7739-4M 29/80 F

Claims (4)

[Claims] 1. A method of manufacturing a field effect semiconductor device having a dual gate, comprising the following steps (a) to (d): (a) a thin line negative resist pattern on a compound semiconductor substrate (11, 12). (15A) is formed, (a) A positive resist is applied on the negative resist pattern and the compound semiconductor substrate, and a gate-shaped opening (20A, 20B) is formed on both sides of the negative resist pattern by exposure and development. Positive resist pattern (1
8) forming step, (c) depositing a metal film on the entire surface, (d) removing the negative resist pattern and the positive resist pattern, and selectively removing the metal film (21) thereon. And a step of forming two gate electrodes (23, 24), a method of manufacturing a field effect semiconductor device. 2. The positive resist pattern forming step,
A low-sensitivity positive resist is applied on the negative resist pattern and the compound semiconductor substrate and prebaked to form a first resist.
A positive resist layer (41) is formed, a high-sensitivity positive resist is applied thereon, and prebaked to form a second positive resist layer (42). These positive resist layers are gated by an electron beam (43A, 43B). 2. The manufacturing method according to claim 1, wherein the portion corresponding to the electrode is exposed with a high dose and the peripheral portion is exposed with a low dose, and then developed. 3. The manufacturing method according to claim 1, wherein in the positive resist pattern forming step, the exposure pattern (19) is one including a portion corresponding to a gate electrode. 4. The manufacturing method according to claim 1, wherein, in the positive resist pattern forming step, there are two exposure patterns (31A, 31B) only corresponding to the gate electrodes.