JPH03161966A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the leak current of a transistor and reduce power consumption, by constituting a memory cell by using an FF constituted of a pair of inverters, and constituting a transistor as a double gate structure in a storage device in which a thin film transistor operates as the load element of an inverter. CONSTITUTION:A memory cell is constituted of an FF 11 and a pair of a transferring transistors 12, 13. The FF 11 is constituted by cross-coupling the input and the output of a pair of inverters 14, 15. The driving transistor 16, 17 of the inverters 14, 15 are NMOS transistors, and load transistor 21, 22 are PMOS transistors. The transistors 21, 22 have double gate structure. Leak current of the load transistors 21, 22 are mainly generated in a P<+> i-junction in the vicinity of a drain region. When the transistors 21, 22 have the double gate structure in this manner, the voltage of the P<+> i-junction in the vicinity of one drain region is lowered, and the leak current is reduced.

Description

[Detailed Description of the Invention] [Field of Application in Industry] The present invention is a semiconductor CMOS type SRAM, in which the load element of a Frisopflosop inverter constituting a memory cell is changed from a thin film transistor to a semiconductor. It's about memory.

[First Summary of the Invention] The present invention provides a semiconductor memory as described above, in which the thin film transistor serving as the load element of the inverter has a double gate structure, thereby reducing power consumption and increasing reliability.

[Conventional technology]

In resistive load type MOS-SRAMs, problems such as high resistance are approaching the limit and it is becoming difficult to secure current during data writing are occurring. For this reason, there is a movement in MOS-SRAMs from a resistive load type to a complete CMOS type.

In order to make the chip area of a complete CMOS SRAM as small as that of a resistive load type MOS-SRAM, a so-called stacked CMOS SRAM, in which the load element is composed of thin film transistors and these thin film transistors are stacked on a bulk transistor, has been considered. (For example, “Nikkei Microdehys J (1988.9) P.123
-130).

On the other hand, it is advantageous to form the semiconductor film to be used as the active layer of the active layer of the film 1/transistor using a polycrystalline semiconductor film rather than a single-crystalline semiconductor film, etc., since it can be formed using a low-temperature process. It is said that there is.

[Problem to be solved by the invention]

However, in thin film transistors in which a polycrystalline semiconductor film is used as an active layer, it is generally difficult to sufficiently reduce leakage current. If the leakage current is large, not only power consumption is large, but also reliability is low because the logic amplitude is small and memory retention ability is low.

[Means to solve the problem]

In the semiconductor memory according to the present invention, inverters 14 and 15
The thin film transistors 21 and 22 serving as load elements have a double gate structure.

[Effect]

In the semiconductor memory according to the present invention, inverters 14 and 15
The voltage between the source and drain of the thin film transistors 21 and 22, which serve as load elements, is divided into two sets of source and drain, and the voltage between the source and drain of each set is low. Therefore, even if the active layers of the thin film transistors 2l and 22 are formed by the polycrystalline semiconductor film 45, the leakage current of the thin film transistors 21 and 22 is small.

〔Example〕

Embodiments 1 to 6 of the present invention will be described below with reference to FIGS. 1 to 9.

1 and 2 show a first embodiment.

In this first embodiment, as shown in FIG. 1, a memory cell is constructed of a Frisopflip 1l and a pair of transfer transistors 12 and 13, and the Frisopflip 1l is composed of a pair of inverters 14, It is constructed by cross-coupling 15 human outputs.

Drive transistors 16 and 17 for inverters 14 and l5
is an nMOS transistor, and is it for load? Ranjistor 2
1 and 22 are PMOS transistors, and these load transistors 21 and 22 have a double gate structure.

A power line 23 is connected to the load transistors 21 and 22, a ground line 24 is connected to the drive transistors 16 and 17, and bisoto lines 25 and 26 and a word line 27 are connected to the transfer transistors 12 and 13, respectively. .

FIG. 2 shows the inverter 14. Next, the manufacturing process of this inverter 14 will be explained.
Since the inverter 15 is also manufactured in the same manner as the inverter 14, a description of the manufacturing process of the inverter 15 will be omitted in principle.

First, an Si02 film 32 for element isolation is formed on the Si substrate 3l, and an SiO2 film 32 as a gate insulating film is formed on the surface of the Sf substrate 31.
■The film 33 is formed, and further the driving transistors 16 and l7
The gate electrodes 34 and 35 are shaped. gate electrode 34,
Reference numeral 35 indicates a certain polycide structure consisting of an n+ type polycrystalline Si film 36 and a WSix film 37.

Next, the gate electrodes 34, 35 and the SiO2 film 32 are removed. The n1 region 41, which is the source region, and the n° region 42, which is the drain region, of the driving transistor 16 are formed in a self-aligned manner. However, the gate electrode 35 is buried in contact with the n'' region 42.

After that, SiO, which is an interlayer insulating film, is formed. depositing a film 43;
A contact hole 44 reaching the gate electrode 35 and the n'' region 42 is provided in the Si02 film 43.

Next, the load transistor 21 which is a thin film transistor
A polycrystalline Si film 45 is used as an active layer, and a SiO2 film 46 is used as a gate insulating film.
Amorphous Si is produced by low pressure CVD at a temperature below 580°C.
A film (not shown) is first deposited.

When the temperature during this low pressure CVD is set to 580° C. or higher, the quality of the deposited St film does not deteriorate.

In that case, the Si film is made amorphous by ion-implanting Si into the deposited Si film.

Then, using infrared lamp light, excimer laser light, etc.
02 atmosphere at 1100℃ for about 20 seconds? Perform a short-temperature heat treatment. Then, the polycrystalline Si film 4 changes from the amorphous Si film.
5 and SiO■ on the surface of this polycrystalline Si film 45.
The shape of the membrane 46 progresses substantially simultaneously.

Polycrystalline Si film 45 that took shape after such high-temperature, short-time heat treatment
The particles have uniform particle size, good surface flatness, and high performance such as mobility. Therefore, the high performance load transistor 2l
can be created. Further, the Si02 film 46 is also flat and of good quality. Therefore, in the load transistor 21, there is little reduction in breakdown voltage due to pinholes and the like.

Furthermore, since the polycrystalline Si film 45 and the SiOz film 46 are formed almost simultaneously, the manufacturing process is also short. Further, by performing the above-described high-temperature, short-time heat treatment in a pressurized O2 atmosphere, the flatness of the polycrystalline Si film 45 and the Si02 film 46 can be further improved.

In order to form the polycrystalline Si film 45 and the SiOz film 46, conventionally, the polycrystalline Si film 45 itself is deposited and then thermal oxidation is performed to form the Sing film 46, or the method of depositing Further on the polycrystalline Si film 45? A method has been adopted in which a Si02 film 46 is deposited by CVD and this SiO2 film 46 is densified by heat treatment using a lamp or the like.

However, since thermal oxidation is usually performed in a high-temperature diffusion furnace, re-diffusion of the underlying n+ regions 41 and 42 occurs. Furthermore, even if densified, the Sin2 film 46 deposited by CVD is inferior in film quality, such as withstand voltage, compared to the SiOz film 46 formed by thermal oxidation.

Furthermore, in either method, the polycrystalline Si film 45 and the SiO
The flatness of the film 46 is poor. For example, in the thermal oxidation method, oxidation is performed after the formation of the polycrystalline Si film 45 is completed, and at this time, grain boundaries are preferentially oxidized, resulting in large irregularities.

After forming the polycrystalline Si film 45 and SiO2 film 46 as described above, a polycrystalline Si film 47 is further formed, and the polycrystalline S+ film 47 and SiO2 film 46 are vacuumed into a double gate structure. , the gate electrodes 51 and 52 of the load transistor 21 are formed.

Then, inside the polycrystalline Si film 47 and this polycrystalline Si film 4
7 as a mask, impurities are introduced into the polycrystalline Si film 45 to make these polycrystalline Si films 45 and 47 p' type.

Furthermore, the polycrystalline Si film 45 is applied to the load transistor 2.
Patterning is performed in the pattern of the active layer of I.

However, if left as is, the polycrystalline Si film 45 and the n+ region 42 form a pn junction, and the contact resistance between them is large, causing a potential drop and the like.

Therefore, as shown in Fig. 2, polycrystalline Sill45 and n+
The laser mask 53 is patterned to expose only the contact portion with the Jli region 42 and its vicinity, and in this state,
XeCl! Noble gas halide excimer laser (wavelength -
308 nm) to 1.5 to 2. Irradiation is performed with an energy of approximately 0 Jcm-''.

As a result, the polycrystalline Si film 45 of the irradiated area and the n'' region 42
are melted to form the alloy portion 54, and the contact resistance between the two is reduced. After that, this first step is performed by a conventionally known process.
Complete the example.

By the way, leakage in the load transistors 2I and 22, which are thin film transistors, mainly occurs at the p''i junction near the drain region.However, in this 9th embodiment, the load transistors 2I and 22 have a double gate structure. , p near one drain region
″ The voltage at the i-junction is low, and leakage current is significantly reduced.

Note that in order to reduce leakage current, the channel length is set to 2.
It is also being considered to double the size or create an offset gate structure. However, as mentioned above, since leakage occurs mainly at the p + + junction near the drain region, this embodiment is less effective than the first embodiment.

FIG. 3 shows the inverter 14 of the second embodiment. This second embodiment has a polycrystalline Si film 45 and an n. It has substantially the same configuration as the first embodiment described above, except that the w4 region 42 is connected mainly through the TiSiz film 55.

To improve the shape of the TiSi2 film 55, the gate electrodes 51, 5
2, the side walls of the Si02 film 56 are shaped, and in this state a Ti film (not shown) is deposited by subsotering.

Then, the Ti film is reacted with the Si substrate 31 and the polycrystalline Si films 45 and 47 in a first stage annealing at about 600°C to form a TiSi film, and then annealed in a second stage at about 800°C. to change the TiSi film to TiSiz film 55,
Remove unreacted Ti film.

In the second embodiment, the contact resistance between the polycrystalline Si film 45 and the r) region 42 is low, and the load transistor 2
The sheet resistance of the source/l/rain regions of No. 1, the gate electrodes 51 and 52, and the power supply line 23 is also low.

FIG. 4 shows the manufacturing process of the inharter 14 of the third embodiment. In manufacturing this third embodiment, substantially the same steps as in the above-mentioned embodiments 1 and 2 are performed up to the shape of the contact 1 and the hole 44.

Thereafter, as shown in FIG. 4A, the contact 1/hole 44 is filled with a W film 57 by selection of W [CV I].

And again, substantially the same as in the second embodiment, the fourth
As shown in Figure B, a p-type polycrystalline S with a thickness of about 300
The i film 45 is formed, and the gate electrode 5l is formed as shown in FIG. 4C.
, 52, and a Sin2 film 56 is formed as the side walls of the gate electrodes 51 and 52 as shown in FIG. 4D.

I ■ Next, as shown in FIG. 4E, the exposed polycrystalline Si films 45 and 47 are used as seeds to selectively lengthen the W film 58, and all of the exposed polycrystalline Si film 45 is is replaced with a W film 58. However, in this state, although the polycrystalline Si film 45 and the W film 58 under the gate electrodes 51 and 52 are in direct contact, the contact resistance therebetween is not sufficiently low.

Therefore, annealing at about 600° C. is then performed. Then, a WSi2 film (not shown) is formed at the interface between the W film 58 and the polycrystalline Si film 45, forming a contact structure of W film 58/WSi2 film/polycrystalline Si film 45, resulting in low resistance. It will be done.

Thereafter, this third embodiment is completed by a conventionally known process.

In such a third embodiment, not only the space between the polycrystalline Si film 45 and the n' region 42 but also the space between the polycrystalline St film 45 and the polycrystalline St film 45 and the
W films 57 and 58 are also interposed between the film 36 and the resistance of the contact structure between the W film 58 and the polycrystalline Si film 45 is low. Therefore, the polycrystalline Si film 45 and the polycrystalline Si film 36
The contact resistance between the first and second embodiments is even lower than that of the first and second embodiments.

1 2? FIG. 5 shows a part of the manufacturing process of the inverter 14 in the fourth embodiment. In manufacturing this fourth embodiment, the SiO2 film 56 which is the side wall of the gate electrodes 51 and 52 is
Up to this point, substantially the same steps as in the third embodiment described above are executed.

Then, a Ti film (not shown) is deposited by sputtering or the like, so that all of the exposed polycrystalline Si film 45 becomes TiSi.
Heat treatment is performed to the extent that it becomes z. Then, as shown in FIG. 5, all of the exposed polycrystalline Si film 45 becomes TiSiz II! in a self-aligned manner. 6 Replaced by 1.

Thereafter, the unreacted Ti film is removed, and further steps known in the art are carried out to complete the fourth embodiment.

In such a fourth embodiment, since the contact resistance between the polycrystalline Si film 45 and the TiSiz film 61 under the gate electrodes 51 and 52 is originally low, the same effects as in the third embodiment described above can be achieved.

FIG. 6 shows the driving transistor 16 of the fifth embodiment.
The manufacturing process is shown. This production] In the second stage, 6A
As shown in the figure, first, a Sin2 film 3 is deposited on the surface of a Si substrate 31.
2 and 33, and a gate electrode 34 consisting of -Si) (film 3713), n" regions 41 and 42, and SiO
(2) Shaping the film 56 in sequence.

Next, a Ti film (not shown) is deposited on the entire surface by spa sottering or the like, and the Ti film (not shown) is deposited on the entire surface by annealing with infrared lamp light.
The film and the Si substrate 31 are reacted, and the unreacted Ti film is removed by selective etching. As a result, as shown in FIG. 6B, TiS is formed on the surfaces of the n'' regions 41 and 42 in a self-aligned manner.
The i2 membrane 62 is formed.

Next, as shown in FIG. 6C, a Sing film 43 is deposited,
As shown in FIG. 6D, contact holes 44 reaching the n4 regions 41 and 42 are formed in the Sj02 film 43 and the TiSi2 film 62. Furthermore, as shown in FIG. 6E, selection C of W
The contact hole 44 is filled with a W film 57 by VD. Note that this may be done in the form of a contact hole 44 for the TiSi2 film 62 or in a dry pretreatment during pretreatment of W selective CVD.

Next, by performing annealing at about 800°C in an NH3 atmosphere, for example, as shown in FIG. 6F,
A WN film 63, which is a barrier metal, is formed at the interface between the W film 57 and the n' regions 41 and 42. After step 14, this fifth embodiment is completed by a conventionally known process.

In such a fifth embodiment, the contact hole 44 is made of TiSi.
It also penetrates the Z film 62, and the W film 57 starts to be deposited only from the Si substrate 31. Therefore, the metal fufluoride film formed by WF6 used in W selective CVD is different from WllΔ and the Si substrate 31.
The contact resistance between the two is low.

On the other hand, if the contact hole 44 does not penetrate the TiSi2 film 62, a TiF film is formed at the interface between the TiSiz film 62 and the W film 57 during the initial reaction process of W selective CVD, and the W film 57 and The contact resistance with the St substrate 3l increases.

Note that the TiSi2 film 6 is used as the inner wall surface of the contact hole 44.
2 is exposed, but on the exposed surface of this TiSiz film 62, a TiN film or a TieX film, which is difficult to be etched with hydrofluoric acid, is naturally formed. Therefore, the W film 57 is not deposited due to the reduction reaction caused by the metal, and therefore no TtF film is formed.

l5 On the other hand, since the TiN film and the TieX film described above are very thin with a thickness of about 50λ, a tunnel current flows between the W film 57 and the TiSiz film 62. Therefore, the overall contact resistance between the W film 57, the Si substrate 31, and the TiSiz film 62 is extremely low.

Note that the inner wall surface of the contact hole 44 is made of TiSi.
In order to reliably prevent the TiF film from forming on the exposed surface of the Z film 62, after forming the contact hole 44, for example, N.
The exposed surface of the TiSi2 film 62 may be nitrided by annealing for about 60 seconds (1.30 seconds) in an H3 atmosphere.

FIG. 7 shows a modification of the fifth embodiment shown in FIG. That is, if the cross section of the TiSi2 film 62 is shifted in a convex shape as shown in FIG. 7, the contact resistance between the W film 57 and the TiSi2 film 62 is further reduced.

FIG. 8 shows the process of connecting the bit line 25 and other Al wiring lines in the sixth embodiment. When connecting the 82 wiring 64 not shown in FIG. 8A by embedding a W film in the same way as in the case of FIG. 6? There is a problem with

Therefore, in this sixth embodiment, as shown in FIG. 8A, Si
O. The Ae wiring 64 is directly formed on the interlayer insulating film such as the film 65.
First, 50% of the SiO film 65 is
A polycrystalline Si film 66 having a thickness of approximately 0.05 mm is deposited. And A7 containing about 1% St! A film is deposited on the polycrystalline Si film 66, and these A6 films and the polycrystalline Si film 66
Pattern A7! The wiring 64 is formed.

Next, as shown in FIG. 8B, an SiO2 film 67, which is an interlayer insulating film, is deposited, and then a polycrystalline Si film 67 is deposited as shown in FIG. 8C.
The contact hole 7I reaching the film 66 is connected to the SiO film 67 and A.
The I2 wiring 64 is formed. Initially, the shape of the contact hole 71 was determined by using a CHh-based gas to form the SiO2 film 6.
Esoching 7 and then sequentially BCI! A7 exposed after switching to type 3 gas! The wiring 64 is etched.

Next, 8th 1. ) As shown in the figure, the contact hole 71 is filled with a W film 72 by selective CVD of W. In this case as well, since the W film 72 is deposited using the polycrystalline Si film 66 as a seed, the W film 72 and A 1' 5[! No AlF film is formed at the interface with the wire 64, and the contact resistance between the W film 72 and the 8L wiring 64 is low.

Note that the exposed surface of the A7+ wiring 64, which is the inner wall surface of the contact hole 71, is covered with a thin A20 natural oxide film.
3 film etc., selective CVD of W does not occur on the exposed surface of this An wiring 64. However, W's selection CVD
In order to reliably prevent this, the exposed surface of the Al wiring 64 may be nitrided after forming the contact hole 71, as in the case of the fifth embodiment.

FIG. 9 shows a modification of the sixth embodiment shown in FIG. That is, if the cross section of the AN wiring 64 is made convex as shown in FIG. 9, the W film 72 and the A
The contact resistance with the A wiring 64 is further reduced.

〔Effect of the invention〕

In the semiconductor memory according to the present invention, since the leakage current of the thin film transistor serving as a load element of the inverter is small, power consumption is low and reliability is high.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell according to a first embodiment of the present invention, FIGS. 2 and 3 are side sectional views of main parts of the first and second embodiments, respectively, and FIG. 4 is a circuit diagram of a memory cell according to a third embodiment. Fig. 5 is a side sectional view of the main part of the fourth embodiment, and Fig. 6 is a side sectional view of the main part of the fifth embodiment. 7 is a side sectional view of the main part of a modification of the fifth embodiment, FIG. 8 is a side sectional view of the main part of the sixth embodiment without sequentially showing the manufacturing process, and FIG. FIG. 7 is a side sectional view of a main part of a modification of the embodiment. In addition, in the codes used in the drawings, 1 1----------・---------Frisopflosoob l4, 1 5 -----------1---1-
Inverters 21, 2 2--1 load transistor 45-1--1 polycrystalline Si film. 19

Claims (1)

[Scope of Claims] A semiconductor memory in which a memory cell is configured using a flip-flop consisting of a pair of inverters, and a thin film transistor serves as a load element of the inverter, characterized in that the thin film transistor has a double gate structure. semiconductor memory.