JPH03151656A - Substrate for mounting semiconductor element - Google Patents

Substrate for mounting semiconductor element

Info

Publication number
JPH03151656A
JPH03151656A JP1291892A JP29189289A JPH03151656A JP H03151656 A JPH03151656 A JP H03151656A JP 1291892 A JP1291892 A JP 1291892A JP 29189289 A JP29189289 A JP 29189289A JP H03151656 A JPH03151656 A JP H03151656A
Authority
JP
Japan
Prior art keywords
semiconductor element
element mounting
mounting pad
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1291892A
Other languages
Japanese (ja)
Other versions
JPH0787225B2 (en
Inventor
Hiroyuki Otaguro
浩幸 太田黒
Masao Hosogai
正男 細貝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1291892A priority Critical patent/JPH0787225B2/en
Publication of JPH03151656A publication Critical patent/JPH03151656A/en
Publication of JPH0787225B2 publication Critical patent/JPH0787225B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To prevent short-circuiting failure between a semiconductor element mounting pad and a conductor layer by forming while shifting the position of an edge surface of an insulation layer opposing to a semiconductor element mounting pad and by providing a stage difference between insulation layers. CONSTITUTION:A semiconductor element mounting pad 6a is provided on a substrate 1, multilayer conductor layers 2a-2c and insulation layers 3a-3c are alternately laminated with this semiconductor element mounting pad 6a as the center, formation is made by shifting the position of an end face of the insulation layers 3a-3c opposing to this semiconductor element mounting pad 6a, and a stage difference is provided among the insulation layers 3a-3c. Thus, when a resist film is applied, space surrounded by the resist film, the end face of the insulation layers 3a-3c, and the surface of the insulation layer 3a-3c on the substrate 1 or directly below becomes nearly equal in any insulation layer 3a-3c so that the resist fully reaches this space, thus preventing a void from occurring easily. Thus, it becomes possible to prevent short-circuiting failure from occurring between the semiconductor element mounting pad 6a and the conductor layers 2a-2c.

Description

【発明の詳細な説明】 〔概 要〕 導体層と絶縁層とからなる多層構造の半導体素子実装用
基板の改良に関し、 絶縁層の形状の変更により、導体層と半導体素子搭載パ
ッドとの短絡障害の発生を防止することが可能となる半
導体素子実装用基板の提供を目的とし、 基板上に半導体素子搭載パッドを備え、該半導体素子搭
載パッドを中心として配設された多層の導体層と絶縁層
とからなる半導体素子実装用基板であって、前記半導体
素子搭載パッドに対向する前記絶縁層の端面の位置をず
らせて形成し、前記絶縁層相互間に段差を設けるよう構
成する。
[Detailed Description of the Invention] [Summary] Regarding the improvement of a semiconductor element mounting board with a multilayer structure consisting of a conductor layer and an insulating layer, a short circuit failure between the conductor layer and the semiconductor element mounting pad was caused by changing the shape of the insulating layer. With the aim of providing a substrate for mounting semiconductor elements that can prevent the occurrence of the A substrate for mounting a semiconductor element, which is formed by shifting the position of the end face of the insulating layer facing the semiconductor element mounting pad, and providing a step between the insulating layers.

〔産業上の利用分野〕[Industrial application field]

本発明は、導体層と絶縁層とからなる多層構造の半導体
素子実装用基板の改良に関するものである。
The present invention relates to an improvement of a semiconductor element mounting board having a multilayer structure consisting of a conductor layer and an insulating layer.

従来の半導体素子実装用基板においては多層構造の絶縁
層は相互間には段差を設けない、端面が一致する形状を
有しており、導体層の形成工程においてこの構造に起因
する短絡障害が発生している。
In conventional substrates for mounting semiconductor devices, the insulating layers of the multilayer structure have a shape in which the end surfaces coincide with each other without any steps between them, and short circuit failures due to this structure occur during the process of forming the conductor layer. are doing.

以上のような状況から製造工程における導体層間の短絡
障害の発生を防止することが可能な半導体素子実装用基
板が要望されている。
Under the above circumstances, there is a need for a substrate for mounting semiconductor elements that can prevent short-circuit failures between conductor layers during the manufacturing process.

〔従来の技術〕[Conventional technology]

従来の4個の半導体素子を搭載する半導体素子実装用基
板について第4図、第5図により詳細に説明する。
A conventional semiconductor element mounting board on which four semiconductor elements are mounted will be explained in detail with reference to FIGS. 4 and 5.

第4図は従来の半導体素子実装用基板の平面図であり、
第5図は第4図のB−B断面の中心より右部を示す図で
ある。
FIG. 4 is a plan view of a conventional semiconductor element mounting board.
FIG. 5 is a view showing the right part from the center of the BB cross section in FIG. 4.

第5図に示すように、基板11の所定の位置には半導体
素子搭載パッド16aが形成されており、この表面に半
導体素子6が固着されており、これを取り囲むように導
体層12a+ 12b+ 12cと絶縁層13a。
As shown in FIG. 5, a semiconductor element mounting pad 16a is formed at a predetermined position on the substrate 11, and a semiconductor element 6 is fixed to the surface of the pad 16a. Insulating layer 13a.

13b、 13cとが交互に積層して形成されている。13b and 13c are formed by stacking them alternately.

導体層間には絶縁層を貫通する接続ビア14a、 14
b、 14cが設けられて導体層間を接続しており、絶
縁層13cの表面には接続ビア14cと接続する部品パ
ッド15が設けられている。
Connection vias 14a, 14 passing through the insulating layer are provided between the conductor layers.
b, 14c are provided to connect the conductor layers, and component pads 15 are provided on the surface of the insulating layer 13c to be connected to the connection vias 14c.

絶縁層13a、 13b、 13cの半導体素子搭載パ
ッド16aと対向している端面ば図に示すように同一位
置に形成されているので、第4図の平面図においてはこ
の端面ば半導体素子搭載パッド16aを取り囲む四角形
を形成している。
Since the end faces of the insulating layers 13a, 13b, and 13c facing the semiconductor element mounting pad 16a are formed at the same position as shown in the figure, in the plan view of FIG. It forms a rectangle surrounding the .

このような半導体素子実装用基板の製造を行うにはまず
フォトリソグラフィー技術を用いて基板11の表面に半
導体素子搭載パッドi6a及び導体層12aを形成する
To manufacture such a substrate for mounting a semiconductor element, first, a semiconductor element mounting pad i6a and a conductor layer 12a are formed on the surface of the substrate 11 using photolithography technology.

ついで全面に絶縁層13aの材料となる膜Jl!、13
〜25μmのポリイミド等の薄膜を塗布形成し、フォト
リソグラフィー技術を用いて接続ビア14aを形成する
孔と所要絶縁部を形成し、めっきを行ってこの孔の中の
導体層12aの表面に金属膜を成長させて接続ビア14
aを形成する。
Then, a film Jl! which becomes the material of the insulating layer 13a is applied to the entire surface. , 13
A thin film of polyimide or the like with a thickness of ~25 μm is applied and formed, and a hole for forming the connection via 14a and the required insulation part are formed using photolithography technology, and plating is performed to form a metal film on the surface of the conductor layer 12a in the hole. Connect via 14 by growing
form a.

その後全面にレジスト膜を形成し、フォトリソグラフィ
ー技術を用いて導体層12bを形成する部分のレジスト
膜を除去し、めっきを行ってこの部分の絶縁層13aの
表面に金属膜を成長させて導体層12bを形成し、レジ
スト膜を除去する。
After that, a resist film is formed on the entire surface, and the resist film is removed in the part where the conductor layer 12b is to be formed using photolithography technology, and plating is performed to grow a metal film on the surface of the insulating layer 13a in this part to form the conductor layer. 12b is formed, and the resist film is removed.

この後、これらの工程を繰り返して順次接続ビア14b
、絶縁層13b、導体層12cを形成し、更に接続ビア
14c、絶縁層13C1部品パッド15を形成してゆき
、半導体素子実装用基板の製造が完了する。
After this, these steps are repeated to sequentially connect the connecting vias 14b.
, an insulating layer 13b and a conductor layer 12c are formed, and further a connecting via 14c, an insulating layer 13C1 and a component pad 15 are formed, thereby completing the manufacture of a substrate for mounting a semiconductor element.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上説明した従来の半導体素子実装用基板においては、
導体層と絶縁層を順次積層して形成してゆくのに伴い、
基板の表面と導体層或いは絶縁層の表面との段差が増加
すると、全面にレジスト膜を塗布した場合には第6図(
alに示すような導体層の端面と基板の表面とで囲まれ
る部分にレジストが充分に回り込まなくなり、ここに空
隙18aが生じるようになる。
In the conventional semiconductor element mounting substrate described above,
As conductive layers and insulating layers are successively laminated,
As the level difference between the surface of the substrate and the surface of the conductor layer or insulating layer increases, the difference in level between the surface of the substrate and the surface of the conductor layer or insulating layer increases, as shown in Fig. 6 (
The resist does not sufficiently wrap around the portion surrounded by the end face of the conductor layer and the surface of the substrate as shown by al, and a gap 18a is created here.

このような状態でレジストを硬化させるために加熱する
と、第6図fb)に示すように、上記の空隙の中の空気
が熱膨張し、このためレジスト膜1・8に亀裂が生じ、
絶縁層の表面に導体層、接続ビア或いは部品パッドをめ
っきにより形成する際に、この亀裂を通してめっきが行
われ、図示するように半導体素子搭載パッド16aと導
体層12aとが短絡する障害が発生ず葛という問題点が
あった。
When the resist is heated in such a state to harden it, the air in the voids expands thermally, as shown in FIG.
When forming a conductor layer, connection via, or component pad on the surface of an insulating layer by plating, plating is performed through this crack, and as shown in the figure, there is no problem of short circuit between the semiconductor element mounting pad 16a and the conductor layer 12a. There was a problem with kudzu.

本発明は簡単且つ容易に行うことができる絶縁層の形状
の変更により、導体層と半導体素子搭載パッドとの短絡
障害の発生を防止することが可能となる半導体素子実装
用基板の提供を目的としたものである。
An object of the present invention is to provide a substrate for mounting a semiconductor element, which can prevent short-circuit failure between a conductor layer and a pad for mounting a semiconductor element by changing the shape of an insulating layer, which can be done simply and easily. This is what I did.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体素子実装用基板は、基板上に半導体素子
搭載パッドを備え、この半導体素子搭載パッドを中心と
して配設された多層の導体層と絶縁層とからなる半導体
素子実装用基板であって、この半導体素子搭載パッドに
対向するこの絶縁層の端面の位置をずらせて形成し、こ
の絶縁層相互間に段差を設けるよう構成する。
The semiconductor element mounting board of the present invention is a semiconductor element mounting board comprising a semiconductor element mounting pad on the substrate, and a multilayer conductor layer and an insulating layer arranged around the semiconductor element mounting pad. The end faces of the insulating layers facing the semiconductor element mounting pads are formed to be shifted in position, and a step is provided between the insulating layers.

〔作用〕[Effect]

即ち本発明においては、基板上に半導体素子搭載パッド
を設け、この半導体素子搭載パッドを中心として多層の
導体層と絶縁層とを交互に積層して配設し、この半導体
素子搭載パッドに対向するこの絶縁層の端面の位置をず
らせて形成してこの絶縁層相互間に段差を設けるから、
レジスト膜を塗布した場合にレジスj・膜と、絶縁層の
端面と、基板の表面或いは直く下の絶縁層の表面とによ
り囲まれる空間がどの絶縁層の場合においてもほぼ同し
で小さくなるので、レシス1−を塗布した場合にレジス
トが充分にこの空間に回り込むので空隙が発生し難くな
り、レジスト膜硬化のための加熱時においても、この空
隙の空気の熱膨張によってレジスト膜に亀裂が生じなく
なり、めっき処理時においても半導体素子搭載パッドと
導体層との間に短絡障害が発生ずることを防止すること
が可能となる。
That is, in the present invention, a semiconductor element mounting pad is provided on a substrate, and a multilayer conductor layer and an insulating layer are alternately stacked and arranged around this semiconductor element mounting pad, and facing the semiconductor element mounting pad. Since the end faces of the insulating layers are formed at different positions to create a step between the insulating layers,
When a resist film is applied, the space surrounded by the resist film, the end face of the insulating layer, and the surface of the substrate or the surface of the insulating layer immediately below is almost the same and small regardless of the insulating layer. Therefore, when Resis 1- is applied, the resist wraps around this space sufficiently, making it difficult to form voids, and even during heating to harden the resist film, the thermal expansion of the air in these voids will cause cracks in the resist film. Therefore, it is possible to prevent short-circuit failure between the semiconductor element mounting pad and the conductor layer even during the plating process.

〔実施例〕〔Example〕

以下4個の半導体素子を搭載する本発明の一実施例につ
いて第1図〜第3図により詳細に説明する。
An embodiment of the present invention in which four semiconductor elements are mounted will be described in detail below with reference to FIGS. 1 to 3.

第1図は本発明の半導体素子実装用基板の平面図であり
、第2図は第1図のA−A断面の中心より布部を示す図
である。
FIG. 1 is a plan view of a substrate for mounting a semiconductor element according to the present invention, and FIG. 2 is a view showing a cloth portion from the center of the AA cross section in FIG. 1.

第2図に示すように、基板1の所定の位置には半導体素
子搭載パッド6aが形成されており、この表面に半導体
素子6が固着されており、これを取り囲むように導体層
2a、2b、2Cと絶縁層3a、3b、3cとが交互に
積層して形成されている。
As shown in FIG. 2, a semiconductor element mounting pad 6a is formed at a predetermined position on the substrate 1, and a semiconductor element 6 is fixed to the surface of the pad 6a. 2C and insulating layers 3a, 3b, and 3c are alternately stacked.

導体層間には絶縁層を貫通する接続ビア4a、4b4c
が設けられ、導体層間を接続しており、絶縁層3cの表
面には接続ビア4cと接続する部品パッド5が設けられ
ている。
Connection vias 4a, 4b4c penetrating the insulating layer are provided between the conductor layers.
are provided to connect the conductor layers, and component pads 5 are provided on the surface of the insulating layer 3c to connect to the connection vias 4c.

絶縁層3a、3b、3cの半導体素子搭載パッド6aと
対向している端面ば図に示すように上層にゆくに従って
半導体素子搭載パッド6aからの距離が遠くなるように
形成されているので、第2図の平面図においてはこの端
面ば半導体素子搭載パッド6aを取り囲む各種の四角形
を形成している。
The end faces of the insulating layers 3a, 3b, and 3c facing the semiconductor element mounting pad 6a are formed so that the distance from the semiconductor element mounting pad 6a increases as one goes to the upper layer, as shown in the figure. In the plan view of the figure, this end face forms various squares surrounding the semiconductor element mounting pad 6a.

このような半導体素子実装用基板の製造を行うにはまず
第3図(alに示すように、基板1の全表面に半導体素
子搭載パッド6a及び導体層2aの材料となる銅、アル
ミニウム或いは金の薄膜2を蒸着法により形成し、この
1llu2の全表面にレジスト膜7を形成する。
To manufacture such a substrate for mounting semiconductor elements, first, as shown in FIG. A thin film 2 is formed by a vapor deposition method, and a resist film 7 is formed on the entire surface of this 1llu2.

つぎにフォトリソグラフィー技術を用いてレジスト膜7
をパターニングし、不要なこれらの金属の薄膜をエツチ
ングにより除去した後、このレジスト膜7を除去して第
3図(blに示すように半導体素子搭載パッド6a及び
導体層2aを形成する。
Next, a resist film 7 is formed using photolithography technology.
After patterning and removing unnecessary metal thin films by etching, the resist film 7 is removed to form semiconductor element mounting pads 6a and conductor layers 2a as shown in FIG.

ついで第3図(C1に示すように、全面に絶縁層3aの
材料となる膜厚13〜25μmのポリイミド等の薄膜を
塗布形成し、フォトリソグラフィー技術を用いて接続ビ
ア4aを形成する孔と所要絶縁部を形成し、めっきを行
ってこの孔の底部の導体層2aの表面に金属膜を成長さ
せて接続ビア4aを形成する。
Next, as shown in FIG. 3 (C1), a thin film of polyimide or the like with a thickness of 13 to 25 μm, which will be the material of the insulating layer 3a, is coated on the entire surface, and holes and necessary holes for forming the connection vias 4a are formed using photolithography technology. An insulating portion is formed and plating is performed to grow a metal film on the surface of the conductor layer 2a at the bottom of the hole to form a connection via 4a.

その後第3図(dlに示すように、全面にレジスト膜8
を形成し、フォトリソグラフィー技術を用いて導体層2
bを形成する部分をパターニングし、導体層2bを形成
する部分のレジスト膜8を除去し、めっきを行ってこの
部分の絶縁層3aの表面に金属膜を成長させて導体層2
bを形成し、レジスト膜8を除去する。
After that, as shown in FIG.
A conductor layer 2 is formed using photolithography technology.
The resist film 8 is removed from the portion where the conductor layer 2b is to be formed, and a metal film is grown on the surface of the insulating layer 3a in this portion by plating.
b is formed, and the resist film 8 is removed.

この後、第3図(c+〜第3図(dlの工程を繰り返し
て順次接続ビア4b、絶縁層3b、導体層2cを形成し
、更に接続ビア4c、絶縁層3c、部品バッド5を形成
してゆき、半導体素子実装用基板の製造が完了する。
After this, the process from FIG. 3(c+) to FIG. 3(dl) is repeated to sequentially form the connecting via 4b, insulating layer 3b, and conductor layer 2c, and further forming the connecting via 4c, insulating layer 3c, and component pad 5. Finally, the manufacturing of the semiconductor element mounting board is completed.

本発明においては、第2図に示すように上記の絶縁層3
bの端面を絶縁層3aの端面よりも半導体素子搭載パッ
ド6aからの距離を遠くして形成し、更に絶縁層3cの
端面を絶縁層3bの端面よりも半導体素子搭載パッド6
aからの距離を遠くして形成して絶縁層相互の間に段差
を設けている。
In the present invention, as shown in FIG.
The end face of the insulating layer 3c is formed farther from the semiconductor element mounting pad 6a than the end face of the insulating layer 3b, and the end face of the insulating layer 3c is formed farther from the semiconductor element mounting pad 6a than the end face of the insulating layer 3b.
The insulating layers are formed at a large distance from a to provide a step between the insulating layers.

このように絶縁層相互の間に段差を設けると、レジスト
を塗布した場合にレジスト膜と、絶縁層の端面と、基板
の表面或いは直ぐ下の絶縁層の表面とにより囲まれる空
間がどの絶縁層の場合においてもほぼ同じで小さくなる
ので、レジストを塗布した場合にレジストが充分にこの
空間に回り込むので空隙が発生し難くなり、レジスト硬
化のための加熱時においても、この空隙の空気の熱膨張
0 によってレジスト膜に亀裂が生じなくなり、めっき処理
時においても半導体素子搭載パッドと導体層との間に短
絡障害が発生することを防止することが可能となる。
If a step is provided between the insulating layers in this way, when a resist is applied, the space surrounded by the resist film, the end face of the insulating layer, and the surface of the substrate or the surface of the insulating layer immediately below will be affected by which insulating layer. When the resist is applied, it will be almost the same and smaller, so when the resist is applied, the resist will fully wrap around this space, making it difficult to create voids, and even when heating to harden the resist, the thermal expansion of the air in these voids will 0 prevents cracks from forming in the resist film, making it possible to prevent short-circuit failures between the semiconductor element mounting pad and the conductor layer during plating processing.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、半導体
素子搭載パッドに対向する絶縁層の端面の位置をずらせ
て形成し、絶縁層相互の間に段差を設けた極めて簡単な
絶縁層の形状の変更により、半導体素子搭載パッドと導
体層との短絡障害を防止することが可能となる利点があ
り、著しい信顛性向上の効果が期待できる半導体素子実
装用基板の提供が可能である。
As is clear from the above description, according to the present invention, the insulating layer has an extremely simple shape in which the end face of the insulating layer facing the semiconductor element mounting pad is shifted in position and a step is provided between the insulating layers. By changing the above, it is possible to prevent a short-circuit failure between the semiconductor element mounting pad and the conductor layer, and it is possible to provide a substrate for mounting a semiconductor element, which can be expected to significantly improve reliability.

第4図は従来の半導体素子実装用基板の平面図、第5図
は第4図のB−B断面図、 第6図は従来の半導体素子実装用基板における問題点を
示す側断面図、 である。
FIG. 4 is a plan view of a conventional substrate for mounting semiconductor elements, FIG. be.

図において、 ■は基板、   2は薄膜、   2aは導体層、2b
は導体層、 2cは導体層、 3aは絶縁層、3bは絶
縁層、 3cは絶縁層、 4aは接続ビア、4bは接続
ビア、4cは接続ビア、 5は部品パッド、   6は半導体素子、6aは半導体
素子搭載パッド、 7はレジスト膜、   8はレジスト膜、を示す。
In the figure, ■ is the substrate, 2 is the thin film, 2a is the conductor layer, 2b
is a conductor layer, 2c is a conductor layer, 3a is an insulating layer, 3b is an insulating layer, 3c is an insulating layer, 4a is a connection via, 4b is a connection via, 4c is a connection via, 5 is a component pad, 6 is a semiconductor element, 6a indicates a semiconductor element mounting pad, 7 indicates a resist film, and 8 indicates a resist film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による一実施例の平面図、第2図は第1
図のA−A断面図、 第3図は本発明の半導体素子実装用基板の製造を工程順
に示す側断面図、
FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a plan view of an embodiment of the present invention.
3 is a side sectional view showing the manufacturing process of the semiconductor element mounting substrate of the present invention in the order of steps,

Claims (1)

【特許請求の範囲】  基板(1)上に半導体素子搭載パッド(6a)を備え
、該半導体素子搭載パッド(6a)を中心として配設さ
れた多層の導体層と絶縁層とからなる半導体素子実装用
基板であって、 前記半導体素子搭載パッド(6a)に対向する前記絶縁
層の端面の位置をずらせて形成し、前記絶縁層相互間に
段差を設けたことを特徴とする半導体素子実装用基板。
[Claims] A semiconductor element mounting comprising a semiconductor element mounting pad (6a) on a substrate (1), and a multilayer conductor layer and an insulating layer arranged around the semiconductor element mounting pad (6a). A substrate for mounting a semiconductor element, characterized in that the position of the end face of the insulating layer facing the semiconductor element mounting pad (6a) is shifted, and a step is provided between the insulating layers. .
JP1291892A 1989-11-08 1989-11-08 Substrate for mounting semiconductor elements Expired - Fee Related JPH0787225B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1291892A JPH0787225B2 (en) 1989-11-08 1989-11-08 Substrate for mounting semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1291892A JPH0787225B2 (en) 1989-11-08 1989-11-08 Substrate for mounting semiconductor elements

Publications (2)

Publication Number Publication Date
JPH03151656A true JPH03151656A (en) 1991-06-27
JPH0787225B2 JPH0787225B2 (en) 1995-09-20

Family

ID=17774804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1291892A Expired - Fee Related JPH0787225B2 (en) 1989-11-08 1989-11-08 Substrate for mounting semiconductor elements

Country Status (1)

Country Link
JP (1) JPH0787225B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5111499B2 (en) * 2007-05-14 2013-01-09 イビデン株式会社 Wiring board
JP5111500B2 (en) * 2007-05-14 2013-01-09 イビデン株式会社 Wiring board
JP5147843B2 (en) * 2007-07-13 2013-02-20 イビデン株式会社 Wiring board
US8648263B2 (en) 2007-05-17 2014-02-11 Ibiden Co., Ltd. Wiring board and method of manufacturing wiring board
US8669480B2 (en) 2007-05-17 2014-03-11 Ibiden Co., Ltd. Wiring board and method of manufacturing wiring board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868952A (en) * 1981-10-20 1983-04-25 Citizen Watch Co Ltd Electrode terminal for wiring connection
JPS63261862A (en) * 1987-04-20 1988-10-28 Sumitomo Electric Ind Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868952A (en) * 1981-10-20 1983-04-25 Citizen Watch Co Ltd Electrode terminal for wiring connection
JPS63261862A (en) * 1987-04-20 1988-10-28 Sumitomo Electric Ind Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5111499B2 (en) * 2007-05-14 2013-01-09 イビデン株式会社 Wiring board
JP5111500B2 (en) * 2007-05-14 2013-01-09 イビデン株式会社 Wiring board
US8648263B2 (en) 2007-05-17 2014-02-11 Ibiden Co., Ltd. Wiring board and method of manufacturing wiring board
US8669480B2 (en) 2007-05-17 2014-03-11 Ibiden Co., Ltd. Wiring board and method of manufacturing wiring board
JP5147843B2 (en) * 2007-07-13 2013-02-20 イビデン株式会社 Wiring board

Also Published As

Publication number Publication date
JPH0787225B2 (en) 1995-09-20

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