JPH0314265B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control signal detection device for a facsimile machine.

[Problems with conventional technology]

In conventional facsimile devices, the configuration shown in FIGS. 1 and 2 has been adopted as a device for detecting control signals (tone signals). That is, in the case of Fig. 1, the received signal input to the input terminal 1 is applied to the bandpass filter 2 that passes only the frequency to be detected, then rectified by the full-wave rectifier circuit 3, and this DC signal is integrated. A circuit 4 integrates the signal and applies it to a comparator 5, and when this signal exceeds the reference voltage level of a reference voltage source 6, a detection output signal is output to an output terminal 7. In the case of FIG. 2, the received signal is first binarized by the zero crossing signal circuit 8 and then added to the counter 9 as a pulse signal.
The number of pulses inputted within a predetermined time measured by 0 is counted, and this counting result is input to the judgment circuit 11 to determine whether the number of pulses counted by the counter 9 is within a predetermined number range. Make sure that it is in
As a result, a detection signal is output from the output terminal 7, assuming that the control signal of the target frequency has been detected.

However, according to the conventional control signal detection device shown in FIG. 1 and FIG. There is a possibility that an image signal is erroneously detected as a control signal and a detection output is generated, and this has the drawback of interfering with communication.

In order to solve the above-mentioned drawbacks, in the past, as in the control signal receiving device for facsimile described in Japanese Patent Application Laid-Open No. 52-25521, only when a specific frequency of the control signal is supplied during the input period of the phase signal. There is a device that detects a control signal by driving a timer circuit and, when the timer circuit reaches a predetermined time, overflows and outputs a detection signal. As in the facsimile system described above, the transmitting side provides a no-signal period for the image signal and transmits it to the receiving side, and the receiving side transmits a control signal during the no-signal period, so that the signal is not transmitted during the no-signal period. When detected, some devices detect the control signal by using the detected signal as a control signal from the receiving side.

However, according to the facsimile control signal receiving device disclosed in Japanese Unexamined Patent Publication No. 52-25521 mentioned above, the phase signal must be differentiated to drive the timer circuit, so the circuit configuration becomes complicated and the manufacturing cost increases. The problem is that it is expensive,
Furthermore, in the facsimile system described in Japanese Patent Application Laid-Open No. 51-30415, when transmitting an image signal, a no-signal period must be provided in addition to the phase signal period, so it takes time to transmit the image signal. In addition to this, when transmitting a control signal, the control signal can only be transmitted during the above-mentioned no-signal period, so it takes time to transmit the control signal, and therefore, there is a drawback that prompt signal transmission cannot be expected. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a facsimile machine that can reliably detect control signals, can quickly transmit and receive the control signals, and can reduce manufacturing costs with a simple circuit configuration. An object of the present invention is to provide a control signal detection device in a device.

[Structure of the invention]

The present invention provides a control system that includes a circuit that detects a control signal and generates an output, and a control circuit that operates this detection output generation circuit when receiving a control signal and stops the operation when receiving an image signal. The signal detection device achieves the above objectives.

〔Example〕

Examples of the present invention will be described in detail below.

FIG. 3 shows the first control signal detection device according to the present invention.
FIG. 4 is a timing chart illustrating its operation. In this embodiment, focusing on the fact that a carrier component is always sent to a certain position in the image signal for a certain period of time while receiving an image signal, a circuit is provided to detect this carrier component, and the circuit is controlled by this circuit. A detection output generation circuit 21 configured to control a signal detection output generation circuit detects a control signal and generates an output, and a carrier detection circuit 22 for controlling this circuit 21.
It becomes more.

The detection output generation circuit 21 includes a frequency detection circuit 23 that detects a control signal of a predetermined frequency, a counter 24 that measures the time during which this circuit 23 outputs a detection output, an AND circuit 25, and an OR circuit 26. It becomes more. The frequency detection circuit 23 includes:
A received signal A as shown in FIG. 4A is applied from the input terminal 1. This received signal A includes an image signal, a line synchronization signal for line synchronization inserted for each line of this image signal, and a control signal sent when there is no image signal or synchronization signal. Re,
Only when this received signal A has a frequency equal to the frequency of the control signal, the frequency detection circuit 23 outputs an output signal B as shown in FIG. A clock signal C as shown in FIG. 4C is applied to the clock terminal of the counter 24. This clock signal C has the same phase as the line synchronization signal of the received signal, and is at the L'' level during the period when the synchronization carrier exists. One input terminal of the OR circuit 26 is connected to the terminal 28.
A signal D as shown in FIG. 4D is added. The above-mentioned signal D is a signal indicating the internal state of the receiving facsimile device. When the signal D is at the "H" level, the device is in a state where it expects a control signal input, and when it is at the "L" level, the device is in a state where it expects the input of the image signal. It is in a state where it is expecting input. If the input of the control signal can be known on the receiving side according to the communication protocol, the counter 24 will overflow due to the "H" level signals B and D, and the input of the control signal cannot be known. In this case, the counter 24 is
overflows.

On the other hand, the carrier detection circuit 22 having an analog filter is connected to the input terminal 1 to receive the received signal A, and detects the carrier component of the line synchronization signal that is always sent to a certain position in the image signal for a certain period of time. Upon detection, a negative logic signal E as shown in FIG. 4(e) is output. That is, when the carrier detection circuit 22 extracts the carrier component of the line synchronization signal using an analog filter, it holds the extracted signal voltage for a period approximately equivalent to one cycle of line synchronization, and generates the signal E based on the inverted output of this holding voltage. I am trying to output it. This signal E is applied to the other input terminal of the OR circuit 26, and the output of the OR circuit 26 is applied to the other input terminal of the AND circuit 25. Therefore, as shown in FIG. 4, the AND circuit 25 maintains the "L" level during the period when the carrier component is present while receiving the image signal, and continuously maintains the "H" level while receiving the control signal. A signal F is output, and this signal F is applied to the enable terminal of the counter 24. The output signal B of the frequency detection circuit 23 is applied to the negative logic clear terminal of the counter 24 .

The counter 24 has its enable terminal 〓H”
When the number of pulses of the clock signal C reaches a predetermined number (N) after reaching the level, that is, after a predetermined time has elapsed since the received signal changed from an image signal to a control signal, When overflow occurs, the detection output G of the control signal as shown in Fig. 4
occurs.

The above is an explanation of the configuration and operation of the first embodiment of the present invention. According to such a configuration, even if a component of the same frequency as the control signal is received during image signal reception, it can be controlled. There is no possibility of false detection as a signal. Also, when receiving a control signal,
The output E of the carrier detection circuit 22 is continuously 〓H”
level, the counter 24 can measure the time during which the output of the frequency detection circuit 23 is active, and after a predetermined period of time has elapsed, the counter 24 can overflow and generate a detection output of the control signal.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6.

In FIG. 5, the detection output generating circuit 21 similar to that in FIG. 3 described above is provided, so this circuit 21
Although a detailed explanation of the configuration of the fifth part is omitted,
In the device shown in the figure, when a control signal having a frequency different from that of the carrier component is received, the signal H output from the demodulator is a beat signal as shown in FIG. A counter 31 is provided which counts beat signals in synchronization with a time slot for transmitting a carrier component whenever a signal is received, that is, a line synchronization signal period.
The output generation circuit 21 detects the output of this counter 31.
The counter 24 is controlled by inputting it to the OR circuit 26.

The output H of the demodulator is applied to the clock terminal of the counter 31 through the terminal 32, and the clock signal C is delayed by the inverter 33 and the polarity is inverted to the negative logic clear terminal. A clock signal generated by the clock signal is added to the clock signal. The overflow output of the counter 31 is applied to the other input terminal of the OR circuit 26 and also applied to the enable terminal of the counter 31 via an inverter 34.

Next, the operation of the apparatus shown in FIG. 5 will be explained with reference to the timing chart shown in FIG. The clock signal has the same phase as the line synchronization signal of the received signal, and is at the low level during the synchronization carrier period.
When the received signal is switched from an image signal to a control signal, the counter 31 receives a signal H as shown in FIG.
By counting a predetermined number of beat signals, an overflow output I as shown in FIG. 6 is output. This output signal I is cleared by the clock signal. This signal I passes through an OR circuit 26 and an AND circuit 25 to the counter 2.
4 is applied as a signal J as shown in FIG. That is, the delayed clock signal delays the clearing timing of the output signal I and accordingly delays the output timing of the signal J. Therefore, at the rising edge of the clock signal C applied to the counter 24, the counter 24 counts by 1 because the clock signal is output before it falls from ``H'' to ``L'', that is, before it is cleared. Do this. Therefore, the counter 24 generates a control signal detection output G as shown in FIG. 6 only when it receives a control signal for a period in which a predetermined number N of pulses are generated.

[Effects of the Invention] As explained above, according to the present invention, the detection signal output of the frequency detection circuit is timed in response to the carrier detection signal from the carrier signal detection circuit, and the control signal is detected based on the timing result. As a result, the control signal can be reliably detected and the control signal can be transmitted and received quickly, and the circuit configuration is simple with a carrier signal detection circuit, a frequency detection circuit, and a clock circuit. Manufacturing costs can be reduced, and communication between each facsimile device can be performed smoothly without any trouble.

[Brief explanation of the drawing]

1 and 2 are block circuit diagrams of a conventional control signal detection device, FIG. 3 is a circuit diagram of an embodiment of the control signal detection device according to the present invention, and FIG. 4 is a timing diagram showing signal waveforms of each part thereof. FIG. 5 is a circuit diagram of another embodiment of the control signal detection device according to the present invention, and FIG. 6 is a timing chart showing signal waveforms at various parts thereof. 21...Detection output generation circuit, 22...Carrier detection circuit, 23...Frequency detection circuit, 24, 31
... Counter, 25 ... OR circuit, 26 ... AND circuit, 33, 34 ... Inverter.

Claims (1)

[Scope of Claims] 1. In a control signal detection device in a facsimile device that detects a control signal from a received signal including an image signal and a control signal, detecting a carrier signal for synchronizing the image signal and detecting the image signal. an image signal detection means for outputting a detection signal indicating the presence or absence of the control signal; a frequency detection means for detecting a frequency equal to the frequency of the control signal and outputting a detection signal; and a clock circuit that clocks the output of the detection signal of the frequency detection means for a predetermined period of time and outputs a timing result when it is indicated that there is no image signal, and detects the control signal based on the timing result. A control signal detection device for a facsimile device, characterized in that: