JPH0216869A - Picture reducing circuit - Google Patents

Abstract

PURPOSE:To correctly set reduction rate by measuring previously the main scanning length of a transmitted and arriving picture, and reducing the picture by determining the reduction ratio according to this measured value. CONSTITUTION:When a main scanning enable signal on a signal line 4 and a picture clock on the signal line 5 are inputted to a main scanning length counter 1, the counter 1 counts the number of the picture signal clock on the signal line 5 for a period when the main scanning enable signal on the signal line 4 is valid, and outputs a count value to a reduction ratio decision circuit 2 by the signal line 8. The circuit 2 determines the reduction rate by the main scanning length counted value on the signal line 8 at the point of time of the termination of main scanning, and outputs it to a reducing circuit 3 through the signal line 9 and reduces the picture. Accordingly, the reduction rate is set automatically, and the picture can be outputted by the optimum reduction ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in an image reduction circuit, and particularly to detection of an image reduction ratio.

(Prior Art) Conventionally, in this type of image reduction circuit, if the size of the image is larger than the size of the printer or memory circuit that receives the image, the A method of receiving an image signal after setting a reduction ratio is known.

(Problems to be Solved by the Invention) The above-mentioned image reduction circuit requires operations to confirm the size of the image in advance and set the reduction ratio using a switch on the operation panel, and it is also possible to set the reduction ratio incorrectly due to an erroneous operation. The disadvantage is that it may be set

An object of the present invention is to measure the main scanning length of an incoming image, determine the reduction ratio based on the measured value, and reduce the image, thereby eliminating the above-mentioned drawbacks and making it possible to set the reduction ratio without error. An object of the present invention is to provide an image reduction circuit configured as follows.

(Means for Solving the Problems) An image reduction circuit according to the present invention includes a scanning length counter, a reduction ratio determination circuit, and a reduction circuit.

The main scanning length counter is for counting the main scanning length, and the reduction rate determination circuit is for determining the reduction rate according to the output of the main scanning length counter.

The reduction circuit performs reduction by thinning out the main scanning enable and image signal clock according to the determined reduction rate.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image reduction circuit according to the present invention.

In FIG. 1, 1 is a main scanning length counter, 2 is a reduction ratio determination circuit, and 3 is a reduction circuit.

When the main scanning enable on the signal line 4 and the image clock on the signal line S are input to the main scanning length counter 1, the reduction rate is set by the main scanning length counter 1 and the reduction rate determination circuit 2, and the reduction rate is set on the signal line 9. sent upwards. Therefore, the reduced main scan enable and image signal clock are outputted from the reduction circuit 3 onto the signal lines 6 and 7, respectively.

The main scanning length counter 1 counts the number of image signal clocks on the signal line s during the period in which the main scanning enable on the signal line 4 is valid, and outputs the count value to the reduction ratio determination circuit 2 via the signal line 8. The reduction ratio determination circuit 2 determines at the end of main scanning,
That is, at the point where the main scanning enable on the signal line 6 changes from valid to invalid, the reduction rate is determined by the main scanning length count value on the signal line 8, and is output to the reduction circuit 3 via the signal line 9 to perform the reduction. do.

FIG. 2 is a timing diagram showing operation waveforms when the reduction ratio is set to 50% in the image reduction circuit shown in FIG.

The image signal in Fig. 2 (a"l) is input to the main scanning counter 1 with the main scanning enable shown in Fig. 2 (b) and the image signal clock shown in Fig. 2 (e"), and the reduction ratio is determined. The reduction circuit 3 undergoes processing at a reduction rate of 50% according to the instructions from the circuit 2. After this, the main scan enable shown in FIG. 2(d) and the image signal clock shown in FIG. 2(e) are output from the reduction circuit 3. Here, as for the main scanning enable in FIGS. 2(b) and 2(d), H is disabled and L is enabled.

(Effects of the Invention) As explained above, the present invention counts the main scanning length of the image signal and automatically sets the reduction ratio according to that value, thereby eliminating the need to set the reduction ratio externally in advance. This has the effect of being able to output at the optimal reduction ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image reduction circuit according to the present invention. FIG. 2 is a timing diagram showing an example of operating waveforms of the image reduction circuit shown in FIG. 1. 1・e・Main scanning length counter 2・−・Reduction rate determination circuit 3・・Reduction circuits 4 to 9e・・Signal line

Claims (1)

[Claims] a main scanning length counter for counting the main scanning length; a reduction rate determination circuit for determining a reduction rate according to the output of the main scanning length counter; and a main scanning enable and control circuit according to the determined reduction rate. 1. An image reduction circuit comprising: a reduction circuit for performing reduction by thinning out an image signal clock.