JPS63292821A - Pulse cut-off detection circuit - Google Patents

Abstract

PURPOSE:To accurately detect the cut-off of a pulse, by stopping a count operation by a pulse signal cut-off detecting signal by opening a counter reset by an input pulse signal and performs the count operation when the input pulse signal is cut-off. CONSTITUTION:A count value is set on the counter 1 by a time TB which recognizes the cut-off of the pulse and a clock cycle (t). And when the pulse of '1' level is inputted within the time TB from a data input (b), the counter is reset. And when the data input (b) goes to '0' level, the reset state of the counter 1 is released, and a clock is inputted from a clock input (a) to the terminal C of the counter 1 via a NOR circuit 2. Thereby, the counter 1 starts the count of a pulse cut-off time. And when the count value arrives at a preset value, the output of the counter 1 goes to the '1' level, and a pulse cut-off detecting output (c) goes to the '1' level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse interruption detection circuit for detecting the presence or absence of an input pulse in a digital communication system.

[Conventional technology]

Conventionally, this type of pulse interruption detection circuit has been comprised of a monostable multivibrator, a capacitor, and a resistor. In a digital communication system, when a failure occurs, the receiving side becomes at a constant, continuous hello level. By detecting this, it becomes possible to detect the occurrence of a failure. Conventionally, a detection circuit having a configuration as shown in FIG. 2 has been employed.

In FIG. 2 showing an example of a conventional pulse break detection circuit,
d is an input terminal to which an input pulse signal is applied, an output terminal from which a Hiro pulse disconnection detection output is obtained, C is a capacitor, R is a resistor connected in series with this capacitor C, and this resistor R
The other end of the capacitor C is connected to the power supply +V, and the other end of the capacitor C is grounded.

In this monostable multivibrator 3, terminal A is connected to input terminal d, terminal TI is connected to the connection point between capacitor C and ground, and terminal TUB is connected to the connection point between capacitor C and resistor H. Connected to the dots.

In the circuit configured in this way, when the signal is input to the input terminal 4, the Q output of the monostable multivibrator 3 becomes %6 lebel by the time constant T determined by the capacitor C and the resistors R and K. . Then, when a pulse is input again during the time constant T, the Q output becomes the %O1 level for the time constant T from the input pulse. As a result, when the input pulse interval is within the time constant TA, the Q output of the monostable multivibrator-3 is 10.
When the level is not equal to the time constant Tm or more, the d output is 11
〃If the level is not correct, input pulse disconnection will be detected.

[Problem that the invention seeks to solve]

In the nine conventional pulse break detection circuits mentioned above, the time was set using the time constant of ACH, which was connected to a monostable multivibrator, so the time could not be set accurately due to the tolerance between the monostable multivibrator and CR.
Moreover, there was a problem that it could not be made into a gate array.

[Means for solving problems]

The pulse interruption detection circuit of the present invention includes a counter that is reset by an input pulse signal and performs a counting operation when the input pulse signal is interrupted, and a circuit that stops the counting operation in response to a pulse signal interruption detection signal. be.

[Function] In the present invention, a pulse interruption is detected by resetting the counter at the pulse input %1 level and counting the time of the pulse input %0 level.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulse interruption detection circuit according to the present invention.

In the figure, a indicates a clock input, b indicates a data input, and C indicates a pulse interruption detection output. 1 is a counter that is reset by an input pulse signal and counts when the input pulse signal is disconnected; 2 is a NOR circuit that receives clock input a and the q output of counter 1; It constitutes a circuit that stops operation.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the clock input a passes through the NOR circuit 2 and the counter
1 number and 4 inputs. Also, data human power is cow,
is input to the reset terminal R of the printer 1. and,
The pulse interruption detection output C is outputted from the terminal Q of the counter 1.

Here, a count value is set in advance in the counter 1. The count value is set by the time TI for recognizing pulse interruption and the clock cycle t.

Next, when a pulse of %1 level is input within the data input time TI, the counter is reset and the Q output of the counter 1 is up to the -ON level of 1. and,
When the data input reaches the %0 level, the counter 1 is released from the reset state, and the clock input a and the Schiff circuit 2 are reset.
A clock is input to the C terminal of the counter 1.

Thereby, counter 1 starts counting the pulse interruption time. When the count value reaches the above-mentioned set value, the Q output of the counter 1 becomes 11 levels, and the pulse break detection output C becomes the '1# level. At the same time, the Q output of the counter 1 and the pulse interruption detection output supplied to the other input terminal of the Schiff circuit 2 cause the counter 1 to
The clock input is fixed at the %OI level and the counting operation line is stopped. As a result, the Q output of the counter 1 remains in the pulse interruption detection state until the data output becomes 11 again until i outputs the %III level.

〔Effect of the invention〕

As explained above, according to the present invention, pulse input %1
Reset the calanter with the rubel and input the pulse 10
``By counting the time of the level, it is possible to detect a pulse interruption, and after detecting it, stop the clock input to the counter and stop the sikarant operation.
The pulse break output can be held until the data input level %1 is input again. Furthermore, by using a clock with a constant cycle, it is possible to suppress the pulse interruption detection time error to within the clock cycle. Therefore, compared to conventional circuits, it is possible to detect pulse interruptions more accurately, and since it is composed of digital circuits, it operates stably. The effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pulse break detection circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional pulse break detection circuit. 1.φ...Counter, 2...NOR circuit.

Claims (1)

[Claims] 1. A pulse interruption detection circuit comprising: a counter that is reset by an input pulse signal and performs a counting operation when the input pulse signal is interrupted; and a circuit that stops the counting operation in response to a pulse signal interruption detection signal.