JP2528133B2 - Bidirectional digital transmission system - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a bidirectional digital transmission device that mutually adjusts timings at the start of operation, when a frequency error of a master clock on the other side is detected, pull-in using only one pole side in a received pulse is performed. This is a system that suppresses frequency detection error by using solitary-like pulses with equal pulse intervals in the training pattern.

[Industrial applications]

The present invention relates to a bidirectional digital transmission system, and in particular,
The present invention relates to an input pulse control device of a timing recovery circuit of a bidirectional digital transmission device used for subscriber transmission in a digital integrated communication network or the like.

At the start of operation, the bidirectional digital transmission device sends a training pattern of several frames for training the line equalizer so that the timings of the transmission devices are adjusted with each other.

In this bidirectional digital transmission device, first, the frequency error from the master clock of the other side is detected, and thereafter, the frequency error is forcibly controlled to be reduced, and the frequency error is periodically arranged in the received signal sequence. It is desirable that the frequency error detection of the timing recovery circuit that corrects the phase difference with the pulse has few detection errors. Therefore, it is necessary to suppress the influence of the intersymbol interference and the asymmetry of the positive and negative pulses on the timing pulse as much as possible during the frequency error detection period.

[Conventional technology]

FIG. 6 is a block diagram of a timing recovery circuit on the receiving side of a conventional bidirectional digital transmission device, and FIG. 7 is a time chart showing the operation of FIG. 6, which is line equalizer output EO, comparator output CO, frame detection. Output FC, clock window pulse CW, phase correction position indication pulse CP from frame counter, input pulse controller output A, start signal S
T, the pull-in start signal CS from the convergence judgment circuit, and the convergence signal RD from the convergence judgment device correspond to the same symbols in FIG. 5, respectively.

In FIG. 6, 1 is a line equalizer, 4 is a DPLL circuit, 5
Is a master clock generator, 6 and 10 are 1/2 dividers, 7 is a selector, 8 is a correction circuit, 9 is a 1 / N divider, 11 is a phase comparator, 12 is a differentiation circuit, 13 is a comparator, Reference numeral 14 is an input pulse controller, 15 is a frame detector, 16 is a convergence determination circuit, 17 is a frame counter, and 18 is a frequency error detection counter.Hereafter, the same reference numerals denote the same functions throughout the drawings. To do.

In FIG. 6, the training pulses sent first for several frames are equalized by the line equalizer 1, and the training pulses shown in FIG.
Input to the comparator 13 with the bipolar pulse shown in EO,
It is converted into a unipolar pulse indicated by CO and input to the input pulse controller 14 and the frame detector 15.

The frame detector 15 detects a frame from the pulse CO and outputs a frame detection signal indicated by FC to the frame counter 17
And to the convergence determination circuit 16.

The clock window pulse CW from the convergence judgment circuit 16 is sent to the input pulse controller 14, and this pulse CW
When is at low level "L", the output CO of the comparator 13 is prohibited. That is, the training pulse and frame pulse indicated by TP in FIG. 7 are created by passing through this window. Also, a pulse indicated by CP indicating the position where the phase is corrected in one frame is sent from the frame counter 17 to the input pulse controller 14,
This pulse CP is the pulse TP and the input pulse controller 14
The pulse OR is taken inside and the pulse indicated by A is input to the DPLL circuit 4.

The operation of the DPLL circuit 4 is started by the start signal indicated by ST, and the phase of the input timing pulse and the regenerated clock from the 1 / N frequency divider 9 is input as indicated by the sign a in the phase signal indicated by Φ in FIG. Is compared and corrected by the convergence determiner 16 and the phase comparator 11, and if converged, the convergence determiner circuit issues a convergence signal indicated by c, and the phase correction is continued until the end of this frame (T shown in FIG. 7). ₁ , T ₂ period). This next frame (7th
During the period T ₃ and the free-running period indicated by waveform B in the figure), there is no input to the DPLL circuit 4, so no phase correction is performed, and therefore the phase signal Φ in FIG. The error occurs at the end of this frame. In the next frame (T ₄ period shown in FIG. 7), pull-in is started,
The correction for correcting the phase error θ is performed by the training pulse (N ₁ period shown in FIG. 7).

At the start of the pull-in, the convergence determination circuit 16 sends a pull-in start signal indicated by CS to the frequency error detection counter 18, and at the time of convergence, a converged signal indicated by RD is sent to the frequency error detection counter 18 and the frame counter 17.

The frequency error detection counter 18 counts the number of pulses N ₁ necessary for correcting the phase error θ by this.
If there are four, for example, this value is sent to the frame counter 17 that is counting frames. In the following frames (the period of T ₄ , T ₅ ... In FIG. 7), one frame such as 1,2,3,4 for the pulse A is about (4 + 1)
The frame counter 17 sends the phase correction position signal pulse CP to the phase comparator 11 and the input pulse controller 14 at the equally divided positions, and according to the signal PL forcibly advanced or delayed by the convergence determination circuit 16, the seventh As shown by the phase signal Φ in the figure, 4
The phase correction is performed in the direction in which the phase error is corrected separately.

The frame pulse in the comparator output CO sent from the comparator 13 to the input pulse controller 14 is detected by the clock window pulse CW, the phase is compared by the phase comparator 11 via the differentiating circuit 12, and the result is corrected by the correction circuit. 8
By inputting into the input, the phase correction is performed with the received signal as a reference.

FIG. 8 shows the circuit configuration of the conventional input pulse controller 14, and FIG. 9 shows its time chart. In the figure, 12 is a differentiating circuit, 21 and 22 are comparators, and 23 and 25 are OR.
Reference numeral 24 denotes an AND circuit.

The output [received pulse] EO of the bipolar line equalizer 1 shown by EO in FIG. 9 is input to each of the + input of the comparator 21 and the-input of the comparator 22, and the comparator 21 The − input and the + input of the comparator 22 are supplied with a reference signal (slice level) for slicing at the 50% position of each pulse. The outputs of the comparators 21 and 22 are input to the OR circuit 23, and the output CO of the OR circuit 23 is input to one input of the AND circuit 24.

The clock window pulse CW is input to the other input of the AND circuit 24, and the output of the AND circuit 24 is input to the OR circuit 25. The insertion pulse CP for reducing the frequency error is input to the other input of the OR circuit 25, and the output of the OR circuit 25 is input to the differentiating circuit 12. The master clock SC of the DPLL circuit 4 is input to the differentiating circuit 12.

In the input pulse controller 14 configured as described above, as shown in FIG. 9, the bipolar reception pulse EO input to the comparators 21 and 22 is converted into the unipolar pulse CO by the OR circuit 23. It is later input to the AND circuit 24, and becomes the signal TP and is input to the OR circuit 25 only while the clock window pulse CW is at the high level “H”. In the OR circuit 25, this signal TP
And the insertion pulse CP for reducing the frequency error, and the pulse A is input to the differentiating circuit 12.

The differentiating circuit 12 differentiates the pulse A with the master clock SC and outputs the differentiated pulse TC, as shown in FIG. 9 (1). As described above, in the conventional circuit, the pulse CO is composed of a pulse sequence including bipolar pulse components obtained by slicing the bipolar received pulse EO with the comparators 21 and 22.

[Problems to be solved by the invention]

However, the training pattern of the timing reproduction circuit requires a pulse sequence at equal intervals, but in the conventional technique, the output CO of the OR circuit 23 is the OR of the + pole reception pulse and the − pole reception pulse of the reception pulse EO. It is a pulse sequence containing the received signals of both polarities, and the OR circuit 23 as shown in Fig. 10 due to the asymmetry of the positive and negative waveforms of the output waveform of the line equalizer and the ± absolute level error of the comparator slice level.
Since the + pole reception pulse and the − pole reception pulse of the output signal CO of are reproduced as different pulses, it is possible to reproduce a pulse sequence at equal intervals for accurately extracting the transmission clock frequency component of the partner transmission device. Not possible (M ≠ in Fig. 10 (3)
N), there is a problem that the frequency error cannot be detected accurately.

Also, during this frequency error detection period, if intersymbol interference occurs in the reception waveform of the transmission side training pattern,
Similar to the above, the + pole reception pulse and the − pole reception pulse of the output signal CO of the OR circuit 23 are reproduced as different pulses, which is a problem.

The present invention solves the problem of the input pulse controller of the conventional timing reproduction circuit described above, and inputs a unipolar received signal pulse train during the frequency error detection period of the timing reproduction circuit to keep the training pattern at equal intervals. An object of the present invention is to provide a bidirectional digital transmission system that can suppress detection of an error in frequency error detection due to intersymbol interference and positive / negative pulses by using a pulse sequence during a frequency error detection period.

[Means for solving problems]

A principle block diagram of a system of the present invention which solves the above problems is shown in FIG.

In the figure, 20 is a unipolar pulse output means for detecting a unipolar pulse from a bipolar received signal from the opposite bidirectional digital transmission device, and outputting the detection result in accordance with either polarity, 23 is OR logic means for taking an OR logic of the respective unipolar pulses, 30 outputs a unipolar pulse from the unipolar pulse output means (20) when a signal indicating a period for detecting a frequency error is input, Selection means (30) for outputting bipolar pulses from the OR logic means (23) when not input, 100 is a training pattern generation means for generating a solitary wave pattern having an equal pulse interval, 101 is a training It is a selector that switches between a pattern and transmission data. On the transmission side, the output of the training pattern generation means 100 is input to the selector 101, and the output of the training pattern generation means is used as the transmission data during the frequency error detection period by the training pattern transmission start signal and the training pattern transmission end signal, and the training pattern At the end of transmission, the transmission data is used as the transmission data. By this means, the timing reproduction circuit can accurately detect the frequency error and perform accurate timing reproduction.

[Work]

The unipolar pulse output means 20 splits the ambipolar received signal into two, detects unipolar pulses from each and outputs them in accordance with either polarity, and the OR logic means 23 outputs the unipolar pulse output. Taking each OR logic of the output of the means 20, the selection means 30 outputs a unipolar pulse from the unipolar pulse output means 20 when a signal indicating a period for detecting a frequency error is input, and when not input, A bipolar pulse is output from the OR logic means 23. On the transmission side, the output of the training pattern generation means 100 is input to the selector 101, and the output of the training pattern generation means is used as the transmission data during the frequency error detection period by the training pattern transmission start signal and the training pattern transmission end signal, and the training pattern At the end of transmission, the transmission data is used as the transmission data. As a result, a training pattern having unipolar equal pulse intervals is obtained during the frequency error detection period, and the transmission clock frequency component of the transmission device on the transmission side can be accurately extracted. A frequency error is detected, and the detection result controls the frequency error to be reduced. Then, the phase difference is corrected by the pulses periodically arranged in the received signal sequence.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the circuit configuration of the system of the present invention, and FIG. 3 (a) is a time chart showing its operation. In FIG. 2, reference numeral 12 denotes a differentiating circuit, the unipolar pulse extracting means 20 includes comparators 21 and 22, and OR
The logic means 23 comprises an OR circuit, and the selection means 30 comprises a NOT circuit 31 and three NAND circuits 32, 33 and 34. 24 is AND
The circuit, 25 is an OR circuit. These are configurations on the receiving side, and a training pattern generator 100 and a selector 101 are provided on the transmitting side. The training pattern generating means 100 on the transmitting side is the training pattern in which the address counter 55 and the training pattern are written.
It consists of ROM56.

The training pattern ROM 56, FIG. 3 (1) equidistant pulse intervals to generate a solitary wave waveform shown in the transmission data SD _{(K 1 = K 2 = K} 3 = K 4 = K 5 = K 6 = K ₇ ), a solitary wave pattern as shown in FIG. 3 (2) is written. In the address counter 55, the frame cycle synchronizing address is generated by the frame cycle signal and the transmission clock,
It is input to the training pattern ROM 56 to generate a training pattern. The training pattern is sent from the training pattern ROM56 to one of the inputs of NAND57,
When the training period signal TST is at "H" level, NAND59
Output from Also, the training period signal TST is "L"
In case of level, transmission data is selected and output from NAND59. The transmission data SD output in this way is transmitted by the transmission unit 10
2 is sent to the receiving side transmission device. In the receiving unit 60 of the receiving side transmission device that receives this transmission signal, the line equalizer 1
As a result, the reception pulse EO shown in FIG. 2 is generated and input to the comparators 21 and 22.

In the comparators 21 and 22, the slice level of 50% of the received pulse amplitude is input in addition to the received pulse EO, and the slice of the received pulse EO is sliced at the slice level of 50% as shown in Fig. 3 (1). Pulse is output.

The output pulses of the comparators 21 and 22 are input to the OR circuit 23, and the positive and negative slice pulses of the reception pulse EO are input to the NAND 32. Further, the slice pulse on the one pole side is input to the NAND 33.

In the selection means 30 shown in FIG. 2, the input OR circuit 23 is input.
When the signal RD is “H” level, the output of the comparator 21 is selected, and when the signal RD is “L” level, the output of the OR23 is selected by the signal RD indicating the frequency error detection period between the output of the It is configured to be output from the NAND34. In particular, during the frequency error detection period when the signal RD is at "H" level, the training period signal TST of the transmission device on the transmitting side is also "H".
The received pulse EO, which is a level and has a solitary wave pattern (FIG. 3 (2)) with evenly spaced pulse intervals, is compared with the comparator 20,2.
Entered in 1.

The NAND output 34 generated in this way is input to the AND 24, ANDed with the clock window pulse CW, and output as the timing pulse TP.

The OR circuit 25 ORs the signal TP and the insertion pulse CP for reducing the frequency error, and the ORed pulse A is input to the differentiating circuit 12. This insertion pulse CP is
It is a pulse that indicates the position where the phase should be corrected independently by the frame counter 17 shown in FIG. 6, and is at a low level during the frequency error detection period, which affects the output of the AND circuit 24 during the frequency error detection period. Absent. After this, the differentiation circuit 12 is the ninth
As shown in FIG. 1A, the pulse A is differentiated by the master clock SC and the differentiated pulse TC is output.

The output TC of the differentiating circuit 12 is the phase comparator 11 shown in FIG.
It is sent to the convergence determination circuit 16 and the frequency error detection counter 18.

Next, the frequency determination circuit 16 will be described. FIG. 4 is a block diagram of an example of the convergence determination circuit 16, and FIG. 5 is a time chart of FIG. 4, where ST, FC, RD, CW, RC, TC, PL, a, b, c, d, e are the Two
Corresponding to the same symbols in the figure, the following signal waveforms are shown.

ST: Start signal FC: Frame detection pulse RD: Convergence signal CW: Clock window pulse RC: Reproduced clock TC: Differentiator 12 output a: FF42 output b: FF43 output c: FF49 output e: Exclusive OR Output of circuit 44 42, 43, 45, 49 to 51 are FFs (flip-flops), 44
Is an exclusive OR circuit, 46, 48, 52, 54 are AND circuits, 53 is an OR circuit, and 47 is a NOT circuit.

Each part of the convergence determiner 16 shown in FIG. 4 has a start signal ST, a frame detection pulse FC, a reproduction clock RC shown in FIG.
And the output TC of the differentiating circuit 12 is input.

The reproduction clock RC is input to FF42, and the output TC of the differentiation circuit 12
When the output TC of the differentiating circuit 12 advances from the reproduction clock RC as shown in FIG. 5 (2), the output a becomes high level "H", and when it is delayed, it becomes low level "L".
Input to the FF43 and the exclusive OR circuit 44, the output signal b is delayed by one step in the FF43, input to the exclusive OR circuit 44, and the exclusive OR is taken. And input to FF45,49.

In the FF45, this signal is output to the NOT circuit 4 of the output TC of the differentiation circuit 12.
When tapped with the signal inverted in 7, it becomes a signal indicated by c,
By changing from the low level “L” to the high level “H”, the pull-in convergence signal shown by the waveform c in FIGS. 5 and 7 is issued,
Enter it in FF50.

In FF29, the frequency error detection counter 18 of FIG.
Until the count start signal CS is output from 51 [two points of the waveform CW in FIG. 5], it is cleared by this signal, and thereafter it operates.

In this operation, as shown in FIG. 5 (3), the output of the exclusive OR circuit 44, which is the exclusive OR of the signals shown in the waveforms a and b, is tapped with the signal TC, and the reproduction clock shown with RC advances. A convergence signal RD indicating convergence is output and output to the frequency error detection counter 18 in FIG. 6 to stop counting.

The inverted output of FF59 is input to AND circuit 52 and
It is input to the circuit 46 and the output TC of the differentiating circuit 12 thereafter is prohibited.

In this case, the output a in FIG. 4, that is, the signal PL, is at the low level "L" while the reproduction clock RC is delayed, and becomes the high level "H" as the reproduction clock RC is delayed. At the time, it is an instruction to advance or delay the phase.

The signal shown in waveform c input to FF50 is beaten at the frame detection pulse FC as shown in Fig. 5 (1), and this output is input to FF51, and at the frame detection pulse FC c. When it is hit, it becomes a high-level "H" signal CS, which causes the frequency counter 18 in FIG. 6 to start counting.

Further, this is input to the AND circuit 52, becomes a second pulse of the pulse CW, and is input to the OR circuit 53.

The outputs of the frame detection pulses FC and FF50 are input to the OR circuit 53, which are ORed and input to the AND circuit 54. The start signal ST is input to the AND circuit 54, and its output becomes the clock window pulse CW in FIG. 5 (1), which is input to the input pulse controller 14 in FIG. 6 to limit the input pulse.

EFFECTS OF THE INVENTION According to the present invention, a unipolar received signal pulse train is input during the frequency error detection period of the timing recovery circuit, and evenly spaced pulses are received in the received signal pulse sequence (training pattern) during the frequency error detection period. By using the solitary wave pattern having intervals, there is an effect that intersymbol interference is eliminated during the frequency error detection period, and error detection of frequency error detection can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the circuit configuration of an embodiment of the system of the present invention, and FIG.
FIG. 1A is a time chart showing the operation of FIG.
FIG. (2) is an explanatory view of a solitary wave pattern, FIG. 4 is a block diagram of an example of a convergence determination circuit, and FIGS. 5 (1), (2),
(3) is a time chart showing the operation of FIG. 4, FIG. 6 is a block diagram of an embodiment of a conventional timing reproduction circuit,
FIG. 7 is a time chart showing the operation of the conventional example of FIG.
FIG. 8 is a circuit configuration diagram of a conventional input pulse controller, FIG. 9 is a time chart diagram showing the operation of FIG. 8, and FIGS. 10 (1), (2), and (3) are conventional input control pulses. It is an operation | movement waveform diagram of an apparatus. 1 ... Line equalizer, 4 ... DPLL circuit, 5 ... Master clock generator, 11 ... Phase comparator, 12 ... Differentiation circuit, 14 ... Input pulse controller, 15 ... Frame detector, 16 ...
… Convergence determiner, 17 …… Frame counter, 18 …… Frequency error detection counter.

Front page continuation (72) Inventor Seiichi Yamano 3-9-11 Midoricho, Musashino City, Tokyo Nihon Telegraph and Telephone Corporation, Research Institute for Communication Networks No. 1 (56) Reference JP-A-61-224530 (JP, A)

Claims (1)

(57) [Claims] 1. A bidirectional digital transmission device having a transmission device equipped with a transmission means (102) and a transmission device equipped with a reception means (60), wherein a bipolar reception signal from a bidirectional digital transmission device facing each other. A unipolar pulse from each of the unipolar pulses and outputs the detection result according to either polarity, and a unipolar pulse output means (20), and an OR logic means (23) that takes the OR logic of the unipolar pulses. ) And a signal indicating the period for detecting the frequency error is input, a unipolar pulse is output from the unipolar pulse output means (20), and when not input, the OR logic means (2
3) is provided with a selection means (30) for outputting bipolar pulses, and during the period of frequency error detection, the transmission device on the transmission side uses the training pattern generation means (100) to isolate the isolated wave with pulse intervals. The frequency error between the output of the selection means (30) and the reproduced clock is detected by transmitting the pulse of the dynamic pattern, the frequency error is controlled to be reduced, and the frequency error is periodically arranged in the received signal sequence. Bidirectional digital transmission system that uses pulse to correct the phase difference.