JPH05211526A - Dc center level automatic correction circuit for base band signal - Google Patents

Abstract

PURPOSE:To provide a digital signal transmission system with high quality by utilizing that a bit synchronizing signal with repetitive 1, 0 is in existence at a head of a packet so as to detect a DC center level thereby forming an automatic correction circuit for a DC center level with high accuracy. CONSTITUTION:A reference voltage appears on an output line 24 of a changeover device 8 in the initial state. When a 1, 0 detector 10 detects a '1, 0' level, an output 22 is obtained from a gate circuit 5 based on a gate pulse 19 and an integration device 6 is operated by a packet length pulse 15. Thereafter, the output 23 keeps an integration voltage till the end of a packet and a reference voltage from a reference voltage generator 13 is added to obtain an output 7. A changeover device 8 is turned to the position of the output of an adder 7 with a control pulse 20 to apply a signal 24 to a subtractor 3. Since the signal 24 after changeover reaches a DC center level being an output of the subtractor 3 obtained before changeover, an output of the subtractor 3 is corrected to a bit synchronizing signal having the DC center level automatically equal to the reference voltage for a period when the DC level is subtracted from the input signal and is kept.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to automatic correction of a DC center level of a baseband signal obtained by demodulating a frequency shift keying signal, or automatic correction of a DC center level of a received baseband signal of the baseband transmission system. It is a thing.

[0002]

2. Description of the Related Art A direct frequency shift keying (hereinafter abbreviated as direct FSK) system corresponds to a frequency shift of increasing or decreasing the frequency of a carrier wave to "1" or "0" of a digital signal. In this method, a digital signal is transmitted. Therefore, normally, on the receiving side, the frequency of the received wave is converted so that the carrier frequency becomes the center of the frequency discriminator, and the discriminator output voltage when the center frequency is applied is used as the reference voltage, and it is either positive or negative from this reference voltage. Depending on whether the digital signal is "1" or "0". Therefore, the accuracy and stability of the carrier frequency on the transmitting side, the frequency accuracy and stability of the local carrier for frequency conversion on the receiving side, the frequency accuracy and stability of the center frequency of the frequency discriminator are all related to the fluctuation of the reference voltage. They are equivalent, which leads to an increase in the error code rate at the time of code detection on the receiving side. Furthermore, in the case of multi-level modulation such as 4-level FSK, it is necessary to provide a plurality of reference voltages closer to each other than in the case of binary level, and therefore it is necessary to further improve the frequency accuracy and stability of each section. There is.

[0003]

Therefore, on the receiving side, AFC (automatic frequency control) is usually used so that the output signal of the frequency discriminator is taken out with the reference voltage as the DC center level. However, if the baseband digital signal is an NRZ (Non Return to Zero) code or the like, the signal contains a DC component, and this DC level fluctuates according to the content of the code. It is difficult to accurately detect the DC level corresponding to the center frequency even if the averaging is performed. Therefore, it is difficult to perform an accurate and stable correction operation by the AFC controlled based on the detected DC level. The present invention provides a DC center level of a baseband signal that can realize demodulation of a low-cost, high-performance frequency shift keying signal without particularly improving the frequency accuracy and stability of each part of the transceiver. It is intended to provide an automatic correction circuit.

[0004]

In order to detect a code error due to transmission, it is usually necessary to transmit a digital signal by 128
Byte to 1024 bytes long (102 for 8-bit code)
A packet (also referred to as burst) type signal divided into about 4 bits to 8192 bits is used. At the beginning of this packet, in a local area radio or the like, several tens of synchronization bits are transmitted by alternately repeating "1" and "0" in order to perform clock reproduction on the receiving side. The DC center level automatic correction circuit of the baseband signal according to the present invention integrates the DC level of the received baseband signal for a time of at least 2 bits of "1,0" among the synchronization bits or an integral multiple of this time. The DC center level is detected by this, and the integrated output is held throughout the packet section, and the center level is corrected using this integrated output so that it is always corrected to an accurate DC center level for each packet. There is.

[0005]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is an example of the structure of a packet signal. At the beginning of the packet, first, a bit synchronization code indicated by A is sent for about several bytes (tens of bits). This signal is usually composed of alternating repetitions of "1" and "0",
It is used for clock recovery to correctly recognize the code that follows. Since the repetitive signal of "1" and "0" is transmitted with band limitation, it is almost a sine wave (2400H when the data rate is 4800 bps) on the receiving side.
z), and if there is a frequency error with respect to the regular frequency in each part of the transceiver, a DC component having a level value corresponding to this frequency error will be superimposed on this sine wave.
Therefore, if only the DC component is detected from the sine wave on which the DC component is superposed, the magnitude of the frequency error is detected, and this error component is held through the packet section below and the error component is inserted. If it is subtracted, the superimposed DC component can be canceled to reproduce the baseband signal having the correct DC center level.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. In FIG. 1, 1 is an input terminal for a demodulated baseband signal added from the output of a frequency discriminator, 2 is an output terminal for a baseband signal whose DC center level is corrected, 3 is a subtractor, 4 is a DC center level detection Circuit, 5 is a gate circuit, 6 is an integrator, 7 is an adder, 8 is a switcher, 9 is a control pulse generator, 10 is a "1,0" detector, and 11 is a reference oscillator that outputs an output wave of a reference frequency. , 12 is a packet length setting device, 13 is a reference voltage generator, 14 is an output line of the "1,0" detector 10, 15 is an output line of the packet length setting device 12, and 16 and 17 are output lines of the reference oscillator 11. ,
18 is "1,0" in the output line of the control pulse generator 9.
The control line of the detector 10, 19 is the control line of the gate circuit 5 among the outputs of the control pulse generator 9, 20 is the control line of the switcher 8, 21 is the output line of the subtractor 3,
Reference numeral 22 is an output line of the gate circuit 5, 23 is an output line of the integrator 6, and 24 is an output line of the switch 8.

The bit cycle signal, which is a demodulated baseband signal applied to the input terminal 1, has a DC center level of 1.0 V when there is no frequency error in each part of the transceiver. , As shown in FIG. The dotted line shows the case where there is no frequency error, and the solid line shows the case where the frequency error is demodulated as + Δ. The reference voltage generator 13 is set to the same voltage as the DC center level when there is no frequency error (1.0 V in this case), and this voltage is output to the output line 24 of the switch 8 in the initial state. Is appearing. Therefore, the output line 21 of the subtractor 3 outputs a sine wave on which the DC level + Δ is superimposed. The DC center level detection circuit 4 outputs "1," from such a signal.
The operation is started by detecting "0". Since this is a repetitive signal, it goes without saying that "0, 1" may be detected.

The most reliable method for detecting "1,0" is a method by Fourier analysis as shown in FIG. In the circuit diagram of the “1,0” detector 10 shown in FIG.
5, 26 are multipliers, 27, 28 are gate circuits, 29, 3
0 is an integrator, 31, 32 are squarers, 33 is an adder, 34
Is a comparator, 35 is a reference voltage generator, 36 is a gate circuit,
37 is a pulse generator. This "1,0" detector 10
Is controlled by the outputs 16 and 17 of the reference oscillator 11, the output 18 of the control pulse generator 9 and the output 15 of the packet length setting device 12, so that for convenience of explanation, the “1,0” detector 10 and the control pulse generator are generated. The operations of the device 9 and the packet length setting device 12 will be collectively described with reference to FIG.

The respective waveforms 14 to 18 in FIG. 5 show the waveforms of the input and output lines of the control pulse generator 9 and the packet length setting device 12. Hereinafter, the number of each line is used as a waveform or voltage of that number. That is, 14 is a "1,0" detection pulse applied from the "1,0" detector 10, 15 is a packet length pulse output from the packet length setter 12 by the pulse 14, and 16 and 17 are output from the reference oscillator 11. Two reference signals having a 90 ° phase difference, the frequency of which is 2400 Hz when the data transmission rate is 4800 bps (hereinafter, the data transmission rate is 4800 bps).
ps is taken as an example), 18 is the reference signal 16 is 2
The pulse is divided by 1 and the pulse length is 1/240.
0 seconds. The outputs 25 and 26 are the multipliers 2 of FIG.
Output waveforms 5 and 26, outputs 27 and 28 are output waveforms of the gate circuits 27 and 28, respectively, and outputs 29 and 30 are output waveforms of the integrators 29 and 30, respectively. Since the multiplication-integration operation is nothing but the phase detection operation, as shown in FIG.
The multiplication of 1 and 16 results in the output 26 and 21 and 17 as the output 25. Output 26 is gated at output 18 to output 28 and output 25 is gated at output 18 to output 27.
Becomes Output 28 is integrated into output 30 and output 27 is integrated into output 29.

Since the above operation is an operation for obtaining each component of two orthogonal axes, in order to obtain an absolute value, that is, an amplitude from these two components, an operation of (X ² + Y ² ) ^1/2 is performed. However, since the amplitude of the sine wave that is the bit synchronization signal does not fluctuate so much, it is not necessary to obtain the square root, and as shown in FIG. In the comparator 34, a window comparison is performed to determine whether the voltage is between the two reference voltages provided by the reference voltage generator 35. If the added voltage is within this window, the output of the comparator 34 is generated.
By sampling with the output pulse of the pulse generator 37, the "1,0" detection pulse 14 shown in FIG. 5 is obtained. The pulse generator 37 is configured such that once the sampling pulse is output, it is not generated in the packet thereafter. In addition, the pulse generator 37 is
Pulses 19 and 20 shown in FIG. 5 are generated by the inversion pulse of the 0 ″ detection pulse 14, the packet length pulse 15, and the pulse 18. The pulse length of the pulse 19 is (1/240).
0) seconds and pulse 20, like pulse 15, lasts until the end of the packet.

Therefore, the gate circuit 5, the integrator 6, and the integrator 6 shown in FIG.
The outputs of the adder 7 and the switching unit 8 are shown in FIG.
become that way. That is, "1,0" is detected within the section G shown at the bottom of FIG. 6, and when "1,0" is detected, the gate pulse 19 outputs the waveform 22 and the packet length pulse 15 Since the integrator 6 is operated by this, a waveform as shown by 23 is obtained at the output, and thereafter, this integrated voltage is held until the packet is completed. A reference voltage is added to the integrated voltage by the reference voltage generator 13 to form a waveform shown as an output 7,
The switch 8 outputs the reference voltage by the control pulse 20 until the section H ends, and when it enters the section I, it is switched to the output side of the adder 7, and the waveform shown by 24 is applied to the subtractor 3.
As is clear from the above description, there is no problem even if the gate pulses 18 and 19 are selected to have an integral multiple of (1/2400) seconds. Since the voltage of 24 in the section I is the DC center level of the output of the subtracter 3 (the reference voltage is subtracted from the input signal) obtained in the section H, this DC level is subtracted from the input signal. In the section I, the output of the subtractor 3 is automatically corrected to a bit sync signal having a DC center level equal to the reference voltage, as shown at 21 in FIG. 6, and thereafter, this correction state is maintained until the packet ends. Will be maintained.

Another configuration example of the "1,0" detector is shown in FIG. In FIG. 7, 21 is a baseband signal input line, 38 is a comparator, 39 is a reference voltage generator, 40 is a digital phase synchronization circuit, 41 is a shift register, 42 is a coincidence detector, and 43 is "1,0" generation. Vessel, 14 is "1,0"
It is a detection output line. FIG. 7 shows that the offset amount of the DC center level, that is, the frequency error is not so large, and the comparator 3
8 is a simple configuration example of the "1,0" detector 10 that can be used when the output of FIG. 8 is such that the digital signal is reproduced even if the duty ratio is not correct. Comparator 3
When a digital signal is reproduced at the output of 8, the digital phase synchronization circuit 40 is synchronized by this signal and the bit timing is reproduced. The shift register 41 has a two-stage configuration, and the digital signals output from the comparator 38 are read one after another at this bit timing. The contents of the shift register 41 are “1,0” from the “1,0” generator 43.
0 "is compared with the coincidence detector 42, and if they coincide with each other, a detection pulse is output. Once the detection pulse is output, the shift register 41 stops reading within the packet period.

FIG. 1 shows a configuration in which the DC center level of the subtractor output signal is detected and fed back to the subtractor.
As shown in FIG. 8, automatic correction can also be performed by directly detecting the DC center level of the input signal and subtracting the detected level from the input signal. This is because the control operation of the present invention is an open control, not a continuous control system, as is clear from the above description. However,
In the case of the configuration of FIG. 8, the adder 7 in the DC center level detection circuit 4 needs to be changed to a subtractor.

Although the configuration of FIG. 1 has been described as being applied to the output of the frequency discriminator of the FSK receiver, it is obvious that the configuration as it is can be applied to the baseband transmission system. Further, with the configuration described below,
Since an AFC (automatic frequency control) system can be configured and the received signal can be amplified at the center of the band, it is possible to prevent deterioration of the demodulation waveform.

The structure will be described below. The system diagram is shown in FIG. In FIG. 9, 44 is an FSK signal input terminal, 45 is a frequency converter, 46 is an intermediate frequency amplifier,
Reference numeral 47 is a frequency discriminator, 48 is a demodulation signal output terminal, 49 is a voltage controlled local oscillator, and 4 is the DC center level detection circuit described in FIG. The difference from the case of FIG. 1 is that instead of subtracting the detection output of the DC center level from the input baseband signal voltage, the voltage controlled local oscillator 49 is controlled by this detection DC center level in FIG. Since the DC center level detection operation is exactly the same as that described in FIG. 1, the frequency of the FSK signal is controlled to the center of the intermediate frequency amplifier and the frequency discriminator by controlling the frequency of the local oscillator with this detection output. It can be corrected automatically.

[0016]

As described above in detail, in the FSK signal transmission system, the frequency accuracy and stability of each part of the transmitter / receiver are the baseband signal transmission system, and the voltage accuracy and stability of each part are the quality of the reproduced digital signal in the baseband signal transmission system. The more serious the influence is, and the more the multilevel signal is, the larger the influence is. According to the present invention, the DC center level is detected by utilizing the fact that the FSK signal and the baseband signal having the packet structure have the bit synchronization signal of "1,0" repeated at the beginning of the packet, and therefore, the high accuracy is achieved. The DC center level automatic correction circuit can be configured, and a high quality digital signal transmission system can be provided. Further, the packet configuration is such that an unmodulated carrier having a center frequency and a DC center level are transmitted before the bit synchronization signal. However, if the present invention is applied, this transmission is unnecessary. Therefore, the transmission efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit system diagram showing an embodiment of the present invention.

FIG. 2 is a packet structure example for explaining the contents of a packet of a transmission signal applied to the present invention.

FIG. 3 is a waveform diagram showing a bit synchronization signal and its DC center level for explaining the present invention.

FIG. 4 is a circuit system diagram showing a circuit configuration example of a “1,0” detector that detects “1,0” which is the minimum repetition of a bit synchronization signal in the present invention.

FIG. 5 is a waveform diagram for explaining the operation of the “1,0” detector used in the present invention.

6 is a waveform chart for explaining an automatic correction operation of the circuit of FIG.

FIG. 7 is a circuit system diagram showing another circuit configuration example of the “1,0” detector of FIG.

FIG. 8 is a circuit system diagram for explaining another configuration of the circuit of FIG.

FIG. 9 is a circuit system diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 demodulation baseband signal input terminal 2 baseband signal output terminal 3 subtractor 4 DC center level detection circuit 5 gate circuit 6 integrator 7 adder 8 switcher 9 control pulse generator 10 "1,0" detector 11 reference oscillator 12 packet length setting device 13 reference voltage generator 14 output line of “1,0” detector 10 15 output line of packet length setting device 16 output line of reference oscillator 11 output line of reference oscillator 11 18 control pulse generator 9 output line 19 control pulse generator 9 output line 20 control pulse generator 9 output line 21 subtractor 3 output line 22 gate circuit 5 output line 23 integrator 6 output line 24 switcher 8 output line 25 multiplier 26 multiplier 27 gate circuit 28 gate circuit 29 integrator 30 integrator 31 squarer 32 squarer 33 adder 34 comparator 35 reference voltage generator 36 gate circuit 37 pulse generator 38 comparator 39 reference voltage generator 40 digital phase synchronization circuit 41 shift register 42 coincidence detector 43 “1,0” generator 44 FSK signal input terminal 45 Frequency converter 46 Intermediate frequency amplifier 47 Frequency discriminator 48 Demodulation signal output terminal 49 Voltage control local oscillator

Claims (2)

[Claims] 1. A DC center level is detected by integrating the received base-dond signal during at least one time of repetition of "1,0" in the received base-band signal having a packet structure, and the detected output is the detected output. A baseband signal configured to maintain the automatic correction of the DC center level within the packet period by subtracting from the DC level of the received baseband signal and holding the integrated output over the packet period. DC center level automatic correction circuit. 2. A DC center level is detected by integrating the reception base dond signal for at least one time of repetition of "1,0" in the reception baseband signal having a packet structure, and this detection output is received. By being fed back to the local oscillator at the pre-machine stage, subtracted from the received baseband signal, and by holding the integral output over the packet period, automatic correction of the DC center level within the packet period is maintained. DC center level automatic correction circuit for configured baseband signals.