JPH06291668A - Multi-valued signal decoding circuit - Google Patents

Abstract

PURPOSE:To automatically maintain a reference voltage for decoding which is relatively correct to a received multi-valued data signal in packet form by generating the reference voltage for decoding from a received signal at the time of the decoding of the multi-valued data signal in packet form. CONSTITUTION:In the decoding circuit 7, a sample holding circuit 31 samples an input signal (data transmitted code) with sampling pulses applied from a clock regenerating circuit 8 and holds its voltage until a next sampled value is obtained. This sample-held waveform 32 is inputted to comparators 33, 35, and 37, which are applied with V1, V2, and V3 as reference voltages, so their outputs 34, 36, and 38 are binary outputs. The outputs 34 and 38 among those outputs are applied to a selector 39, which selects the output 34 when the output 36 is 1 or the output 38 when the output 36 is 0 and outputs the 40, thereby performing correct decoding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for decoding a packet-type multilevel data transmission signal.

[0002]

2. Description of the Related Art In a wired or wireless transmission system for transmitting a multilevel signal, the amplitude and DC center level of the multilevel signal transmitted are fluctuated due to changes in environmental conditions such as temperature and power supply voltage. If the fluctuation is large, the noise margin is lowered, and further, an error occurs in the judgment in the decoding circuit.
Therefore, circuit design and mechanism design are performed so as not to be affected by external factors such as normal temperature and power supply voltage as much as possible. However, in mass production, there is a limit to the accuracy of parts, so there is a limit to the performance that can be achieved. . Although an automatic amplitude control circuit can be used, this method has the following drawbacks. That is, as the amplitude control element, it is general to use the internal resistance between the drain and source of the field effect transistor (FET), but the value of the internal resistance with respect to the control voltage (applied voltage between the gate and source) is , Individual FET
Since there is variation due to, the control system must be a closed loop. Therefore, in order to stabilize the operation of this loop, a certain amount of time is required until the operation of the loop converges, and this operation cannot be performed on a multilevel signal. It is necessary to provide this training time at the beginning of the packet for automatic amplitude control, and to hold the automatic control system as it is at the part of the multilevel signal. The automatic control system is highly stable in its operation,
The higher the accuracy, the longer the training time must be, and the transmission efficiency is reduced accordingly.

[0003]

In the transmission of multilevel signals, there is a limit in maintaining the input signal amplitude of the decoding circuit to the digital code so as not to be affected by various environmental conditions, and there is a limit in the closed loop configuration. The use of the automatic amplitude control system inevitably leads to a decrease in transmission efficiency due to the required training time.

An object of the present invention is to provide a multilevel signal decoding circuit capable of suppressing the deterioration of noise margin and changing the occurrence of decoding error by changing the decoding reference voltage in accordance with the fluctuation of the input signal amplitude. To provide.

[0005]

In transmitting a digital signal, in order to detect a code error due to normal transmission, a length of 128 bytes to 1024 bytes (in the case of an 8-bit code, 102 bytes) is used.
A signal divided into a packet (also called burst or block) format composed of a code of about 4 bits to 8192 bits is used. At the beginning of this packet signal, demodulation or decoding is performed on the receiving side. In order to push out and reproduce the clock required for the operation from the received signal, it is usually a binary alternating cycle (for effective use of the transmission bandwidth,
Normally, a sine wave is used) to transmit a bit synchronization signal having a length of several bits to several tens of bits. In the present invention, the DC center level and amplitude are detected using this bit synchronization signal,
Since both voltages are held over the packet signal section and the reference voltage for the decoding circuit is created from these voltages, accurate decoding can always be performed.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a configuration example of a packet signal. At the beginning of the packet, the bit synchronization code indicated by A is transmitted for several bits to several tens of bits. This signal is usually a binary repetitive signal as described above, but it is almost a sine wave (2400H when the sync code is 4800 bps).
z), even when transmitting multi-valued data,
The header parts A, B, C and D in FIG. 2 are transmitted as a binary signal having an amplitude equal to the maximum amplitude of the multivalued data part. Since the bit synchronization code A is transmitted as a sinusoidal analog waveform, the analog waveform is hereinafter referred to as a bit synchronization signal. The bit sync signal is usually
Since the maximum amplitude is constant, the receiving side can detect the DC center level and the amplitude from the bit synchronization signal, and the reference voltage required for decoding can be created from these two voltages. Therefore, if this reference voltage is held during the packet section, the correct decoding operation can always be maintained.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a frequency discriminator output if the transmission path is wireless transmission by frequency shift keying (FSK), a reception input signal terminal if wired transmission, and an input terminal for a multilevel baseband signal. is there. 2 is a decoded signal output terminal decoded into a digital signal, 3 is a DC center level and amplitude detection circuit, 4 is a control pulse generation circuit,
Reference numeral 5 is a synchronous code detection circuit, 6 is a reference voltage generation circuit, 7 is a decoding circuit, 8 is a clock recovery circuit, and 9 is a reference frequency generator.

There are various multilevel signals, but in the following,
For ease of explanation, 4-value clock speed is 4800p
An example of ps, that is, a data transmission rate of 9600 bps will be described. FIG. 3 is a waveform example of a four-valued signal, and shows a case where there is no error in the center level and amplitude. The waveform A in FIG. 3 means the bit synchronization signal in FIG.
Means that it is the data transmission code of FIG. P
Indicates a sampling clock pulse obtained from the clock recovery circuit. If the voltage of the pulse sampled by this clock pulse is equal to or higher than the reference voltage V _{1, the} decoding circuit outputs “11”, and if it is between the reference voltages V ₁ and V ₂ , “10” and V ₂ . If it is between V ₃ , "01", V ₃
In the following cases, "00" is output. As is clear from FIG. 3, the reference voltage V ₂ in this case is the center voltage of the waveform A, and the reference voltages V ₁ and V ₃ are voltages corresponding to 1/3 of the voltage between the positive peak and the negative peak of the waveform A. However, the voltages are set to positive and negative voltages respectively shifted from V ₂ . In order to maximize the noise margin, these reference voltages are central voltages of two adjacent binary values of the four-valued input signal.
Therefore, even if the DC center level or the amplitude of the input signal changes, each reference voltage may be corrected so as to maintain the above voltage relationship according to the change.

When the signal having the waveform shown in FIG. 3 is applied to the input signal terminal 1 of FIG. 1, the entire operation starts with the operation of the synchronous code detecting circuit 5 first. The bit sync signal is
As described above, since it is a binary alternating repetitive signal having a length of several bits to several tens of bits, it can be easily detected by the circuit shown in FIG. In FIG. 4, 10 is an AC coupling circuit, 11 is a shaping circuit, 12 is a shift register, 13
Is a coincidence detection circuit. Even if the DC center level of the input signal is not zero, the AC coupling circuit 10 eliminates the DC offset, and the signal is added to the shaping circuit 11 in the state of the waveform A in FIG. 3 to be shaped into a rectangular wave. Bit sync signal is 2
At 400 Hz, a square wave of this speed is generated by the 4800 pps clock pulse from the reference frequency generator 9.
It is sequentially read into the shift register 12. The contents of each stage of the shift register are inspected by the coincidence detection circuit 13,
If "1" and "0" are alternately arranged in the required number of bits, a coincident output is obtained, which means that the bit synchronization code is detected.

When the bit sync code is detected, the control pulse generator 4 is operated by the 4800 pps clock pulse from the reference frequency generator 9. Control pulse generator 4
FIG. 5 shows a configuration example of the above. In FIG. 5, 14 is a clock pulse input line from the reference frequency generator 9, and 15 is 1 /
2 frequency divider circuit, 16 frequency divider circuit output line, 17 gate circuit, 18 gate circuit output line, 19 flip-flop circuit, 20 flip-flop circuit output line,
Reference numeral 21 is an output line of the synchronous code detection circuit 5, and 22 is a flip-flop circuit. 14, 16, 18, 20, 21
The waveforms in each line are shown by the same numbers in the lower part of FIG.
In FIG. 5, the 4800 pps clock of the line 14 is divided by the 1/2 divider circuit 15 to generate the 2400 pps clock of the line 16. On the other hand, if the sync code detection circuit 5 detects a bit sync code, 2
A match detect pulse such as 1 sets flip-flop 22 so that its output causes gate circuit 17 to hear and produce a pulse at 18 at its output. By driving the flip-flop circuit 19 with this pulse,
The pulse shown by 20 is obtained, and at the same time, the flip-flop circuit 22 is reset. Therefore, the pulse output to the line 20 has a length of 1/2400 seconds, and this pulse is used as a time reference for operating the DC center level and amplitude detection circuit 3.

FIG. 6 shows a DC center level and amplitude detection circuit 3
And an example of the circuit configuration of the reference voltage generating circuit 6. In FIG. 6, 23 is a positive peak hold circuit, 24 is a negative peak hold circuit, 25 is an addition circuit, 26 is a subtraction circuit, and 27 is 1
A 1/2 voltage dividing circuit, 28 is a 1/3 voltage dividing circuit, 29 is an adding circuit, and 30 is a subtracting circuit. Positive peak hold circuit 23
The negative peak hold circuit 24 detects the positive peak voltage and the negative peak voltage in the signal input within this time by the control pulse having a length of 1/2400 seconds from the control pulse generation circuit 4, respectively. And hold. Therefore, both of these voltages are added by the adder circuit 25 to obtain 1
If the voltage is divided into 1/2 by the 1/2 voltage dividing circuit 27, the DC center level (V _{2 in} FIG. 3) can be obtained. In addition, the subtraction circuit 26
By taking the difference between the two voltages, the voltage between the positive peak and the negative peak can be obtained. Therefore, if this voltage is divided into 1/3 and added to and subtracted from the DC center level, the reference explained with reference to FIG. The voltages V ₁ , V ₂ and V ₃ will be obtained.

FIG. 7 shows a circuit configuration example of the decoding circuit. Figure 7
, 31 is a sampling / holding circuit, 32 is its output line, 33, 35, 37 are comparators, 34, 3
Reference numerals 6 and 38 denote the respective output lines, 39 denotes the selector, and 40 denotes the output line. The sampling / holding circuit 31 samples the input signal (FIG. 3E) by the sampling pulse P shown in FIG. 3 applied from the clock regenerating circuit 8 and holds the voltage until the next sampled value is obtained. This operation will be described with reference to FIG. The dotted line 32 shown in FIG. 8 is the sampling / holding waveform. Since V ₁ , V ₂ and V ₃ are applied as reference voltages to the comparators 33, 35 and 37, binary outputs 34, 36 and 38 shown in FIG. 8 are obtained. Three
4 and 38 are added to the selector 39. Here, 34 is selected when 36 is "1", and 38 is selected when 36 is "0".
It is output as 0, which means that it is correctly decoded.

The DC center level and amplitude detection method described with reference to the drawings was a method of creating from a positive peak and a negative peak, but this can of course be detected by other methods. An example thereof is shown in FIG. FIG. 10 is a waveform of each corresponding part of FIG. In FIG. 9, 41 and 48 are gate circuits, 42 and 49 are output lines thereof, and 43 and 50.
Is an integrating circuit, 44 and 51 are its output lines, 45 is a subtracting circuit, 46 is its output line, 47 is a double-wave rectifying circuit, 5
2 is a control pulse generating circuit, and 53, 54, 55 and 56 are output lines thereof. When a sync code having a DC component is applied from the input signal terminal 1 as shown by 1 in the waveform diagram of FIG. 10, the gate circuit 4 is controlled by the control pulse shown by the waveform 53 of the control pulse generating circuit 52.
1 opens the gate only while it is equal to one cycle of the synchronizing signal, and the output is integrated by the integrator 43 to obtain 4
As shown in 4, the DC center level is detected, and thereafter the voltage is held. The pulse waveform shown at 54 is the discharge pulse of the integrator 43. Since the DC center level is subtracted from the input signal in the subtraction circuit 45, its output is corrected to a signal having no DC component as shown in the waveform chart 46. This signal is applied to the gate circuit 48 and the integrating circuit 50 through the full-wave rectification circuit 47.
Since 8 is opened by the control pulse indicated by 55, its output waveform becomes a waveform indicated by 49, and a voltage indicating the amplitude is obtained at the output of the integrating circuit 50, as indicated by 51.

Therefore, when the circuit of FIG. 9 is used, the reference voltage of the decoding circuit, when applied to the circuit of FIG. 7, allows V ₂ to be zero volt, and the reference voltage directly to the output of the integrating circuit 50. Since V ₁ is obtained, it is inverted and amplified (gain-
1) Then, V ₃ is obtained. However, in this case, the input of the decoding circuit 7 of FIG. 7 is the output 46 of the subtraction circuit 45 of FIG.
From the above, the input multilevel data signal whose DC center level is set to 0 volt in advance is decoded by the circuit of FIG. That is, in the configuration of FIG. 6, by changing the reference voltage V ₂ in conjunction with the change in the DC center level of the input signal, it is possible to always obtain a correct reference voltage relative to the input signal. 9
In the configuration (1), first, the DC center level is corrected so that it becomes zero (it operates in the bit synchronization signal section, but this correction operation is maintained even in the multilevel signal section), and then the amplitude is detected for this signal. Then, V ₁ and V ₂ are created from this. Therefore, in the case of FIG. 9, since the DC center level of the multilevel signal is always corrected to zero, the reference voltage V ₂ may be zero volt.

As another method, although detailed description is omitted, the DC component and the amplitude can be detected by using the Fourier analysis method. In this case, if the detection time length is set to a certain length or more, since it also has a synchronous code detecting function, the synchronous code detecting circuit 5 can be omitted.

Although the above description has been made by taking the decoding of four-valued data as an example, it is obvious that the present invention can be applied to the decoding of multi-valued data having four or more values, as is clear from the operation description. is there.

[0017]

As described above in detail, in the present invention, the decoding reference voltage is generated by using the bit synchronization signal in the header portion of the packet in decoding the packet-type multilevel data transmission signal. Even if the DC center level or amplitude of the received signal varies, a correct decoding reference voltage is always obtained relative to the received signal, and the noise margin can always be kept at the maximum state.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is an example of a packet structure for explaining contents of a packet of a transmission signal applied to the present invention.

FIG. 3 is a waveform diagram showing a relationship between a waveform of a four-valued signal and a decoding reference voltage.

FIG. 4 is a circuit configuration diagram of a synchronous code detection circuit which is one of the constituent elements of the embodiment of FIG.

5 is a circuit configuration diagram of a control pulse generation circuit which is one of the constituent elements of the embodiment of FIG.

6 is a circuit configuration diagram of a DC center level and amplitude detection circuit which is one of the components of the embodiment of FIG.

FIG. 7 is a circuit configuration diagram of a decoding circuit which is one of the constituent elements of the embodiment of FIG.

FIG. 8 is a waveform diagram for explaining the operation of the decoding circuit.

9 is a circuit configuration diagram showing a configuration example of a DC center level and amplitude detection circuit different from the example of FIG.

10 is a waveform chart for explaining the operation of the circuit of FIG.

[Explanation of symbols]

1 Multi-level data signal input terminal 2 Decoded signal output terminal 3 DC center level and amplitude detection circuit 4 Control pulse generation circuit 5 Synchronous code detection circuit 6 Reference voltage generation circuit 7 Decoding circuit 8 Clock recovery circuit 9 Reference frequency generator 10 AC coupling Circuit 11 Shaping circuit 12 Shift register 13 Match detection circuit 14 Clock input line 15 1/2 frequency divider circuit 16 Frequency divider circuit output line 17 Gate circuit 18 Gate circuit output line 19 Flip-flop circuit 20 Control pulse generation circuit output line 21 Synchronous code Detection circuit output line 22 Flip-flop circuit 23 Positive peak hold circuit 24 Negative peak hold circuit 25 Addition circuit 26 Subtraction circuit 27 1/2 voltage divider circuit 28 1/3 voltage divider circuit 29 Addition circuit 30 Subtraction circuit 31 Sampling / hold circuit 32 sampling and hold Output line 33 comparator 34 comparator output line 35 comparator 36 comparator output line 37 comparator 38 comparator output line 39 selector 40 selector output line 41 gate circuit 42 gate circuit output line 43 integration circuit 44 integration circuit output line 45 subtraction circuit 46 subtraction circuit output Line 47 Double-wave rectifier circuit 48 Gate circuit 49 Gate circuit output line 50 Integrator circuit 51 Integrator circuit output line 52 Control pulse generator circuit 53, 54, 55, 56 Control pulse generator circuit output line

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[Procedure amendment]

[Submission date] May 10, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

Claims (3)

[Claims] 1. A decoding circuit for a packet-type multi-level data signal, at least from a detection output that detects repetition of "1,0" of a bit synchronization signal included in the transmitted packet-type multi-level data signal. A detection circuit for detecting the amplitude of "1,0" once and the DC component corresponding to the median of the amplitude, and the multivalued reference voltage for decoding the multivalued data signal using the amplitude and the DC component. And a reference voltage creating circuit for creating and holding the multilevel signal decoding circuit. 2. A packet-type multi-level data signal decoding circuit for detecting a positive peak value and a negative peak value of a bit synchronization signal located in the header portion of each packet of the transmitted multi-level data signal. A hold circuit for holding, a DC component corresponding to the median of the amplitude of the bit synchronization signal, the positive peak value and the negative peak value from the positive peak value and the negative peak value obtained from the hold circuit. Of the multivalued data signal by a detection circuit for extracting the DC value, and a plurality of reference voltages obtained by adding and subtracting a DC center level corresponding to the DC component and a required voltage proportional to the amplitude of the bit synchronization signal to the DC component. A multi-valued signal decoding circuit, comprising: a reference voltage creating circuit for creating a multi-valued reference voltage for decoding. 3. A packet-type multi-valued data signal decoding circuit detects and holds a DC component included in one period section of a bit synchronization signal included in the transmitted packet-type multi-valued data signal. A first detection circuit for extracting the packet-type multivalued data signal containing no DC component by subtracting the held DC component from the bit synchronization signal; and packet-type multivalued data not containing the DC signal. A second detection circuit for taking out a voltage proportional to the amplitude of the bit synchronization signal by performing double-wave rectification on the bit synchronization signal in the signal; and a zero potential corresponding to the median value of the amplitude of the bit synchronization signal and the proportionality. A multi-valued signal decoding circuit that creates and holds a multi-valued reference voltage for decoding the multi-valued data signal that does not include the DC signal from the voltage.