JPH07297871A - Tdma data receiver - Google Patents

Abstract

PURPOSE:To detect a symbol identification point and to implement automatic frequency control in the TDMA data receiver. CONSTITUTION:Reception data read from a RAM 10 are given to a switch 12, from which I, Q data are outputted to discrimination circuits 19, 20 via a phase compensation circuit 18, in which discrimination values Id, Qd are obtained. Then a correlation arithmetic circuit 14 is used to obtain a complex correlation psid between the I, Q data and the Id, Qd data for a block of information symbol data and a complex correlation psisw between the data I, Q for the block of the synchronization word and the base band signal of the known synchronization word outputted from a synchronization word generating circuit 15 and a correlation power ¦psi¦ of a total complex correlation. A selection circuit 16 decides a sample point at which the correlation power ¦psi¦ is maximum and the switch 12 samples the data by using it as a symbol identification point. The selection circuit 16 detects the complex correlation psisw at the maximum sample point as a phase error for the frequency offset and averages it to compensate the phase of the I, Q signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiple access (TDMA) data receiving apparatus used in digital radio communication, and at the time of frame synchronous reception, the received data after baseband differential detection and a known synchronous word are used. By taking the correlation, the phase error caused by the detection of the symbol identification point and the frequency offset is compensated, and the estimated values at the current and past reception slots are used for averaging, and the automatic frequency control is performed.
(AFC).

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing the structure of a conventional TDMA data receiving apparatus.
4-shift 4-phase phase modulation (QPSK) wave signal (hereinafter π / 4
A shift QPSK modulated wave signal) is received.

In FIG. 7, 1 is an antenna for receiving a π / 4 shift QPSK modulated wave signal of TDMA, 2 is a receiving root Nyquist band pass filter (hereinafter abbreviated as RNBPF) for waveform shaping of the received signal, 3 is a limiter amplifier connected to the output of RNBPF2, and 4 is
A quadrature detector for frequency-converting the output of the limiter amplifier 3 to detect an in-phase component and a quadrature component of the baseband,
Reference numeral 5 is a local oscillator for supplying the quadrature detector 4 with a sine wave signal which is quasi-synchronized with the carrier frequency of the received signal,
FIG. 6 shows a phase diagram after baseband differential detection when a frequency offset is generated in this local oscillator.

Reference numerals 6 and 7 denote in-phase components of the quadrature detector 4,
An A / D converter that operates at a sampling frequency M times (M: a positive integer) the symbol rate for converting the quadrature component output into a digital signal. The second switch (SW) for sending the reception slot data after A / D conversion to the RAM 10 described later according to the control signal from the reception window function generation circuit 9 described later when frame synchronous reception is performed after Is.

The reception window function generation circuit 9 described above defines the reception time of the reception slot of its own station on the basis of the synchronization pulse supplied from the selection circuit 16 described later during continuous reception for frame synchronization acquisition. A reception window function is generated and this reception window function is supplied as a control signal to the second switch 8 at the time of frame synchronization reception. The procedure for frame synchronization acquisition at the time of this frame synchronization reception is shown in FIG.

The above-mentioned RAM 10 is for storing the data of the receiving slot of its own station after A / D conversion via the second switch 8, and FIG. 3 shows the received data stored in this RAM. An example is shown.

Reference numeral 11 denotes a first switch (SW) for sending the outputs of the A / D converters 6 and 7 to a baseband delay detection circuit 13 which will be described later, when the burst reception signals are continuously received for frame synchronization acquisition. ), 12 is a first for sampling and reading the reception slot data of its own station stored in the RAM 10 at each symbol period in response to a control signal from the selection circuit 16 described later at the time of frame synchronous reception. 3 switches (SW).

The above-mentioned baseband differential detection circuit 13 takes in the oversampled outputs X and Y of the A / D converters 6 and 7 at the time of continuous reception, and at the time of frame synchronous reception. The reception slot data Xs, Ys of the own station sampled for each symbol period which is the output of the third switch 12 is taken in, and the cosine of the modulation phase difference of the π / 4 shift QPSK modulated wave signal received from these data is obtained. The sine is output as an oversampled in-phase component I and quadrature component Q, or as an in-phase component I and quadrature component Q sampled for each symbol period.

FIG. 5 shows a phase diagram of the judgment result after the baseband delay detection of the π / 4 shift QPSK modulated wave signal received by the baseband delay detection circuit 13.

Reference numeral 14 denotes a correlation calculation circuit, which is used for continuous reception for frame synchronization acquisition, and the baseband of the oversampled I and Q signals and a known synchronization word output from a synchronization word generation circuit 15 described later. The complex correlation value Ψ between the signal values and its correlation power | Ψ | are calculated in real time and supplied to the selection circuit 16 described later. At the time of frame synchronization reception, the I and Q signals sampled for each symbol period are The complex correlation value Ψ _SW between the I and Q signals and the base band signal value of the known sync word output from the sync word generating circuit 15 described later and the correlation power | Ψ _SW | , This correlation calculation is performed a plurality of times while sliding the sampling position for each symbol period by the third switch 12, and the result is sent to the selection circuit 16 described later. To supply.

The above-mentioned sync word generation circuit 15 supplies the cosine and sine of the modulation phase difference corresponding to the known sync word to the correlation calculation circuit 14 as baseband signals.
FIG. 8 shows the procedure of correlation calculation between the received data after baseband differential detection and a known sync word at the time of frame synchronous reception.

The selection circuit 16 described above uses the correlation power │Ψ of the complex correlation value Ψ during continuous reception for frame synchronization acquisition.
When │ is observed and the correlation power │Ψ│ shows a peak value exceeding the set threshold value, it is determined that the sync word is received at that time, and the sync pulse is generated by the reception window function generating circuit 9 described later. To the phase error θe due to the frequency offset.
It is supplied as an estimated value to the phase compensation circuit 18 described later to set the initial value of the phase error θe in preparation for frame synchronous reception.

During frame synchronous reception, the correlation power | Ψ _SW | of the complex correlation value Ψ _SW is observed and the correlation power | Ψ _{SW
When SW} | shows the maximum value exceeding the set threshold value, the sample position for each symbol period in the third switch 12 at that time is determined to be a symbol identification point,
A control signal for sampling at that timing is supplied to the third switch 12, and the complex correlation value Ψ _SW at the time when the correlation power │Ψ _SW │ shows the maximum value is added to the phase error θe due to the frequency offset. The estimated value is supplied to the phase compensation circuit 18, which will be described later.

The above-mentioned phase compensating circuit 18 is for compensating the phase error θe due to the frequency offset of the local oscillator 5 with respect to the outputs I and Q of the baseband delay detection circuit 13 at the time of frame synchronous reception. Is. Numerals 19 and 20 are decision circuits for performing binary decision on the values of the outputs Ie and Qe of the phase compensation circuit 18 and outputting the results as Id and Qd. Reference numeral 21 is the outputs Id and Qd of the decision circuits 19 and 20. Is a decoder for converting the data into binary serial data, and 22 is a reception data output terminal for detecting the output of the decoder 21 as reception data.

Next, the operation of the above-mentioned conventional example will be described based on FIG. 7 with reference to FIGS. 2, 3, 5, 5, and 8. In FIG. 7, π / received from the antenna 1
The 4-shift QPSK modulated wave signal is input to the quadrature detector 4 via the RNBPPF 2 and the limiter amplifier 3, and is frequency-converted into a baseband signal through the quadrature detector 4. At this time, the symbol rate of the modulated wave signal is fR = 1 / T (T: symbol period), and the sampling frequency of the A / D converters 6 and 7 is fs.
= 1 / Ts = MfR (Ts: sampling period, M: oversampling ratio (positive integer)), the outputs X (nTs) and Y (nTs) of the A / D converters 6 and 7 are given by (Equation 1). , (Equation 2) However, it is assumed that the noise is zero.

[0016]

[Formula 1] X (nTs) = COS (φ (nTs) + 2πΔfnTs)

[0017]

(2) Y (nTs) = SIN (φ (nTs)) + 2πΔfnTs) In (Equation 1) and (Equation 2), φ (nTs) is the received π /
The modulation phase of the 4-shift QPSK modulated wave signal, Δf, represents the frequency offset which is the error between the center frequency of this modulated signal and the frequency of the local oscillator 5.

First, the operation during continuous reception for frame synchronization acquisition will be described.

During continuous reception, the first switch 11 is closed and the outputs of the A / D converters 6 and 7 are X (nTs) and Y (n).
Ts) is input to the baseband differential detection circuit 13. The baseband differential detection circuit 13 performs the operations of (Equation 3) and (Equation 4) on X (nTs) and Y (nTs).

[0020]

## EQU3 ## I (nTs) = X (nTs) X ((n-M) Ts) + Y (n
Ts) Y ((n-M) Ts)

[0021]

## EQU4 ## Q (nTs) = Y (nTs) X ((n-M) Ts) -X (n
Ts) Y ((n-M) Ts) As a result, the in-phase output I of the baseband differential detection circuit 13
(nTs) and the quadrature output Q (nTs) include the cosine and sine of the modulation phase difference Δφ (nTs) of the received π / 4 shift QPSK modulated wave signal as shown in (Equation 5) and (Equation 6). To occur.

[0022]

[Equation 5] I (nTs) = COS (Δφ (nTs) + θe)

[0023]

[Equation 6] Q (nTs) = SIN (Δφ (nTs) + θe)

[0024]

[Formula 7] Δφ (nTs) = φ (nTs) −φ ((n−M) Ts) However, θe in (Formula 5) and (Formula 6) becomes Δf as represented by (Formula 8). This is the resulting phase error.

[0025]

## EQU00008 ## .theta.e = 2.pi..DELTA.fTs = 2.pi..DELTA.fT In the following description, a signal having an in-phase component and a quadrature component will be described as a complex signal having the in-phase component in the real part and the quadrature component in the imaginary part.

The output of the baseband differential detection circuit 13 is expressed as a complex signal S (nTs) as shown in (Equation 9).

[0027]

S (nTs) = I (nTs) + jQ (nTs) = exp (j (Δφ (nTs) + θe)) (j: imaginary number) Further, here, each reception slot has a synchronization word of L symbols. , It is assumed that the synchronization word of the reception slot of the local station is already known. Then, the baseband signal corresponding to this known sync word is expressed as a complex signal in S shown in (Equation 10).
Expressed as i (kT) (k = 0, 1, 2, ... L-1),
It is assumed that this complex signal is output from the synchronization word generation circuit 15.

[0028]

[Equation 10] Si (kT) = exp (jΔφ (kT)) (k = 0, 1, 2, ... L-1) At the time of continuous reception, the position of the synchronization word of the receiving slot of the own station is detected. By doing so, frame synchronization is acquired and the position of the receiving slot of the own station is known. First, in the correlation calculation circuit 14, the S output from the baseband delay detection circuit 13 is output.
(nTs) and Si output from the synchronization word generation circuit 15
The complex correlation calculation shown in (Equation 11) is performed using (kT).

[0029]

[Equation 11]

Further, the correlation power of the complex correlation value Ψ (nTs) is calculated by (Equation 12).

[0031]

[Equation 12]

The correlation power | Ψ (nTs) | is 1
The following are real numbers. The selection circuit 16 uses the complex correlation value Ψ
(nTs) and the correlation power | Ψ (nTs) | are taken in, and the value of the correlation power | Ψ (nTs) | is observed first.

As shown in FIG. 2, the frame period of the received signal (1) is FTs, and (n0 + F1) Ts (1 = 0,
It is assumed that the last symbol Si ((L-1) T) of the synchronization word exists at the time of 1, ... m, m + 1 ,. That is, from (Equation 9) and (Equation 10),

[0034]

## EQU13 ## S ((n0 + F1-kM) Ts) = exp (j (Δφ (L
It is assumed that the relation −1−k) T) + θe (k = 0, 1, 2, ..., L-1) holds. Therefore, the time (n0
+ F1) Ts correlation power | Ψ ((n0 + F1) Ts) |
From 1), (Equation 12), (Equation 13),

[0035]

[Equation 14]

Then, the peak value is obtained as shown in FIG. When the value of the correlation power | Ψ (nTs) | takes a peak value exceeding the threshold value S, the selection circuit 16 determines that a sync word exists at that position, and at that time, FIG.
A receiving window function generating circuit 9 for generating a synchronization pulse as shown in FIG.
Supply to.

Further, the complex correlation value Ψ at the time when the correlation power | Ψ (nTs) | has a peak value of (n0 + F1) Ts.
((n0 + F1) Ts gives information on the phase error θe caused by the frequency offset as shown in (Equation 15).

[0038]

[Equation 15]

The information of the estimated value of the phase error given by (Equation 15) is supplied from the selection circuit 16 to the phase compensation circuit 18, which is used as the initial setting value of the phase compensation circuit 18 at the time of frame synchronous reception.

On the other hand, the receiving window function generating circuit 9 takes in the synchronizing pulse output from the selecting circuit 16 and defines the receiving time of the receiving slot of its own station as shown in FIG. Generate a receive window function that That is, in the same figure, the receiving slot of the own station exists while the receiving window function is H. However, here, in consideration of the error of the time when the sync pulse is generated, a margin mg is provided to generate a reception window function which is slightly wider than the actual reception slot. Then, at the time of frame synchronous reception of FIG. 3 (1), this reception window function (FIG. 3 (2)) is supplied to the second switch 8 as a control signal, and the reception slot data of its own station (FIG.
Only (3)) is loaded into the RAM 10 (Fig. 3 (4)).

Next, the operation of frame synchronization reception after the frame synchronization acquisition is completed and the reception time of the reception slot of the own station is defined by the reception window function will be described.

At the time of frame synchronous reception, the first time in FIG.
Switch 11 is opened and the receiving window function generator 9
According to the reception window function signal from, the second switch 8 is closed while the signal is H, X (nTs) of the A / D converters 6 and 7,
The Y (nTs) is stored in the RAM 10. As shown in FIG. 3, during the period when the reception window function (FIG. 3 (2)) is H, 1/2 symbol (T / T) before and after the length of the reception slot of the own station.
The margin of 2) shall be provided. Further, here, as shown in FIG. 3 (4), the format of the reception slot data stored in the RAM 10 is assumed as follows.

The received sample data of the in-phase component and the quadrature component stored in the RAM 10 are X (0), X (Ts), ..., X ((2N + L) MTs) Y (0), Y (Ts ), ..., Y ((2N + L) MTs) each (2N + L) M + 1 samples.

Among the received sample data stored in the RAM 10, the symbol data at the actual discrimination point is X (kT + (M / 2) Ts) (k = 0, 1, ..., 2N + L
-1) Y (kT + (M / 2) Ts) (k = 0, 1, ………, 2N + L
−1) (T = MTs, oversampling ratio M is an even number), each of 2N + L symbols, of which k = 0,
1, ………, N-1, and k = N + L, N + L + 1, ……
…, 2N + L-1 data is information symbol data
(2N symbols), k = N, N + 1, ..., N + L-1 The data at the time is assumed to be a synchronization word (L symbol).

Next, the symbol identification point is detected from the data stored in the RAM 10. That is, kT + (M / 2) Ts (k = 0, 1, ..., 2N + L described in the above assumption
-1) The time is detected. First, the sample data stored in the RAM 10 in FIG.
As shown by (3), the data is read through the third switch 12 every symbol period T, and the values are set as Xs (kT) and Ys (kT).

[0046]

Xs (kT) = X ((kM + m) Ts) = X (kT + mTs) Ys (kT) = Y ((kM + m) Ts) = Y (kT + mTs) (k = 0, 1, ... ......, 2N + L-1) Here, the value of m in (Equation 16) is changed (m = 0, 1, ..., M) according to the control signal from the selection circuit 16, and the sample position for each symbol period is changed. Read data while sliding. Next, Xs (kT) and Ys (kT) are input to the baseband differential detection circuit 13. In the baseband differential detection circuit 13, for Xs (kT) and Ys (kT)
The calculation of (Equation 17) and (Equation 18) is performed.

[0047]

I (kT + mTs) = Xs (kT) Xs ((k-1) T) + Ys (k
T) Ys ((k-1) T) = X (kT + mTs) X ((k-1) T +
mTs) + Y (kT + mTs) Y ((k-1) T + mTs) (k = 0,1, ........., 2N + L-1)

[0048]

Q (kT + mTs) = Ys (kT) Xs ((k−1) T) −Xs (k
T) Ys ((k-1) T) = Y (kT + mTs) X ((k-1) T +
mTs) -X (kT + mTs) Y ((k-1) T + mTs) (k = 0, 1, ..., 2N + L-1) As a result, the in-phase output I of the baseband differential detection circuit 13 is obtained.
(kT + mTs) and quadrature output Q (kT + mTs) have the same modulation phase difference Δ of the received π / 4 shift QPSK modulated wave signal as shown in (Equation 19) and (Equation 20), as in the case of continuous reception.
Generate cosine and sine of φ (kT + mTs). However, θe is the phase error due to the frequency offset in the local oscillator 5, as in the case of (Equation 8) in the case of continuous reception.

[0049]

(19) I (kT + mTs) = COS (Δφ (kT + mTs) + θe)

[0050]

[Equation 20] Q (kT + mTs) = SIN (Δφ (kT + mTs) + θe)

[0051]

[Formula 21] Δφ (kT + mTs) = φ (kT + mTs) −φ
((k-1) T + mTs) In the following description, as in the case of continuous reception, a signal having an in-phase component and a quadrature component will be described as a complex signal having an in-phase component in the real part and an quadrature component in the imaginary part. . (Number 1
9), complex signal S (kT + m) as shown in (Equation 20) as shown in (Equation 22)
Express as Ts).

[0052]

S (kT + mTs) = I (kT + mTs) + jQ (kT + mT)
s) = exp (j (Δφ (kT + mTs) + θe)) (j: imaginary number) (k = 0, 1, ………, 2N + L-1) As a result, FIG. 8 (1) shows (Equation 22) In the received signal waveform S (kT + mTs) after the baseband differential detection of, the received symbol data after the baseband differential detection of 2N + L symbols is obtained as shown in FIG. 8 (2), and the sampling position for each symbol period is shown in FIG. By sliding as shown in (3),
This data gives M + 1 sets of m = 0, 1, ..., M. However, as shown in FIG.
0, 1, ..., N-1, and k = N + L, N + L + 1, ....
…, 2N + L-1 data is information symbol data
(2N symbols) and k = N, N + 1, ..., N + L-
The data at the time of 1 is the synchronization word (L symbol).

On the other hand, from the synchronization word generation circuit 15,
A complex baseband signal Si (kT) (k = 0, 1, ..., L-1) corresponding to the known sync word indicated by 0) is output.

Next, in order to detect the symbol identification point, first, in the correlation calculation circuit 14, the baseband delay detection circuit 13
Using the S (kT + mTs) output from the sync word generator and the Si (kT) output from the sync word generation circuit 15, the sync word interval (k = N, N + 1, ..., N + L-1) , (3), the value of m is changed to m = 0, 1, ..., M, and the complex correlation calculation shown in (Equation 23) is performed while sliding the sample position.

[0055]

[Equation 23]

Further, the correlation power of the complex correlation value Ψ _SW (m) is
Calculate by (Equation 24).

[0057]

[Equation 24]

The correlation power | Ψ _SW (m) | is a real number of 1 or less. Selection circuit 16, the complex correlation value [psi _SW (m) and the correlation power | Ψ _SW (m) | uptake, first correlation power while sliding the sample position for each symbol period to change the value of m | Ψ _SW ( m) Observe the value of |. Now, since the time kT + (M / 2) Ts is the symbol identification point based on the above-mentioned assumption regarding the above-mentioned received data, S (kT + (M / 2) Ts) (k = N, N + 1, ... …
, N + L-1) corresponds to the symbol value of the sync word. That is, from (Equation 10) and (Equation 22),

[0059]

(25) S (kT + (M / 2) Ts) = exp (j (Δφ ((k-
N) T) + θe)) (k = N, N + 1, ..., N + L-1). Therefore, the correlation power | Ψ _SW (M / 2) | at the sample position where m = M / 2 is (Equation 23),
From (Equation 24) and (Equation 25),

[0060]

[Equation 26]

Thus, the maximum value is obtained as shown in FIG. In the selection circuit 16, when the correlation power | Ψ _SW (m) | has the maximum value exceeding the threshold value S, the sampling position of the value of m at that time is determined as the symbol identification point. That is,
Here, it is determined that the sample position where m = M / 2 is the symbol identification point. Then, the value of m at the symbol identification point is supplied as a control signal to the third switch 12, and the received data is controlled to be sampled at the symbol identification point.

Further, the complex correlation value Ψ at the sample position where m = M / 2 where the correlation power | Ψ _SW (m) | takes the maximum value.
_SW (M / 2) gives the information of the phase error θe caused by the frequency offset as shown in (Equation 27).

[0063]

[Equation 27]

Ψ _SW (M / 2) of (Equation 27) is supplied to the phase compensation circuit 18 as information of the estimated value of the phase error in the current reception slot.

On the other hand, the received data S (kT +) sampled at the symbol identification point and subjected to baseband delay detection
(M / 2) Ts) has a phase error θe in a certain direction due to the influence of the frequency offset in the phase diagram on the I and Q planes as shown in FIG. The phase compensation circuit 18 uses the phase error information Ψ _SW (M / 2) supplied from the selection circuit 16 to perform the operation represented by (Equation 28) on S (kT + (M / 2) Ts). Thus, compensation of the phase error θe is realized.

[0066]

[Equation 28]

When the noise is zero, the phase compensation circuit 18 has a compensation range of -π <θe <π (-fR / 2 <Δf <fR / 2). The output Se (kT + (M / 2) Ts) of the phase compensating circuit 18 uses the decision circuits 19 and 20, and Δφ = π / when it exists in the first quadrant on the I and Q planes as shown in FIG. 4, Δφ = 3π / 4 when present in the second quadrant, Δφ = −3π / 4 when present in the third quadrant, Δ when present in the fourth quadrant
It is determined that φ = −π / 4. The outputs of the decision circuits 19 and 20 are converted into binary serial data by the decoder 21 and output from the reception data output terminal 22.

As described above, also in the above-mentioned conventional TDMA data receiving apparatus, at the time of frame synchronous reception, the correlation between the received data after the baseband differential detection and the known synchronous word is detected to detect the symbol identification point and frequency offset. Compensation of induced phase error, that is, automatic frequency control
(AFC) can be performed.

[0069]

However, in the above-mentioned conventional TDMA data receiving apparatus, at the time of frame synchronization reception, correlation is performed only for the synchronization word, the symbol identification point is detected, and the phase error caused by the frequency offset is compensated. Therefore, when the synchronization word section of the received data is distorted due to the influence of noise or fading, the detection accuracy of the symbol identification point in the reception slot and the estimation accuracy of the phase error are significantly deteriorated. was there.

The present invention solves such a conventional problem, and not only the section of the synchronization word of the received data but also the section of the information symbol data is correlated by using the judgment value, The purpose is to perform highly accurate automatic frequency control (AFC).

[0071]

In order to achieve the above object, the present invention detects a symbol identification point by correlating received data after baseband differential detection with a known synchronization word during frame synchronization reception. And T that performs automatic frequency control by compensating for the phase error caused by the frequency offset.
In the DMA data receiving device, in order to suppress the variation between the receiving slots of the phase error θe due to the frequency offset estimated by the selection circuit and improve the estimation accuracy of the phase error θe, the phase obtained in each receiving slot is increased. An inter-slot averaging circuit that calculates the average value of the error θe values between slots and supplies the result to the phase compensation circuit as the estimated value of the phase error θe is provided between the selection circuit and the phase compensation circuit. It is characterized by

[0072]

Therefore, according to the present invention, the received data after the baseband differential detection is correlated not only with the synchronization word section but also with the judgment value not only in the section of the information symbol data but also in the noise or fading. Even if the sync word section of the received data is distorted due to the effect of, if the judgment value of the information symbol data is correct, the correlation value for the information symbol data section is used to compensate for the distortion effect in the sync word, and the identification check is performed. Allow out.
Furthermore, the estimated value of the phase error due to the frequency offset is also averaged using the estimated values obtained in the past receiving slots, so that even if the estimated value in the current receiving slot is degraded, its effect will be affected. It is compensated and good automatic frequency control (AFC) can be performed.

[0073]

1 is a block diagram showing the configuration of a TDMA data receiving apparatus according to an embodiment of the present invention, which is, for example, the same .pi. / 4 shift QPS as the conventional example of FIG.
The case of receiving a K modulated wave signal is also applicable to a TDMA data receiving apparatus for differentially encoded N-phase PSK (N = 4, 8, 16, ...) Modulated wave.

The blocks having the same functions as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. However, functionally different blocks will be described.

The correlation calculating circuit 14 in this embodiment, during continuous reception for frame synchronization acquisition, oversamples the I and Q signals and the baseband signal value of the known sync word output from the sync word generating circuit 15. The complex correlation value Ψ and its correlation power | Ψ | are calculated in real time and supplied to the selection circuit 16. At the time of frame synchronization reception, I and Q information symbol data sections sampled for each symbol period are I , Q and its judgment value I
A complex correlation value Ψ d between d and Qd is calculated. For the section of the sync word, a complex correlation value Ψ _SW between I and Q and the baseband signal value of the known sync word output from the sync word generation circuit 15 is calculated. was calculated, further a correlation power of the complex correlation value of the total | Ψt | = (| Ψd | + | Ψ SW |) / 2 the calculated, sample position for each symbol period of these correlations calculated by the third switch 12 Is performed plural times while sliding, and the result is supplied to the selection circuit 16.

Further, the selection circuit 16 determines the correlation power | Ψ of the complex correlation value Ψ during continuous reception for frame synchronization acquisition.
When | is observed and the correlation power | Ψ | shows a peak value exceeding the set threshold value, it is determined that the sync word is received at that time point, and the sync pulse is directed to the reception window function generating circuit 9. Then, the complex correlation value Ψ at that time is supplied to an inter-slot averaging circuit 17, which will be described later, as an estimated value of the phase error θe caused by the frequency offset. Further, at the time of frame synchronization reception, the correlation power | Ψt | of the total complex correlation value is observed, and when the correlation power | Ψt | shows the maximum value exceeding the set threshold value, the third power When the sampling position of the switch 12 for each symbol period is determined as a symbol identification point, a control signal for sampling at that timing is supplied to the third switch 12, and the correlation power | Ψt | shows the maximum value. phase error θe due to frequency offset complex correlation values [psi _SW in
It is supplied to the inter-slot averaging circuit 17 described later as the estimated value of

The inter-slot averaging circuit 17 described above is an additional circuit that is a feature of the present invention. This averaging circuit between slots 17
Is the phase error information Ψ or Ψ _SW from the selection circuit 16.
The average value is used as the initial estimation value of the phase error in preparation for the frame synchronization signal during continuous reception, and the average value is used for the frame synchronization signal. It is supplied to the phase compensation circuit 18 as an estimated value of the phase error in the reception slot.

Next, the operation of this embodiment will be described with reference to FIG. 1 and with reference to FIGS. 2, 3, 4, 5, and 6. The conventional TDMA data receiving apparatus shown in FIG. In the receiving operation in, the complex correlation value Ψ ((n0 + F1) at the time when the correlation power | Ψ (nTs) | takes a peak value (n0 + F1) Ts based on the π / 4 shift QPSK modulated wave signal received from the antenna 1. Ts) is obtained (Equation 1)
From (1) to (Equation 15), this embodiment is also the same, so the following operation will be described.

The information on the designated value of the phase error given by the above (Equation 15) is averaged with the designated value in each reception slot in the inter-slot averaging circuit 17, as shown in (Equation 29). , Ψa ((n0 + F1) Ts) are supplied to the phase compensation circuit 18.

[0080]

[Equation 29]

This value is an initial setting value of the phase compensation circuit 18 at the start of frame synchronous reception.

On the other hand, the receiving window function generating circuit 9 takes in the synchronizing pulse output from the selecting circuit 16 and defines the receiving time of the receiving slot of its own station as shown in FIG. Generate a receive window function that That is, in the same figure, the receiving slot of the own station exists while the receiving window function is H. However, here, in consideration of the error of the time when the sync pulse is generated, a margin mg is provided to generate a reception window function which is slightly wider than the actual reception slot. Then, at the time of frame synchronous reception of FIG. 3 (1), this reception window function (FIG. 3 (2)) is supplied to the second switch 8 as a control signal, and the reception slot data of its own station (FIG.
Only (3)) is loaded into the RAM 10 (Fig. 3 (4)).

Next, the operation of the frame synchronization reception after the frame synchronization acquisition is completed and the reception time of the reception slot of the own station is defined by the reception window function will be described.

At the time of frame-synchronized reception, the first time in FIG.
Switch 11 is opened and the receiving window function generator 9
According to the reception window function signal from, the second switch 8 is closed while the signal is H, and the output X (nT of the A / D converters 6 and 7 is
s) and Y (nTs) are stored in the RAM 10. As shown in FIG. 3, during the period when the reception window function (FIG. 3 (2)) is H, 1/2 symbol before and after the length of the reception slot of the own station.
A margin of (T / 2) shall be provided. Further, here, as shown in FIG. 3 (4), the format of the reception slot data stored in the RAM 10 is assumed as follows.

The received sample data of the in-phase component and the quadrature component stored in the RAM 10 are X (0), X (Ts), ..., X ((2N + L) MTs) Y (0), Y (Ts ), ..., Y ((2N + L) MTs) each (2N + L) M + 1 samples.

Of the received sample data stored in the RAM 10, the symbol data at the actual identification point is X (kT + (M / 2) Ts) (k = 0, 1, ..., 2N + L
-1) Y (kT + (M / 2) Ts) (k = 0, 1, ………, 2N + L
−1) (T = MTs, oversampling ratio M is an even number), each of which is 2N + L symbols, of which k = 0,
1, ………, N-1, and k = N + L, N + L + 1, ……
…, 2N + L-1 data is information symbol data
(2N symbols), k = N, N + 1, ..., N + L-1 The data at the time is assumed to be a synchronization word (L symbol).

Next, the symbol identification point is detected from the data stored in the RAM 10. That is, kT + (M / 2) Ts (k = 0, 1, ..., 2N + L described in the above assumption
-1) The time is detected. First, the sample data stored in the RAM 10 in FIG.
As shown by (3), the data is read through the third switch 12 every symbol period T, and the values are set as Xs (kT) and Ys (kT).

[0088]

Xs (kT) = X ((kM + m) Ts) = X (kT + mTs) Ys (kT) = Y ((kM + m) Ts) = Y (kT + mTs) (k = 0, 1, ..., 2N + L-1) Here, the value of m in (Equation 30) is changed (m = 0, 1, ..., M) according to the control signal from the selection circuit 16, and the sample position for each symbol period is changed. Read data while sliding. Next, Xs (kT) and Ys (kT) are input to the baseband differential detection circuit 13. In the baseband differential detection circuit 13, for Xs (kT) and Ys (kT)
Performs the operations of (Equation 31) and (Equation 32).

[0089]

(31) I (kT + mTs) = Xs (kT) Xs ((k-1) T) + Ys (k
T) Ys ((k-1) T) = X (kT + mTs) X ((k-1) T +
mTs) + Y (kT + mTs) Y ((k-1) T + mTs) (k = 0,1, ........., 2N + L-1)

[0090]

Q (kT + mTs) = Ys (kT) Xs ((k-1) T) -Xs (kT)
Ys ((k-1) T) = Y (kT + mTs) X ((k-1) T + m
Ts) -X (kT + mTs) Y ((k-1) T + mTs) (k = 0, 1, ..., 2N + L-1) As a result, the in-phase output I of the baseband differential detection circuit 13 is obtained.
(kT + mTs), the quadrature output Q (kT + mTs) has a modulation phase difference Δ of the received π / 4 shift QPSK modulated wave signal as shown in (Expression 33) and (Expression 34), as in the case of continuous reception.
Generate cosine and sine of φ (kT + mTs). However, θe is the phase error due to the frequency offset in the local oscillator 5, as in the case of (Equation 8) in the case of continuous reception.

[0091]

(33) I (kT + mTs) = COS (Δφ (kT + mTs) + θe)

[0092]

(34) Q (kT + mTs) = SIN (Δφ (kT + mTs) + θe)

[0093]

(35) Δφ (kT + mTs) = φ (kT + mTs) −φ
((k-1) T + mTs) In the following description, as in the case of continuous reception, a signal having an in-phase component and a quadrature component will be described as a complex signal having an in-phase component in the real part and an quadrature component in the imaginary part. . (Number 3
3), the complex signal S (kT + m) as shown in (Formula 36) from (Formula 36)
Express as Ts).

[0094]

(36) S (kT + mTs) = I (kT + mTs) + jQ
(kT + mTs) = exp (j (Δφ (kT + mTs) + θe)) (k = 0, 1, ………, 2N + L-1) (j: imaginary number) As a result, it is shown in FIG. The received signal waveform S (kT + mTs) after the baseband differential detection of) is the received symbol data after the baseband differential detection of 2N + L symbols, as shown in FIG. 4 (2). By sliding as shown in 4 (3),
This data gives M + 1 sets of m = 0, 1, ..., M. However, as shown in FIG. 4, k =
0, 1, ..., N-1, and k = N + L, N + L + 1, ....
…, 2N + L-1 data is information symbol data
(2N symbols) and k = N, N + 1, ..., N + L-
The data at the time of 1 is the synchronization word (L symbol).

Next, the reception data S (kT + mTs) after the baseband differential detection is subjected to phase compensation in the phase compensation circuit 18 based on the initial value of the phase error set at the time of continuous reception, and is given by (Formula 37). The results shown are obtained.

[0096]

[Equation 37] Se (kT + mTs) = Ie (kT + mTs) + jQ
e (kT + mTs) = exp (j (Δφ (kT + mTs) + θer) where θer is the residual phase error caused by the difference between the phase error in the current reception slot and the initial setting value, and the output Se (kT + mTs) of the phase compensation circuit 18. Using the decision circuits 19 and 20, the phase is π / 4 when it exists in the first quadrant on the I and Q planes, and 3π / 4 when it exists in the second quadrant, as shown in FIG. If it exists in the third quadrant, it is determined to be -3π / 4, and if it exists in the fourth quadrant, it is determined to be -π / 4. As a result, (I
d + JQd) is first supplied to the correlation calculation circuit 14. on the other hand,
The sync word generation circuit 15 supplies the complex baseband signal corresponding to the known sync word to the correlation calculation circuit 14.

In the correlation calculation circuit 14, first, the determination circuit
By using the outputs of 19 and 20 and the output from the synchronization word generating circuit 15, as shown in FIG.
(kT).

[0098]

(38) Judgment value (k = 0, 1, ..., N-1, N + L, N + L + 1, ..., 2N) of the information symbol data section of Si (kT) = Se (kT + mTs)
+ L-1)

[0099]

Si (kT) = exp (jΔφ (kT)): Baseband signal value of known sync word (k = N, N + 1, ... N + L-1) Next, the symbol identification point is detected. Therefore, S (kT + mTs) and (equation 3
8), using Si (kT) of (Equation 39), as shown in FIG.
The value of is changed to m = 0, 1, ..., M, and the correlation calculation of (Equation 40), (Equation 41), (Equation 42) is performed while sliding the sample position. That is, the section of the information symbol data (k
= 0, 1, ..., N-1, N + L, N + L + 1, ..., 2N + L
For (-1), the correlation between S (kT + mTs) and Si (kT) in (Equation 38), which is the judgment value after phase compensation, is calculated, and the synchronization word section (k = N, N + 1, ... For N + L-1),
Correlation between S (kT + mTs) and Si (kT) of (Equation 39), which is the baseband signal value of the known synchronization word, and the power of the total correlation value are obtained.

[0100]

[Formula 40]

[0101]

[Formula 41]

[0102]

Equation 42] Total correlation power of the complex correlation value; | Ψt (m) | = (| Ψd (m) | + | Ψ SW (m) |) / 2 It should be noted that the correlation power | Ψt (m) | is It is a real number less than or equal to 1.
The selection circuit 16 takes in the complex correlation value Ψ _SW (m) and the correlation power | Ψt (m) | described above, and first changes the value of m and slides the sample position for each symbol period to obtain the correlation power | Ψt ( m) Observe the value of |. Now, from the above-mentioned assumption regarding the received data, kT + (M
/ 2) The time Ts is the symbol identification point.
From (6), (Equation 37), (Equation 38), and (Equation 39), the following relationship holds.

Information symbol data section: (k = 0, 1, ..., N-1, N + L, N + L + 1, ..., 2N + L
-1)

[0104]

S (kT + (M / 2) Ts) = exp (j (Δφ (kT
+ (M / 2) Ts) + θe))

[0105]

Si (kT) = exp (j (Δφ (kT + (M / 2) Ts) + εe)) (Δφ (kT) + (M / 2) Ts) = ± π / 4, ± 3π / 4; Correct symbol judgment value) (εe = 0 or ± π / 2) ・ Synchronization word section: (k = N, N + 1, ………, N + L−
1)

[0106]

S (kT + (M / 2) Ts) = exp (j (Δφ (k
T) + θe))

[0107]

Si (kT) = exp (jΔφ (kT)) where εe in (Equation 44) is the output Se of the phase compensation circuit 18.
(kT + (M / 2) Ts) is an error amount caused by a determination error caused by the phase error θer included in

[0108]

[Outer 1]

Therefore, the correlation power | Ψt (M / 2) | at the sample position where m = M / 2 is (Equation 40), (Equation 41), (Equation 42)
Than,

[0110]

[Equation 47]

[0111]

[Equation 48]

[0112]

| Ψt (M / 2) | = (| Ψd (M / 2) | + | Ψ
_SW (M / 2) |) / 2 = 1 and takes the maximum value as shown in FIG. 4 (4). Selection circuit 1
In 6, when the correlation power | Ψt (m) | takes the maximum value exceeding the threshold value S, the sample position of the value of m at that time is determined as the symbol identification point. That is, here, m = M
It is determined that the sample position of / 2 is the symbol identification point. Then, the value of m at the symbol identification point is supplied as a control signal to the third switch 12, and the received data is controlled to be sampled at the symbol identification point.

Further, the complex correlation value Ψ at the sample position where m = M / 2 where the correlation power | Ψt (m) | takes the maximum value.
_SW (M / 2) gives information on the phase error θe due to the frequency offset as shown in (Equation 48). (Formula 48) Ψ _SW (M
/ 2) is supplied to the inter-slot averaging circuit 17 as information on the estimated value of the phase error in the current reception slot.

[0114]

[Outside 2]

[0115]

[Equation 50]

On the other hand, the received data S (kT (MT
/ 2) Ts) has a phase error θe in a certain direction due to the influence of the frequency offset in the phase diagram on the I and Q planes as shown in FIG. The phase compensation circuit 18 receives the phase error information Ψa (n) supplied from the inter-slot averaging circuit 17.
Is used to perform the calculation represented by (Equation 51) for S (kT (M / 2) Ts), thereby realizing compensation of the phase error θe, that is, automatic frequency control (AFC).

[0117]

[Equation 51]

The phase compensation circuit 18 has a compensation range of -π <θe <π (-fR / 2 <Δf <fR / 2) when noise is zero. Output Se of phase compensation circuit 18 (kT + (M / 2) Ts)
5 using the decision circuits 19 and 20, Δφ = π / 4 when present in the first quadrant on the I and Q planes, Δφ = 3π / 4 when present in the second quadrant, When it exists in the third quadrant, it is determined that Δφ = −3π / 4, and when it exists in the fourth quadrant, Δφ = −π / 4. Then, the decision circuits 19 and 20
The output of is converted into binary serial data by the decoder 21 and output from the reception data output terminal 22.

As described above, according to this embodiment, at the time of frame synchronization reception, the section of the synchronization word of the reception data is distorted due to the influence of noise and fading, and the complex correlation value Ψ _SW (m) of (Formula 41) Even if the value of becomes smaller, as can be seen from the correlation power | Ψt (m) | of (Equation 42), if the judgment value of the information symbol data is correct, the correlation power | Ψt (m) for the section of the information symbol data The value of | compensates for the influence of the distortion in the sync word and enables the detection of discrimination points. Furthermore, the estimated value of the phase error caused by the frequency offset is also averaged using the estimated values obtained in the past reception slots as shown in the average value Ψa (n) of (Equation 50), so that the current reception Even if the estimated value in the slot is deteriorated, its influence is compensated, and good automatic frequency control (AFC) can be performed.

[0120]

As described above, the TDMA of the present invention.
The data receiving device, with respect to the received data after the baseband differential detection, not only the section of the synchronization word but also the section of the information symbol data is correlated with the determination value thereof, so that the reception data of the received data is affected by noise or fading. Even if the section of the synchronization word is distorted, if the determination value of the information symbol data is correct, the correlation value for the section of the information symbol data compensates for the influence of the distortion in the synchronization word and enables the identification point detection. Furthermore, even if the estimated value of the phase error due to the frequency offset is averaged using the estimated values obtained in the past receiving slots, even if the estimated value in the current receiving slot is degraded, its effect Good automatic frequency control (AFC)
It can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a TDMA data receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a procedure of frame synchronization acquisition at the time of continuous reception in FIGS.

FIG. 3 is a format diagram of received data stored in a RAM at the time of frame synchronous reception of FIGS. 1 and 7.

FIG. 4 is a diagram showing the procedure of the correlation calculation of FIG.

5 is a phase diagram of the output of the decision circuit of FIGS. 1 and 7. FIG.

6 is a phase diagram when affected by the frequency offset of FIGS. 1 and 7. FIG.

FIG. 7 is a block diagram showing a configuration of a conventional TDMA data receiving device.

8 is a diagram showing a procedure of the correlation calculation of FIG.

[Explanation of symbols]

1 ... Antenna, 2 ... Reception root Nyquist bandpass filter (RNBPF), 3 ... Limiter amplifier, 4 ...
Quadrature detector, 5 ... Local oscillator, 6, 7 ... A / D converter, 8 ... Second switch (SW), 11 ... First switch (SW), 12 ... Third switch (SW), 9 ... Reception window function generation circuit, 10 ... RAM, 13 ... Baseband delay detection circuit, 14 ... Correlation calculation circuit, 15 ... Synchronization word generation circuit, 16 ... Selection circuit, 17 ... Slot averaging circuit,
18 ... Phase compensation circuit, 19, 20 ... Judgment circuit, 21 ... Decoder, 22 ... Received data output terminal.

Claims (1)

[Claims] 1. At the time of frame synchronous reception, by correlating the received data after baseband differential detection with a known synchronous word, the phase error caused by the detection of the symbol identification point and the frequency offset is compensated, and the automatic frequency is corrected. In a TDMA data receiving device that performs control, in order to suppress the variation in the phase error θe due to the frequency offset estimated by the selection circuit between the receiving slots and improve the estimation accuracy of the phase error θe, Between the selection circuit and the phase compensation circuit, an inter-slot averaging circuit that calculates an average value of the values of the phase error θe between slots and supplies the result to the phase compensation circuit as an estimated value of the phase error θe And a TDMA data receiving device.