JPH0313766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width discrimination circuit, and provides a pulse width discrimination circuit that can extract pulses having a predetermined pulse width or more from a digital time series signal by using a reversible counter having a counting stop function. The purpose is to

BACKGROUND ART Conventionally, there has been a desire for a digital pulse width discriminator circuit that can extract pulse widths greater than a predetermined value from a digital time-series signal in which various pulse widths are synthesized in a time-series manner without being affected by noise or the like.

The present invention satisfies the above requirements, and one embodiment thereof will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the pulse width discrimination circuit according to the present invention, and FIGS. 2A to 2L are signal waveform diagrams for explaining the operation of the circuit shown in the first diagram. In this example,
For convenience of explanation, a composite synchronization signal separated from a video signal reproduced from a recording medium such as a disk as a digital time-series signal will be explained as an example, and the pulse width to be extracted is that of the vertical synchronization signal.

In FIG. 1, reference numeral 1 denotes a clock pulse input terminal, and the clock pulse a shown in FIG. Applied to the terminal. Also 2
is the composite synchronization signal input terminal, and the composite synchronization signal b that comes from this includes noise as shown in Figure 2B, and a part of the vertical synchronization signal part V.Sy _NC is missing. It is applied to the data input terminal D of flip-flop 3. Since the clock pulse a is selected to have a cycle sufficiently smaller than the minimum pulse width that the composite synchronization signal b originally has, D
From the Q output terminal of flip-flop 3,
As shown in FIG.
The sampled signal c is extracted. This sampled signal c is applied to the up/down control input terminal U/D of the reversible counter 4, the data input terminal D of the D flip-flop 5, one input terminal of the two-input exclusive OR circuit 8, and the D flip-flop 9, which will be described later. It is applied to each of the data input terminals D.

The Q output terminal of the D flip-flop 5 is connected to the other input terminal of the exclusive OR circuit 8.
These constitute a circuit that detects the rising and falling edge portions of the sampled signal c. That is, the signal d shown in FIG. 2D is taken out from the Q output terminal of the D flip-flop 5, and the edge signal e corresponding to the rising and falling edges of the sampled signal c is taken out from the exclusive OR circuit 8. . This edge signal e is applied to a reset terminal R of a D flip-flop 7, which will be described later.

By the way, let T _D be the minimum pulse width that you want to extract from the composite synchronization signal b, and let T D be the maximum pulse width that you want to remove.
Tu, the clock pulse (sampling pulse)
If the period of a is Ts, the reversible counter 4 is an N-ary counter that satisfies the following inequality.

Tu/Ts<N<T _D /Ts In this example, since the vertical synchronization signal is extracted,
Assuming that T _D is 30 μs, Ts is 1.68 μs, and Tu is 5 μs, N is approximately selected within the range of 3 to 17.
Here, as shown in FIG. 1, the reversible counter 4 is 8
(=N) base. Furthermore, the reversible counter 4 performs an addition counting operation when the sampled signal c applied to its up/down control input terminal U/D is at a high level, and performs a subtraction counting operation when it is at a low level at the falling edge of the clock input. Do it at the edge. Furthermore, the reversible counter 4 has a disable terminal.
The counting operation is stopped while the Q output signal of the D flip-flop 7 applied to the DIS is at a high level.

As a result, the output of the first bit of the reversible counter 4 becomes as shown in FIG. 2F, the output of the second and third bits becomes as shown in FIG. It is indicated by a number between F and G. Here, when the next clock pulse a is applied after the reversible counter 4 reaches the maximum value during the addition counting operation, it outputs a carry signal i from the carry terminal CY as shown by i ₁ and i ₂ in Fig. 2 I. On the other hand, when the next clock pulse a is applied after the minimum value is reached during the subtraction counting operation, borrow signals j are outputted from the borrow terminal BRW as shown by j ₁ , j ₂ , and j ₃ in FIG. 2J.

The carry signal i and the borrow signal H j are applied to the clock input terminal of the D flip-flop 7 via an OR circuit 6. A fixed positive voltage is applied to the data input terminal D of this D flip-flop 7, and since it is configured to be reset by the edge signal e as described above, the data input terminal D of the D flip-flop 7 is Outputs a signal k as shown in
It is applied to the disable terminal DIS of the reversible counter 4 and the clock input terminal of the D flip-flop 9, respectively. As a result, the signal k stops the counting operation of the reversible counter 4 during its high level period, and at the same time, the D flip-flop 9 further samples the sampled signal c. As a result,
A signal l shown in FIG. 2L is taken out from the Q output terminal of the D flip-flop 9 and output from the output terminal 10. This output signal l has the pulse width T _D
It is the vertical synchronization signal of , and the pulse width Tu (here
For signals and noise with a pulse width of 5μs or less, see Figure 2B,
When L is compared, it is clearly removed.

Note that the present invention is not limited to the above-mentioned embodiments, and the present invention is not limited to the above-mentioned embodiments.
Only pulse widths longer than NTs (seconds) can be separated and extracted by removing pulse widths shorter than NTs (seconds).

As described above, the pulse width discriminator circuit according to the present invention converts a digital time-series signal in which two or more pulses with different pulse widths are synthesized in time series to a period sufficiently smaller than the minimum pulse width that this signal originally has. A first sampling circuit that samples and holds the value, T _D is the minimum pulse width to be separated and extracted from the digital time series signal, Tu is the maximum pulse width to be removed, and Tu is the first sampling circuit. When the sampling period is Ts, N
An N-ary reversible counter whose value satisfies the inequality Tu/Ts<N<T _D /Ts, has a counting stop function, and performs counting at the sampling frequency by controlling the output signal of the first sampling circuit. an edge detection circuit that detects an edge of the output signal of the first sampling circuit; and an edge detection circuit that stops the counting operation of the reversible counter when a carry signal or borrow signal is output from the N-ary reversible counter. The second sampling circuit consists of a counting operation control circuit that outputs a signal to cancel the suspension of counting operation in response to a signal, and a second sampling circuit that samples the output signal of the first sampling circuit with the output signal of the counting operation control circuit.
The sampling circuit can discriminately output a pulse width signal longer than NTs in the digital time series signal, and therefore, for example, it is possible to distinguish and output a signal with a pulse width longer than NTs in the digital time series signal. It has the advantage that only the vertical synchronization signal can be taken out without passing the signal, and is particularly suitable for application to a reproduced composite synchronization signal such as a video disc where the S/N is guaranteed to some extent.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the circuit of the present invention,
2A to 2L are signal waveform diagrams for explaining the operation of the first illustrated circuit, respectively. 1... Clock pulse input terminal, 2... Composite synchronization signal input terminal, 3, 5, 9, 7... D flip-flop, 4... Octal reversible counter, 10... Output terminal.

Claims (1)

[Scope of Claims] 1. A pulse width discrimination circuit that discriminates and extracts a vertical synchronization signal from a composite synchronization signal converted into a digital time series signal, which outputs a sampling signal obtained by sampling the composite synchronization signal with a sampling pulse. and a first sampling circuit that performs an addition counting operation when the sampling signal supplied from the first sampling circuit is at one level, and after reaching a maximum value during this addition counting operation, the sampling pulse When supplied, a carry signal is output, and when the sampling signal supplied from the first sampling circuit is at the other level, a subtraction counting operation is performed, and after reaching the minimum value during this subtraction counting operation, the above sampling is performed. an N-ary reversible counter that outputs a borrow signal when a pulse is supplied;
an edge detection circuit for detecting an edge signal of the sampling signal supplied from the sampling circuit; and an edge detection circuit for detecting an edge signal of the sampling signal supplied from the N-ary reversible counter; output to stop the counting operation of the N-ary reversible counter, and stop outputting the counting operation stop signal in synchronization with the start of supply of the edge signal from the edge detection circuit to stop the counting operation of the N-ary reversible counter. a counting operation control circuit for canceling the counting operation; and a second sampling circuit for outputting a vertical synchronization signal obtained by sampling the sampling signal from the first sampling circuit using a counting operation stop signal supplied from the counting operation control circuit. The period Ts of the sampling pulse is Ts<Tu<TD, where Tu is the maximum pulse width of the noise to be removed from the composite synchronization signal, TD is the pulse width of the vertical synchronization signal, and the N-ary reversible counter A pulse width discrimination circuit characterized in that the value of N satisfies the inequality Tu/Ts<N<TD/Ts.